Patrick Georgi | ac95903 | 2020-05-05 22:49:26 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
Ravi Sarawadi | efa606b | 2017-08-04 16:26:09 -0700 | [diff] [blame] | 2 | |
| 3 | #include <device/device.h> |
| 4 | #include <device/pci.h> |
| 5 | #include <device/pci_ids.h> |
| 6 | #include <intelblocks/lpc_lib.h> |
Ravi Sarawadi | efa606b | 2017-08-04 16:26:09 -0700 | [diff] [blame] | 7 | #include <soc/pm.h> |
| 8 | |
Michael Niewöhner | 74ec3ef | 2022-04-03 21:00:45 +0200 | [diff] [blame] | 9 | #include "lpc_def.h" |
| 10 | |
Subrata Banik | 8885206 | 2018-01-10 10:51:50 +0530 | [diff] [blame] | 11 | /* SoC overrides */ |
| 12 | |
Ravi Sarawadi | efa606b | 2017-08-04 16:26:09 -0700 | [diff] [blame] | 13 | /* Common weak definition, needs to be implemented in each soc LPC driver. */ |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame] | 14 | __weak void lpc_soc_init(struct device *dev) |
Ravi Sarawadi | efa606b | 2017-08-04 16:26:09 -0700 | [diff] [blame] | 15 | { |
Subrata Banik | 8885206 | 2018-01-10 10:51:50 +0530 | [diff] [blame] | 16 | /* no-op */ |
Ravi Sarawadi | efa606b | 2017-08-04 16:26:09 -0700 | [diff] [blame] | 17 | } |
| 18 | |
Subrata Banik | 8885206 | 2018-01-10 10:51:50 +0530 | [diff] [blame] | 19 | /* Fill up LPC IO resource structure inside SoC directory */ |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame] | 20 | __weak void pch_lpc_soc_fill_io_resources(struct device *dev) |
Subrata Banik | 8885206 | 2018-01-10 10:51:50 +0530 | [diff] [blame] | 21 | { |
| 22 | /* no-op */ |
| 23 | } |
| 24 | |
| 25 | void pch_lpc_add_new_resource(struct device *dev, uint8_t offset, |
| 26 | uintptr_t base, size_t size, unsigned long flags) |
| 27 | { |
| 28 | struct resource *res; |
| 29 | res = new_resource(dev, offset); |
| 30 | res->base = base; |
| 31 | res->size = size; |
| 32 | res->flags = flags; |
| 33 | } |
| 34 | |
Elyes HAOUAS | 4a13126 | 2018-09-16 17:35:48 +0200 | [diff] [blame] | 35 | static void pch_lpc_add_io_resources(struct device *dev) |
Subrata Banik | 8885206 | 2018-01-10 10:51:50 +0530 | [diff] [blame] | 36 | { |
Michael Niewöhner | 74ec3ef | 2022-04-03 21:00:45 +0200 | [diff] [blame] | 37 | uint32_t gen_io_dec; |
| 38 | uint16_t base, size; |
| 39 | |
Subrata Banik | 8885206 | 2018-01-10 10:51:50 +0530 | [diff] [blame] | 40 | /* Add the default claimed legacy IO range for the LPC device. */ |
| 41 | pch_lpc_add_new_resource(dev, 0, 0, 0x1000, IORESOURCE_IO | |
| 42 | IORESOURCE_ASSIGNED | IORESOURCE_FIXED); |
| 43 | |
Michael Niewöhner | 74ec3ef | 2022-04-03 21:00:45 +0200 | [diff] [blame] | 44 | /* LPC Generic IO Decode ranges */ |
| 45 | for (size_t i = 0; i < LPC_NUM_GENERIC_IO_RANGES; i++) { |
| 46 | gen_io_dec = pci_read_config32(dev, LPC_GENERIC_IO_RANGE(i)); |
| 47 | if (gen_io_dec & LPC_LGIR_EN) { |
| 48 | base = gen_io_dec & LPC_LGIR_ADDR_MASK; |
| 49 | size = (0x3 | ((gen_io_dec >> 16) & 0xfc)) + 1; |
| 50 | pch_lpc_add_new_resource(dev, LPC_GENERIC_IO_RANGE(i), base, size, |
| 51 | IORESOURCE_IO | IORESOURCE_ASSIGNED | |
| 52 | IORESOURCE_FIXED); |
| 53 | } |
| 54 | } |
| 55 | |
Subrata Banik | 8885206 | 2018-01-10 10:51:50 +0530 | [diff] [blame] | 56 | /* SoC IO resource overrides */ |
| 57 | pch_lpc_soc_fill_io_resources(dev); |
| 58 | } |
| 59 | |
Michael Niewöhner | 74ec3ef | 2022-04-03 21:00:45 +0200 | [diff] [blame] | 60 | static void pch_lpc_add_mmio_resources(struct device *dev) |
| 61 | { |
| 62 | /* LPC Memory Decode */ |
| 63 | uint32_t lgmr = pci_read_config32(dev, LPC_GENERIC_MEM_RANGE); |
| 64 | if (lgmr & LPC_LGMR_EN) { |
| 65 | lgmr &= LPC_LGMR_ADDR_MASK; |
| 66 | pch_lpc_add_new_resource(dev, LPC_GENERIC_MEM_RANGE, lgmr, LPC_LGMR_WINDOW_SIZE, |
| 67 | IORESOURCE_MEM | IORESOURCE_ASSIGNED | |
| 68 | IORESOURCE_FIXED | IORESOURCE_RESERVE); |
| 69 | } |
| 70 | } |
| 71 | |
Elyes HAOUAS | 4a13126 | 2018-09-16 17:35:48 +0200 | [diff] [blame] | 72 | static void pch_lpc_read_resources(struct device *dev) |
Ravi Sarawadi | efa606b | 2017-08-04 16:26:09 -0700 | [diff] [blame] | 73 | { |
| 74 | /* Get the PCI resources of this device. */ |
| 75 | pci_dev_read_resources(dev); |
| 76 | |
| 77 | /* Add IO resources to LPC. */ |
Subrata Banik | 8885206 | 2018-01-10 10:51:50 +0530 | [diff] [blame] | 78 | pch_lpc_add_io_resources(dev); |
Michael Niewöhner | 74ec3ef | 2022-04-03 21:00:45 +0200 | [diff] [blame] | 79 | |
| 80 | /* Add non-standard MMIO resources. */ |
| 81 | pch_lpc_add_mmio_resources(dev); |
Ravi Sarawadi | efa606b | 2017-08-04 16:26:09 -0700 | [diff] [blame] | 82 | } |
| 83 | |
Subrata Banik | 8885206 | 2018-01-10 10:51:50 +0530 | [diff] [blame] | 84 | static void pch_lpc_set_child_resources(struct device *dev); |
Ravi Sarawadi | efa606b | 2017-08-04 16:26:09 -0700 | [diff] [blame] | 85 | |
Subrata Banik | 8885206 | 2018-01-10 10:51:50 +0530 | [diff] [blame] | 86 | static void pch_lpc_loop_resources(struct device *dev) |
Ravi Sarawadi | efa606b | 2017-08-04 16:26:09 -0700 | [diff] [blame] | 87 | { |
| 88 | struct resource *res; |
| 89 | |
| 90 | for (res = dev->resource_list; res; res = res->next) { |
| 91 | if (res->flags & IORESOURCE_IO) |
| 92 | lpc_open_pmio_window(res->base, res->size); |
Ravi Sarawadi | efa606b | 2017-08-04 16:26:09 -0700 | [diff] [blame] | 93 | } |
Subrata Banik | 8885206 | 2018-01-10 10:51:50 +0530 | [diff] [blame] | 94 | pch_lpc_set_child_resources(dev); |
Ravi Sarawadi | efa606b | 2017-08-04 16:26:09 -0700 | [diff] [blame] | 95 | } |
| 96 | |
| 97 | /* |
| 98 | * Loop through all the child devices' resources, and open up windows to the |
| 99 | * LPC bus, as appropriate. |
| 100 | */ |
Subrata Banik | 8885206 | 2018-01-10 10:51:50 +0530 | [diff] [blame] | 101 | static void pch_lpc_set_child_resources(struct device *dev) |
Ravi Sarawadi | efa606b | 2017-08-04 16:26:09 -0700 | [diff] [blame] | 102 | { |
| 103 | struct bus *link; |
| 104 | struct device *child; |
| 105 | |
| 106 | for (link = dev->link_list; link; link = link->next) { |
| 107 | for (child = link->children; child; child = child->sibling) |
Subrata Banik | 8885206 | 2018-01-10 10:51:50 +0530 | [diff] [blame] | 108 | pch_lpc_loop_resources(child); |
Ravi Sarawadi | efa606b | 2017-08-04 16:26:09 -0700 | [diff] [blame] | 109 | } |
| 110 | } |
| 111 | |
Elyes HAOUAS | 4a13126 | 2018-09-16 17:35:48 +0200 | [diff] [blame] | 112 | static void pch_lpc_set_resources(struct device *dev) |
Ravi Sarawadi | efa606b | 2017-08-04 16:26:09 -0700 | [diff] [blame] | 113 | { |
| 114 | pci_dev_set_resources(dev); |
| 115 | |
| 116 | /* Now open up windows to devices which have declared resources. */ |
Subrata Banik | 8885206 | 2018-01-10 10:51:50 +0530 | [diff] [blame] | 117 | pch_lpc_set_child_resources(dev); |
Ravi Sarawadi | efa606b | 2017-08-04 16:26:09 -0700 | [diff] [blame] | 118 | } |
| 119 | |
Jonathan Zhang | db202ba | 2020-09-21 17:09:50 -0700 | [diff] [blame] | 120 | #if CONFIG(HAVE_ACPI_TABLES) |
| 121 | static const char *lpc_acpi_name(const struct device *dev) |
| 122 | { |
| 123 | return "LPCB"; |
| 124 | } |
| 125 | #endif |
| 126 | |
Ravi Sarawadi | efa606b | 2017-08-04 16:26:09 -0700 | [diff] [blame] | 127 | static struct device_operations device_ops = { |
Nico Huber | 68680dd | 2020-03-31 17:34:52 +0200 | [diff] [blame] | 128 | .read_resources = pch_lpc_read_resources, |
| 129 | .set_resources = pch_lpc_set_resources, |
| 130 | .enable_resources = pci_dev_enable_resources, |
Karthikeyan Ramasubramanian | 0e971e1 | 2020-01-09 11:32:16 -0700 | [diff] [blame] | 131 | #if CONFIG(HAVE_ACPI_TABLES) |
Nico Huber | 68680dd | 2020-03-31 17:34:52 +0200 | [diff] [blame] | 132 | .write_acpi_tables = southbridge_write_acpi_tables, |
Jonathan Zhang | db202ba | 2020-09-21 17:09:50 -0700 | [diff] [blame] | 133 | .acpi_name = lpc_acpi_name, |
Karthikeyan Ramasubramanian | 0e971e1 | 2020-01-09 11:32:16 -0700 | [diff] [blame] | 134 | #endif |
Nico Huber | 68680dd | 2020-03-31 17:34:52 +0200 | [diff] [blame] | 135 | .init = lpc_soc_init, |
| 136 | .scan_bus = scan_static_bus, |
| 137 | .ops_pci = &pci_dev_ops_pci, |
Ravi Sarawadi | efa606b | 2017-08-04 16:26:09 -0700 | [diff] [blame] | 138 | }; |
| 139 | |
| 140 | static const unsigned short pci_device_ids[] = { |
Wonkyu Kim | 9f40107 | 2020-11-13 15:16:32 -0800 | [diff] [blame] | 141 | PCI_DID_INTEL_MTL_ESPI_0, |
| 142 | PCI_DID_INTEL_MTL_ESPI_1, |
| 143 | PCI_DID_INTEL_MTL_ESPI_2, |
| 144 | PCI_DID_INTEL_MTL_ESPI_3, |
| 145 | PCI_DID_INTEL_MTL_ESPI_4, |
| 146 | PCI_DID_INTEL_MTL_ESPI_5, |
| 147 | PCI_DID_INTEL_MTL_ESPI_6, |
| 148 | PCI_DID_INTEL_MTL_ESPI_7, |
Bora Guvendik | a15b25f | 2022-02-28 14:43:49 -0800 | [diff] [blame] | 149 | PCI_DID_INTEL_RPP_P_ESPI_0, |
| 150 | PCI_DID_INTEL_RPP_P_ADP_P_ESPI_1, |
| 151 | PCI_DID_INTEL_RPP_P_ADP_P_ESPI_2, |
| 152 | PCI_DID_INTEL_RPP_P_ESPI_3, |
| 153 | PCI_DID_INTEL_RPP_P_ESPI_4, |
| 154 | PCI_DID_INTEL_RPP_P_ESPI_5, |
| 155 | PCI_DID_INTEL_RPP_P_ADP_M_ESPI_6, |
| 156 | PCI_DID_INTEL_RPP_P_ESPI_7, |
| 157 | PCI_DID_INTEL_RPP_P_ESPI_8, |
| 158 | PCI_DID_INTEL_RPP_P_ESPI_9, |
| 159 | PCI_DID_INTEL_RPP_P_ESPI_10, |
| 160 | PCI_DID_INTEL_RPP_P_ESPI_11, |
| 161 | PCI_DID_INTEL_RPP_P_ESPI_12, |
| 162 | PCI_DID_INTEL_RPP_P_ESPI_13, |
| 163 | PCI_DID_INTEL_RPP_P_ESPI_14, |
| 164 | PCI_DID_INTEL_RPP_P_ESPI_15, |
| 165 | PCI_DID_INTEL_RPP_P_ESPI_16, |
| 166 | PCI_DID_INTEL_RPP_P_ESPI_17, |
| 167 | PCI_DID_INTEL_RPP_P_ESPI_18, |
| 168 | PCI_DID_INTEL_RPP_P_ESPI_19, |
| 169 | PCI_DID_INTEL_RPP_P_ESPI_20, |
| 170 | PCI_DID_INTEL_RPP_P_ESPI_21, |
| 171 | PCI_DID_INTEL_RPP_P_ESPI_22, |
| 172 | PCI_DID_INTEL_RPP_P_ESPI_23, |
| 173 | PCI_DID_INTEL_RPP_P_ESPI_24, |
| 174 | PCI_DID_INTEL_RPP_P_ESPI_25, |
| 175 | PCI_DID_INTEL_RPP_P_ESPI_26, |
| 176 | PCI_DID_INTEL_RPP_P_ESPI_27, |
| 177 | PCI_DID_INTEL_RPP_P_ESPI_28, |
| 178 | PCI_DID_INTEL_RPP_P_ESPI_29, |
| 179 | PCI_DID_INTEL_RPP_P_ESPI_30, |
| 180 | PCI_DID_INTEL_RPP_P_ESPI_31, |
Maximilian Brune | 667d0f8 | 2022-08-11 12:58:06 +0200 | [diff] [blame] | 181 | PCI_DID_INTEL_RPP_S_ESPI_0, |
| 182 | PCI_DID_INTEL_RPP_S_ESPI_1, |
| 183 | PCI_DID_INTEL_RPP_S_ESPI_2, |
| 184 | PCI_DID_INTEL_RPP_S_ESPI_3, |
| 185 | PCI_DID_INTEL_RPP_S_ESPI_4, |
| 186 | PCI_DID_INTEL_RPP_S_ESPI_5, |
| 187 | PCI_DID_INTEL_RPP_S_ESPI_6, |
| 188 | PCI_DID_INTEL_RPP_S_ESPI_7, |
| 189 | PCI_DID_INTEL_RPP_S_ESPI_8, |
| 190 | PCI_DID_INTEL_RPP_S_ESPI_9, |
| 191 | PCI_DID_INTEL_RPP_S_ESPI_10, |
| 192 | PCI_DID_INTEL_RPP_S_ESPI_11, |
| 193 | PCI_DID_INTEL_RPP_S_ESPI_HM770, |
| 194 | PCI_DID_INTEL_RPP_S_ESPI_WM790, |
| 195 | PCI_DID_INTEL_RPP_S_ESPI_14, |
| 196 | PCI_DID_INTEL_RPP_S_ESPI_15, |
| 197 | PCI_DID_INTEL_RPP_S_ESPI_16, |
| 198 | PCI_DID_INTEL_RPP_S_ESPI_17, |
| 199 | PCI_DID_INTEL_RPP_S_ESPI_18, |
| 200 | PCI_DID_INTEL_RPP_S_ESPI_19, |
| 201 | PCI_DID_INTEL_RPP_S_ESPI_20, |
| 202 | PCI_DID_INTEL_RPP_S_ESPI_21, |
| 203 | PCI_DID_INTEL_RPP_S_ESPI_22, |
| 204 | PCI_DID_INTEL_RPP_S_ESPI_23, |
| 205 | PCI_DID_INTEL_RPP_S_ESPI_24, |
| 206 | PCI_DID_INTEL_RPP_S_ESPI_25, |
| 207 | PCI_DID_INTEL_RPP_S_ESPI_26, |
| 208 | PCI_DID_INTEL_RPP_S_ESPI_27, |
| 209 | PCI_DID_INTEL_RPP_S_ESPI_28, |
| 210 | PCI_DID_INTEL_RPP_S_ESPI_29, |
| 211 | PCI_DID_INTEL_RPP_S_ESPI_30, |
| 212 | PCI_DID_INTEL_RPP_S_ESPI_31, |
Felix Singer | 43b7f41 | 2022-03-07 04:34:52 +0100 | [diff] [blame] | 213 | PCI_DID_INTEL_SPT_LP_SAMPLE, |
| 214 | PCI_DID_INTEL_SPT_LP_U_BASE, |
| 215 | PCI_DID_INTEL_SPT_LP_U_PREMIUM, |
| 216 | PCI_DID_INTEL_SPT_LP_Y_PREMIUM, |
| 217 | PCI_DID_INTEL_SPT_H_H110, |
| 218 | PCI_DID_INTEL_SPT_H_H170, |
| 219 | PCI_DID_INTEL_SPT_H_Z170, |
| 220 | PCI_DID_INTEL_SPT_H_Q170, |
| 221 | PCI_DID_INTEL_SPT_H_Q150, |
| 222 | PCI_DID_INTEL_SPT_H_B150, |
| 223 | PCI_DID_INTEL_SPT_H_C236, |
| 224 | PCI_DID_INTEL_SPT_H_C232, |
| 225 | PCI_DID_INTEL_SPT_H_QM170, |
| 226 | PCI_DID_INTEL_SPT_H_HM170, |
| 227 | PCI_DID_INTEL_SPT_H_CM236, |
| 228 | PCI_DID_INTEL_SPT_H_HM175, |
| 229 | PCI_DID_INTEL_SPT_H_QM175, |
| 230 | PCI_DID_INTEL_SPT_H_CM238, |
| 231 | PCI_DID_INTEL_LWB_C621, |
| 232 | PCI_DID_INTEL_LWB_C622, |
| 233 | PCI_DID_INTEL_LWB_C624, |
| 234 | PCI_DID_INTEL_LWB_C625, |
| 235 | PCI_DID_INTEL_LWB_C626, |
| 236 | PCI_DID_INTEL_LWB_C627, |
| 237 | PCI_DID_INTEL_LWB_C628, |
| 238 | PCI_DID_INTEL_LWB_C629, |
| 239 | PCI_DID_INTEL_LWB_C621A, |
| 240 | PCI_DID_INTEL_LWB_C627A, |
| 241 | PCI_DID_INTEL_LWB_C629A, |
| 242 | PCI_DID_INTEL_LWB_C624_SUPER, |
| 243 | PCI_DID_INTEL_LWB_C627_SUPER_1, |
| 244 | PCI_DID_INTEL_LWB_C621_SUPER, |
| 245 | PCI_DID_INTEL_LWB_C627_SUPER_2, |
| 246 | PCI_DID_INTEL_LWB_C628_SUPER, |
| 247 | PCI_DID_INTEL_LWB_C621A_SUPER, |
| 248 | PCI_DID_INTEL_LWB_C627A_SUPER, |
| 249 | PCI_DID_INTEL_LWB_C629A_SUPER, |
| 250 | PCI_DID_INTEL_EMB_SUPER, |
| 251 | PCI_DID_INTEL_UPT_H_Q270, |
| 252 | PCI_DID_INTEL_UPT_H_H270, |
| 253 | PCI_DID_INTEL_UPT_H_Z270, |
| 254 | PCI_DID_INTEL_UPT_H_Q250, |
| 255 | PCI_DID_INTEL_UPT_H_B250, |
| 256 | PCI_DID_INTEL_UPT_H_Z370, |
| 257 | PCI_DID_INTEL_UPT_H_H310C, |
| 258 | PCI_DID_INTEL_UPT_H_B365, |
| 259 | PCI_DID_INTEL_SPT_LP_Y_PREMIUM_HDCP22, |
| 260 | PCI_DID_INTEL_SPT_LP_U_PREMIUM_HDCP22, |
| 261 | PCI_DID_INTEL_SPT_LP_U_BASE_HDCP22, |
| 262 | PCI_DID_INTEL_UPT_LP_SUPER_SKU, |
| 263 | PCI_DID_INTEL_UPT_LP_U_BASE, |
| 264 | PCI_DID_INTEL_UPT_LP_U_PREMIUM, |
| 265 | PCI_DID_INTEL_UPT_LP_Y_PREMIUM, |
| 266 | PCI_DID_INTEL_APL_LPC, |
| 267 | PCI_DID_INTEL_GLK_LPC, |
| 268 | PCI_DID_INTEL_GLK_ESPI, |
| 269 | PCI_DID_INTEL_CNL_BASE_U_LPC, |
| 270 | PCI_DID_INTEL_CNL_U_PREMIUM_LPC, |
| 271 | PCI_DID_INTEL_CNL_Y_PREMIUM_LPC, |
| 272 | PCI_DID_INTEL_CNP_H_LPC_H310, |
| 273 | PCI_DID_INTEL_CNP_H_LPC_H370, |
| 274 | PCI_DID_INTEL_CNP_H_LPC_Z390, |
| 275 | PCI_DID_INTEL_CNP_H_LPC_Q370, |
| 276 | PCI_DID_INTEL_CNP_H_LPC_B360, |
| 277 | PCI_DID_INTEL_CNP_H_LPC_C246, |
| 278 | PCI_DID_INTEL_CNP_H_LPC_C242, |
| 279 | PCI_DID_INTEL_CNP_H_LPC_QM370, |
| 280 | PCI_DID_INTEL_CNP_H_LPC_HM370, |
| 281 | PCI_DID_INTEL_CNP_H_LPC_CM246, |
| 282 | PCI_DID_INTEL_ICL_BASE_U_ESPI, |
| 283 | PCI_DID_INTEL_ICL_BASE_Y_ESPI, |
| 284 | PCI_DID_INTEL_ICL_U_PREMIUM_ESPI, |
| 285 | PCI_DID_INTEL_ICL_U_SUPER_U_ESPI, |
| 286 | PCI_DID_INTEL_ICL_U_SUPER_U_ESPI_REV0, |
| 287 | PCI_DID_INTEL_ICL_SUPER_Y_ESPI, |
| 288 | PCI_DID_INTEL_ICL_Y_PREMIUM_ESPI, |
| 289 | PCI_DID_INTEL_CMP_SUPER_U_LPC, |
| 290 | PCI_DID_INTEL_CMP_PREMIUM_Y_LPC, |
| 291 | PCI_DID_INTEL_CMP_PREMIUM_U_LPC, |
| 292 | PCI_DID_INTEL_CMP_BASE_U_LPC, |
| 293 | PCI_DID_INTEL_CMP_SUPER_Y_LPC, |
| 294 | PCI_DID_INTEL_CMP_H_LPC_HM470, |
| 295 | PCI_DID_INTEL_CMP_H_LPC_WM490, |
| 296 | PCI_DID_INTEL_CMP_H_LPC_QM480, |
| 297 | PCI_DID_INTEL_CMP_H_LPC_W480, |
| 298 | PCI_DID_INTEL_CMP_H_LPC_H470, |
| 299 | PCI_DID_INTEL_CMP_H_LPC_Z490, |
| 300 | PCI_DID_INTEL_CMP_H_LPC_Q470, |
| 301 | PCI_DID_INTEL_TGP_ESPI_0, |
| 302 | PCI_DID_INTEL_TGP_SUPER_U_ESPI, |
| 303 | PCI_DID_INTEL_TGP_PREMIUM_U_ESPI, |
| 304 | PCI_DID_INTEL_TGP_BASE_U_ESPI, |
| 305 | PCI_DID_INTEL_TGP_ESPI_1, |
| 306 | PCI_DID_INTEL_TGP_ESPI_2, |
| 307 | PCI_DID_INTEL_TGP_SUPER_Y_ESPI, |
| 308 | PCI_DID_INTEL_TGP_PREMIUM_Y_ESPI, |
| 309 | PCI_DID_INTEL_TGP_ESPI_3, |
| 310 | PCI_DID_INTEL_TGP_ESPI_4, |
| 311 | PCI_DID_INTEL_TGP_ESPI_5, |
| 312 | PCI_DID_INTEL_TGP_ESPI_6, |
| 313 | PCI_DID_INTEL_TGP_ESPI_7, |
| 314 | PCI_DID_INTEL_TGP_ESPI_8, |
| 315 | PCI_DID_INTEL_TGP_ESPI_9, |
| 316 | PCI_DID_INTEL_TGP_ESPI_10, |
| 317 | PCI_DID_INTEL_TGP_ESPI_11, |
| 318 | PCI_DID_INTEL_TGP_ESPI_12, |
| 319 | PCI_DID_INTEL_TGP_ESPI_13, |
| 320 | PCI_DID_INTEL_TGP_ESPI_14, |
| 321 | PCI_DID_INTEL_TGP_ESPI_15, |
| 322 | PCI_DID_INTEL_TGP_ESPI_16, |
| 323 | PCI_DID_INTEL_TGP_ESPI_17, |
| 324 | PCI_DID_INTEL_TGP_ESPI_18, |
| 325 | PCI_DID_INTEL_TGP_ESPI_19, |
| 326 | PCI_DID_INTEL_TGP_ESPI_20, |
| 327 | PCI_DID_INTEL_TGP_ESPI_21, |
| 328 | PCI_DID_INTEL_TGP_ESPI_22, |
| 329 | PCI_DID_INTEL_TGP_ESPI_23, |
| 330 | PCI_DID_INTEL_TGP_ESPI_24, |
| 331 | PCI_DID_INTEL_TGP_ESPI_25, |
| 332 | PCI_DID_INTEL_TGP_ESPI_26, |
| 333 | PCI_DID_INTEL_TGP_H_ESPI_B560, |
| 334 | PCI_DID_INTEL_TGP_H_ESPI_H510, |
| 335 | PCI_DID_INTEL_TGP_H_ESPI_H570, |
| 336 | PCI_DID_INTEL_TGP_H_ESPI_Q570, |
| 337 | PCI_DID_INTEL_TGP_H_ESPI_W580, |
| 338 | PCI_DID_INTEL_TGP_H_ESPI_Z590, |
| 339 | PCI_DID_INTEL_TGP_H_ESPI_HM570, |
| 340 | PCI_DID_INTEL_TGP_H_ESPI_QM580, |
| 341 | PCI_DID_INTEL_TGP_H_ESPI_WM590, |
| 342 | PCI_DID_INTEL_MCC_ESPI_0, |
| 343 | PCI_DID_INTEL_MCC_ESPI_1, |
| 344 | PCI_DID_INTEL_MCC_BASE_ESPI, |
| 345 | PCI_DID_INTEL_MCC_PREMIUM_ESPI, |
| 346 | PCI_DID_INTEL_MCC_SUPER_ESPI, |
| 347 | PCI_DID_INTEL_MCC_ESPI_2, |
| 348 | PCI_DID_INTEL_MCC_ESPI_3, |
| 349 | PCI_DID_INTEL_MCC_ESPI_4, |
| 350 | PCI_DID_INTEL_JSP_SUPER_ESPI, |
Maximilian Brune | 667d0f8 | 2022-08-11 12:58:06 +0200 | [diff] [blame] | 351 | PCI_DID_INTEL_ADP_S_ESPI_WM690, |
| 352 | PCI_DID_INTEL_ADP_S_ESPI_HM670, |
| 353 | PCI_DID_INTEL_ADP_S_ESPI_W685, |
| 354 | PCI_DID_INTEL_ADP_S_ESPI_W680, |
| 355 | PCI_DID_INTEL_ADP_S_ESPI_H610, |
| 356 | PCI_DID_INTEL_ADP_S_ESPI_B660, |
| 357 | PCI_DID_INTEL_ADP_S_ESPI_H670, |
| 358 | PCI_DID_INTEL_ADP_S_ESPI_Z690, |
| 359 | PCI_DID_INTEL_ADP_S_ESPI_Q670, |
Felix Singer | 43b7f41 | 2022-03-07 04:34:52 +0100 | [diff] [blame] | 360 | PCI_DID_INTEL_ADP_S_ESPI_0, |
| 361 | PCI_DID_INTEL_ADP_S_ESPI_1, |
| 362 | PCI_DID_INTEL_ADP_S_ESPI_2, |
Felix Singer | 43b7f41 | 2022-03-07 04:34:52 +0100 | [diff] [blame] | 363 | PCI_DID_INTEL_ADP_S_ESPI_9, |
Felix Singer | 43b7f41 | 2022-03-07 04:34:52 +0100 | [diff] [blame] | 364 | PCI_DID_INTEL_ADP_S_ESPI_11, |
Felix Singer | 43b7f41 | 2022-03-07 04:34:52 +0100 | [diff] [blame] | 365 | PCI_DID_INTEL_ADP_S_ESPI_14, |
| 366 | PCI_DID_INTEL_ADP_S_ESPI_15, |
Felix Singer | 43b7f41 | 2022-03-07 04:34:52 +0100 | [diff] [blame] | 367 | PCI_DID_INTEL_ADP_S_ESPI_19, |
| 368 | PCI_DID_INTEL_ADP_S_ESPI_20, |
| 369 | PCI_DID_INTEL_ADP_S_ESPI_21, |
| 370 | PCI_DID_INTEL_ADP_S_ESPI_22, |
| 371 | PCI_DID_INTEL_ADP_S_ESPI_23, |
| 372 | PCI_DID_INTEL_ADP_S_ESPI_24, |
| 373 | PCI_DID_INTEL_ADP_S_ESPI_25, |
| 374 | PCI_DID_INTEL_ADP_S_ESPI_26, |
| 375 | PCI_DID_INTEL_ADP_S_ESPI_27, |
| 376 | PCI_DID_INTEL_ADP_S_ESPI_28, |
| 377 | PCI_DID_INTEL_ADP_S_ESPI_29, |
| 378 | PCI_DID_INTEL_ADP_S_ESPI_30, |
| 379 | PCI_DID_INTEL_ADP_S_ESPI_31, |
Maximilian Brune | a0bc90e | 2022-08-08 12:30:47 +0200 | [diff] [blame] | 380 | PCI_DID_INTEL_ADP_S_ESPI_H610E, |
| 381 | PCI_DID_INTEL_ADP_S_ESPI_Q670E, |
| 382 | PCI_DID_INTEL_ADP_S_ESPI_R680E, |
Felix Singer | 43b7f41 | 2022-03-07 04:34:52 +0100 | [diff] [blame] | 383 | PCI_DID_INTEL_ADP_M_N_ESPI_0, |
| 384 | PCI_DID_INTEL_ADP_M_N_ESPI_1, |
| 385 | PCI_DID_INTEL_ADP_M_N_ESPI_2, |
| 386 | PCI_DID_INTEL_ADP_M_N_ESPI_3, |
| 387 | PCI_DID_INTEL_ADP_M_N_ESPI_4, |
| 388 | PCI_DID_INTEL_ADP_M_N_ESPI_5, |
| 389 | PCI_DID_INTEL_ADP_M_N_ESPI_7, |
| 390 | PCI_DID_INTEL_ADP_M_N_ESPI_8, |
| 391 | PCI_DID_INTEL_ADP_M_N_ESPI_9, |
| 392 | PCI_DID_INTEL_ADP_M_N_ESPI_10, |
| 393 | PCI_DID_INTEL_ADP_M_N_ESPI_11, |
| 394 | PCI_DID_INTEL_ADP_M_N_ESPI_12, |
| 395 | PCI_DID_INTEL_ADP_M_N_ESPI_13, |
| 396 | PCI_DID_INTEL_ADP_M_N_ESPI_14, |
| 397 | PCI_DID_INTEL_ADP_M_N_ESPI_15, |
| 398 | PCI_DID_INTEL_ADP_M_N_ESPI_16, |
| 399 | PCI_DID_INTEL_ADP_M_N_ESPI_17, |
| 400 | PCI_DID_INTEL_ADP_M_N_ESPI_18, |
| 401 | PCI_DID_INTEL_ADP_M_N_ESPI_19, |
| 402 | PCI_DID_INTEL_ADP_M_N_ESPI_20, |
| 403 | PCI_DID_INTEL_ADP_M_N_ESPI_21, |
| 404 | PCI_DID_INTEL_ADP_M_N_ESPI_22, |
| 405 | PCI_DID_INTEL_ADP_M_N_ESPI_23, |
| 406 | PCI_DID_INTEL_ADP_M_N_ESPI_24, |
| 407 | PCI_DID_INTEL_ADP_M_N_ESPI_25, |
| 408 | PCI_DID_INTEL_ADP_M_N_ESPI_26, |
| 409 | PCI_DID_INTEL_ADP_M_N_ESPI_27, |
| 410 | PCI_DID_INTEL_ADP_M_N_ESPI_28, |
| 411 | PCI_DID_INTEL_ADP_M_N_ESPI_29, |
| 412 | PCI_DID_INTEL_ADP_M_N_ESPI_30, |
| 413 | PCI_DID_INTEL_ADP_M_N_ESPI_31, |
Felix Singer | 43b7f41 | 2022-03-07 04:34:52 +0100 | [diff] [blame] | 414 | PCI_DID_INTEL_SPR_ESPI_1, |
Ravi Sarawadi | efa606b | 2017-08-04 16:26:09 -0700 | [diff] [blame] | 415 | 0 |
| 416 | }; |
| 417 | |
Subrata Banik | 8885206 | 2018-01-10 10:51:50 +0530 | [diff] [blame] | 418 | static const struct pci_driver pch_lpc __pci_driver = { |
Ravi Sarawadi | efa606b | 2017-08-04 16:26:09 -0700 | [diff] [blame] | 419 | .ops = &device_ops, |
Felix Singer | 43b7f41 | 2022-03-07 04:34:52 +0100 | [diff] [blame] | 420 | .vendor = PCI_VID_INTEL, |
Ravi Sarawadi | efa606b | 2017-08-04 16:26:09 -0700 | [diff] [blame] | 421 | .devices = pci_device_ids, |
| 422 | }; |