Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 1 | chip northbridge/intel/sandybridge |
Vladimir Serbinenko | dd2bc3f | 2014-10-31 09:16:31 +0100 | [diff] [blame] | 2 | # IGD Displays |
Matt DeVillier | 6269636 | 2020-03-29 13:20:59 -0500 | [diff] [blame] | 3 | register "gfx" = "GMA_STATIC_DISPLAYS(0)" |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 4 | |
| 5 | # Enable DisplayPort Hotplug with 6ms pulse |
| 6 | register "gpu_dp_d_hotplug" = "0x06" |
| 7 | |
| 8 | # Enable Panel as eDP and configure power delays |
Angel Pons | dc0c081 | 2020-09-02 19:17:30 +0200 | [diff] [blame] | 9 | register "gpu_panel_port_select" = "PANEL_PORT_DP_A" |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 10 | register "gpu_panel_power_cycle_delay" = "6" # 500ms |
| 11 | register "gpu_panel_power_up_delay" = "2000" # 200ms |
| 12 | register "gpu_panel_power_down_delay" = "500" # 50ms |
| 13 | register "gpu_panel_power_backlight_on_delay" = "2000" # 200ms |
| 14 | register "gpu_panel_power_backlight_off_delay" = "2000" # 200ms |
| 15 | |
| 16 | # Set backlight PWM values for eDP |
| 17 | register "gpu_cpu_backlight" = "0x00000200" |
| 18 | register "gpu_pch_backlight" = "0x04000000" |
| 19 | |
Keith Hui | 7039edd | 2023-07-21 10:12:05 -0400 | [diff] [blame] | 20 | register "ec_present" = "1" |
| 21 | register "ddr3lv_support" = "1" |
| 22 | # FIXME: Native raminit requires reduced max clock |
| 23 | register "max_mem_clock_mhz" = "CONFIG(USE_NATIVE_RAMINIT) ? 666 : 800" |
| 24 | |
| 25 | register "usb_port_config" = "{ |
| 26 | { 0, 3, 0x0000 }, |
| 27 | { 1, 0, 0x0040 }, |
| 28 | { 1, 1, 0x0040 }, |
| 29 | { 1, 3, 0x0040 }, |
| 30 | { 0, 3, 0x0000 }, |
| 31 | { 1, 3, 0x0040 }, |
| 32 | { 0, 3, 0x0000 }, |
| 33 | { 0, 3, 0x0000 }, |
| 34 | { 1, 4, 0x0040 }, |
| 35 | { 1, 4, 0x0040 }, |
| 36 | { 0, 4, 0x0000 }, |
| 37 | { 0, 4, 0x0000 }, |
| 38 | { 0, 4, 0x0000 }, |
| 39 | { 0, 4, 0x0000 },}" |
Vladimir Serbinenko | b2ad810 | 2016-02-10 03:07:42 +0100 | [diff] [blame] | 40 | |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 41 | device domain 0 on |
| 42 | subsystemid 0x1ae0 0xc000 inherit |
Arthur Heymans | b5df65a | 2022-11-12 14:51:49 +0100 | [diff] [blame] | 43 | device ref host_bridge on end # host bridge |
| 44 | device ref igd on end # vga controller |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 45 | |
| 46 | chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 47 | # GPI routing |
| 48 | # 0 No effect (default) |
| 49 | # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) |
| 50 | # 2 SCI (if corresponding GPIO_EN bit is also set) |
| 51 | register "alt_gp_smi_en" = "0x0100" |
| 52 | register "gpi7_routing" = "2" |
| 53 | register "gpi8_routing" = "1" |
| 54 | |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 55 | register "sata_port_map" = "0x1" |
| 56 | |
| 57 | register "sata_port0_gen3_tx" = "0x00880a7f" |
| 58 | |
| 59 | # EC range is 0x800-0x9ff |
| 60 | # Please note: you MUST not change this unless |
| 61 | # you also change romstage.c:pch_enable_lpc |
| 62 | register "gen1_dec" = "0x00fc0801" |
| 63 | register "gen2_dec" = "0x00fc0901" |
| 64 | |
| 65 | # Enable zero-based linear PCIe root port functions |
Angel Pons | af4bd56 | 2021-12-28 13:05:56 +0100 | [diff] [blame] | 66 | register "pcie_port_coalesce" = "true" |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 67 | |
Arthur Heymans | b5df65a | 2022-11-12 14:51:49 +0100 | [diff] [blame] | 68 | device ref mei1 on end # Management Engine Interface 1 |
| 69 | device ref mei2 off end # Management Engine Interface 2 |
| 70 | device ref me_ide_r off end # Management Engine IDE-R |
| 71 | device ref me_kt off end # Management Engine KT |
| 72 | device ref gbe off end # Intel Gigabit Ethernet |
| 73 | device ref ehci2 on end # USB2 EHCI #2 |
| 74 | device ref hda on end # High Definition Audio |
| 75 | device ref pcie_rp1 off end # PCIe Port #1 (WLAN remapped) |
| 76 | device ref pcie_rp2 off end # PCIe Port #2 |
| 77 | device ref pcie_rp3 on end # PCIe Port #3 (WLAN actual) |
| 78 | device ref pcie_rp4 off end # PCIe Port #4 |
| 79 | device ref pcie_rp5 off end # PCIe Port #5 |
| 80 | device ref pcie_rp6 off end # PCIe Port #6 |
| 81 | device ref pcie_rp7 off end # PCIe Port #7 |
| 82 | device ref pcie_rp8 off end # PCIe Port #8 |
| 83 | device ref ehci1 on end # USB2 EHCI #1 |
| 84 | device ref pci_bridge off end # PCI bridge |
| 85 | device ref lpc on |
Matt DeVillier | 3044af7 | 2018-08-01 13:05:14 -0500 | [diff] [blame] | 86 | chip drivers/pc80/tpm |
| 87 | device pnp 0c31.0 on end |
| 88 | end |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 89 | chip ec/google/chromeec |
| 90 | # We only have one init function that |
| 91 | # we need to call to initialize the |
| 92 | # keyboard part of the EC. |
| 93 | device pnp ff.1 on # dummy address |
| 94 | end |
| 95 | end |
| 96 | end # LPC bridge |
Arthur Heymans | b5df65a | 2022-11-12 14:51:49 +0100 | [diff] [blame] | 97 | device ref sata1 on end # SATA Controller 1 |
| 98 | device ref smbus on end # SMBus |
| 99 | device ref sata2 off end # SATA Controller 2 |
| 100 | device ref thermal on end # Thermal |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 101 | end |
| 102 | end |
| 103 | end |