| chip northbridge/intel/sandybridge |
| # IGD Displays |
| register "gfx" = "GMA_STATIC_DISPLAYS(0)" |
| |
| # Enable DisplayPort Hotplug with 6ms pulse |
| register "gpu_dp_d_hotplug" = "0x06" |
| |
| # Enable Panel as eDP and configure power delays |
| register "gpu_panel_port_select" = "PANEL_PORT_DP_A" |
| register "gpu_panel_power_cycle_delay" = "6" # 500ms |
| register "gpu_panel_power_up_delay" = "2000" # 200ms |
| register "gpu_panel_power_down_delay" = "500" # 50ms |
| register "gpu_panel_power_backlight_on_delay" = "2000" # 200ms |
| register "gpu_panel_power_backlight_off_delay" = "2000" # 200ms |
| |
| # Set backlight PWM values for eDP |
| register "gpu_cpu_backlight" = "0x00000200" |
| register "gpu_pch_backlight" = "0x04000000" |
| |
| register "ec_present" = "1" |
| register "ddr3lv_support" = "1" |
| # FIXME: Native raminit requires reduced max clock |
| register "max_mem_clock_mhz" = "CONFIG(USE_NATIVE_RAMINIT) ? 666 : 800" |
| |
| register "usb_port_config" = "{ |
| { 0, 3, 0x0000 }, |
| { 1, 0, 0x0040 }, |
| { 1, 1, 0x0040 }, |
| { 1, 3, 0x0040 }, |
| { 0, 3, 0x0000 }, |
| { 1, 3, 0x0040 }, |
| { 0, 3, 0x0000 }, |
| { 0, 3, 0x0000 }, |
| { 1, 4, 0x0040 }, |
| { 1, 4, 0x0040 }, |
| { 0, 4, 0x0000 }, |
| { 0, 4, 0x0000 }, |
| { 0, 4, 0x0000 }, |
| { 0, 4, 0x0000 },}" |
| |
| device domain 0 on |
| subsystemid 0x1ae0 0xc000 inherit |
| device ref host_bridge on end # host bridge |
| device ref igd on end # vga controller |
| |
| chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH |
| # GPI routing |
| # 0 No effect (default) |
| # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) |
| # 2 SCI (if corresponding GPIO_EN bit is also set) |
| register "alt_gp_smi_en" = "0x0100" |
| register "gpi7_routing" = "2" |
| register "gpi8_routing" = "1" |
| |
| register "sata_port_map" = "0x1" |
| |
| register "sata_port0_gen3_tx" = "0x00880a7f" |
| |
| # EC range is 0x800-0x9ff |
| # Please note: you MUST not change this unless |
| # you also change romstage.c:pch_enable_lpc |
| register "gen1_dec" = "0x00fc0801" |
| register "gen2_dec" = "0x00fc0901" |
| |
| # Enable zero-based linear PCIe root port functions |
| register "pcie_port_coalesce" = "true" |
| |
| device ref mei1 on end # Management Engine Interface 1 |
| device ref mei2 off end # Management Engine Interface 2 |
| device ref me_ide_r off end # Management Engine IDE-R |
| device ref me_kt off end # Management Engine KT |
| device ref gbe off end # Intel Gigabit Ethernet |
| device ref ehci2 on end # USB2 EHCI #2 |
| device ref hda on end # High Definition Audio |
| device ref pcie_rp1 off end # PCIe Port #1 (WLAN remapped) |
| device ref pcie_rp2 off end # PCIe Port #2 |
| device ref pcie_rp3 on end # PCIe Port #3 (WLAN actual) |
| device ref pcie_rp4 off end # PCIe Port #4 |
| device ref pcie_rp5 off end # PCIe Port #5 |
| device ref pcie_rp6 off end # PCIe Port #6 |
| device ref pcie_rp7 off end # PCIe Port #7 |
| device ref pcie_rp8 off end # PCIe Port #8 |
| device ref ehci1 on end # USB2 EHCI #1 |
| device ref pci_bridge off end # PCI bridge |
| device ref lpc on |
| chip drivers/pc80/tpm |
| device pnp 0c31.0 on end |
| end |
| chip ec/google/chromeec |
| # We only have one init function that |
| # we need to call to initialize the |
| # keyboard part of the EC. |
| device pnp ff.1 on # dummy address |
| end |
| end |
| end # LPC bridge |
| device ref sata1 on end # SATA Controller 1 |
| device ref smbus on end # SMBus |
| device ref sata2 off end # SATA Controller 2 |
| device ref thermal on end # Thermal |
| end |
| end |
| end |