Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 1 | chip northbridge/intel/sandybridge |
Vladimir Serbinenko | dd2bc3f | 2014-10-31 09:16:31 +0100 | [diff] [blame] | 2 | # IGD Displays |
Matt DeVillier | 6269636 | 2020-03-29 13:20:59 -0500 | [diff] [blame^] | 3 | register "gfx" = "GMA_STATIC_DISPLAYS(0)" |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 4 | |
| 5 | # Enable DisplayPort Hotplug with 6ms pulse |
| 6 | register "gpu_dp_d_hotplug" = "0x06" |
| 7 | |
| 8 | # Enable Panel as eDP and configure power delays |
| 9 | register "gpu_panel_port_select" = "1" # eDP_A |
| 10 | register "gpu_panel_power_cycle_delay" = "6" # 500ms |
| 11 | register "gpu_panel_power_up_delay" = "2000" # 200ms |
| 12 | register "gpu_panel_power_down_delay" = "500" # 50ms |
| 13 | register "gpu_panel_power_backlight_on_delay" = "2000" # 200ms |
| 14 | register "gpu_panel_power_backlight_off_delay" = "2000" # 200ms |
| 15 | |
| 16 | # Set backlight PWM values for eDP |
| 17 | register "gpu_cpu_backlight" = "0x00000200" |
| 18 | register "gpu_pch_backlight" = "0x04000000" |
| 19 | |
Vladimir Serbinenko | b2ad810 | 2016-02-10 03:07:42 +0100 | [diff] [blame] | 20 | register "max_mem_clock_mhz" = "666" |
| 21 | |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 22 | device cpu_cluster 0 on |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 23 | chip cpu/intel/model_206ax |
| 24 | # Magic APIC ID to locate this chip |
Arthur Heymans | 7e6946a | 2019-01-21 17:55:02 +0100 | [diff] [blame] | 25 | device lapic 0x0 on end |
Arthur Heymans | b3f2323 | 2019-01-21 17:48:55 +0100 | [diff] [blame] | 26 | device lapic 0xacac off end |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 27 | |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 28 | register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1) |
| 29 | register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3) |
| 30 | register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7) |
| 31 | |
| 32 | register "c1_battery" = "1" # ACPI(C1) = MWAIT(C1) |
| 33 | register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3) |
| 34 | register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7) |
| 35 | end |
| 36 | end |
| 37 | |
| 38 | device domain 0 on |
| 39 | subsystemid 0x1ae0 0xc000 inherit |
| 40 | device pci 00.0 on end # host bridge |
| 41 | device pci 02.0 on end # vga controller |
| 42 | |
| 43 | chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 44 | # GPI routing |
| 45 | # 0 No effect (default) |
| 46 | # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) |
| 47 | # 2 SCI (if corresponding GPIO_EN bit is also set) |
| 48 | register "alt_gp_smi_en" = "0x0100" |
| 49 | register "gpi7_routing" = "2" |
| 50 | register "gpi8_routing" = "1" |
| 51 | |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 52 | register "sata_port_map" = "0x1" |
| 53 | |
| 54 | register "sata_port0_gen3_tx" = "0x00880a7f" |
| 55 | |
| 56 | # EC range is 0x800-0x9ff |
| 57 | # Please note: you MUST not change this unless |
| 58 | # you also change romstage.c:pch_enable_lpc |
| 59 | register "gen1_dec" = "0x00fc0801" |
| 60 | register "gen2_dec" = "0x00fc0901" |
| 61 | |
| 62 | # Enable zero-based linear PCIe root port functions |
| 63 | register "pcie_port_coalesce" = "1" |
| 64 | |
Vladimir Serbinenko | 5b044ae | 2014-10-25 15:20:55 +0200 | [diff] [blame] | 65 | register "c2_latency" = "1" |
Vladimir Serbinenko | 5b044ae | 2014-10-25 15:20:55 +0200 | [diff] [blame] | 66 | |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 67 | device pci 16.0 on end # Management Engine Interface 1 |
| 68 | device pci 16.1 off end # Management Engine Interface 2 |
| 69 | device pci 16.2 off end # Management Engine IDE-R |
| 70 | device pci 16.3 off end # Management Engine KT |
| 71 | device pci 19.0 off end # Intel Gigabit Ethernet |
| 72 | device pci 1a.0 on end # USB2 EHCI #2 |
| 73 | device pci 1b.0 on end # High Definition Audio |
| 74 | device pci 1c.0 off end # PCIe Port #1 (WLAN remapped) |
| 75 | device pci 1c.1 off end # PCIe Port #2 |
| 76 | device pci 1c.2 on end # PCIe Port #3 (WLAN actual) |
| 77 | device pci 1c.3 off end # PCIe Port #4 |
| 78 | device pci 1c.4 off end # PCIe Port #5 |
| 79 | device pci 1c.5 off end # PCIe Port #6 |
| 80 | device pci 1c.6 off end # PCIe Port #7 |
| 81 | device pci 1c.7 off end # PCIe Port #8 |
| 82 | device pci 1d.0 on end # USB2 EHCI #1 |
| 83 | device pci 1e.0 off end # PCI bridge |
| 84 | device pci 1f.0 on |
Matt DeVillier | 3044af7 | 2018-08-01 13:05:14 -0500 | [diff] [blame] | 85 | chip drivers/pc80/tpm |
| 86 | device pnp 0c31.0 on end |
| 87 | end |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 88 | chip ec/google/chromeec |
| 89 | # We only have one init function that |
| 90 | # we need to call to initialize the |
| 91 | # keyboard part of the EC. |
| 92 | device pnp ff.1 on # dummy address |
| 93 | end |
| 94 | end |
| 95 | end # LPC bridge |
| 96 | device pci 1f.2 on end # SATA Controller 1 |
| 97 | device pci 1f.3 on end # SMBus |
| 98 | device pci 1f.5 off end # SATA Controller 2 |
| 99 | device pci 1f.6 on end # Thermal |
| 100 | end |
| 101 | end |
| 102 | end |