V Sowmya | c6d7166 | 2021-07-15 08:11:08 +0530 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #include <device/pci_ids.h> |
| 4 | #include <device/pci_ops.h> |
| 5 | #include <fsp/api.h> |
| 6 | #include <soc/ramstage.h> |
| 7 | #include <soc/vr_config.h> |
| 8 | #include <console/console.h> |
| 9 | #include <intelblocks/cpulib.h> |
| 10 | |
| 11 | /* |
| 12 | * VR Configurations for IA and GT domains for ADL-P SKU's. |
Curtis Chen | 150fee6 | 2021-12-21 11:51:33 +0800 | [diff] [blame] | 13 | * Per doc#627345 ADL_P Partial Intel PlatformDesignStudio Rev 2.0.0, update PD |
V Sowmya | c6d7166 | 2021-07-15 08:11:08 +0530 | [diff] [blame] | 14 | * |
| 15 | * +----------------+-----------+-------+-------+---------+-------------+----------+ |
| 16 | * | SKU | Setting | AC LL | DC LL | ICC MAX | TDC Current | TDC Time | |
| 17 | * | | |(mOhms)|(mOhms)| (A) | (A) | (msec) | |
| 18 | * +----------------+-----------+-------+-------+---------+-------------+----------+ |
| 19 | * | ADL-P 682(45W) | IA | 2.3 | 2.3 | 160 | 57 | 28000 | |
| 20 | * + +-----------+-------+-------+---------+-------------+----------+ |
Curtis Chen | 150fee6 | 2021-12-21 11:51:33 +0800 | [diff] [blame] | 21 | * | | GT | 3.2 | 3.2 | 55 | 57 | 28000 | |
V Sowmya | c6d7166 | 2021-07-15 08:11:08 +0530 | [diff] [blame] | 22 | * +----------------+-----------+-------+-------+---------+-------------+----------+ |
Curtis Chen | 150fee6 | 2021-12-21 11:51:33 +0800 | [diff] [blame] | 23 | * | ADL-P 482(45W) | IA | 2.3 | 2.3 | 120 | 47 | 28000 | |
| 24 | * + 442(45W) +-----------+-------+-------+---------+-------------+----------+ |
| 25 | * | | GT | 3.2 | 3.2 | 55 | 47 | 28000 | |
| 26 | * +----------------+-----------+-------+-------+---------+-------------+----------+ |
| 27 | * | ADL-P 682(28W) | IA | 2.3 | 2.3 | 109 | 40 | 28000 | |
V Sowmya | c6d7166 | 2021-07-15 08:11:08 +0530 | [diff] [blame] | 28 | * + +-----------+-------+-------+---------+-------------+----------+ |
Curtis Chen | 150fee6 | 2021-12-21 11:51:33 +0800 | [diff] [blame] | 29 | * | | GT | 3.2 | 3.2 | 55 | 40 | 28000 | |
| 30 | * +----------------+-----------+-------+-------+---------+-------------+----------+ |
| 31 | * | ADL-P 482(28W) | IA | 2.3 | 2.3 | 85 | 32 | 28000 | |
Patrick Rudolph | 4f37cf0 | 2023-03-15 15:32:26 +0100 | [diff] [blame] | 32 | * + 442(28W) +-----------+-------+-------+---------+-------------+----------+ |
Curtis Chen | 150fee6 | 2021-12-21 11:51:33 +0800 | [diff] [blame] | 33 | * | | GT | 3.2 | 3.2 | 55 | 32 | 28000 | |
V Sowmya | c6d7166 | 2021-07-15 08:11:08 +0530 | [diff] [blame] | 34 | * +----------------+-----------+-------+-------+---------+-------------+----------+ |
| 35 | * | ADL-P 282(15W) | IA | 2.8 | 2.8 | 80 | 20 | 28000 | |
| 36 | * + +-----------+-------+-------+---------+-------------+----------+ |
| 37 | * | | GT | 3.2 | 3.2 | 40 | 20 | 28000 | |
| 38 | * +----------------+-----------+-------+-------+---------+-------------+----------+ |
| 39 | */ |
| 40 | |
V Sowmya | 7de81d5 | 2022-04-05 14:45:36 +0530 | [diff] [blame] | 41 | /* |
| 42 | * VR Configurations for IA and GT domains for ADL-N SKU's. |
| 43 | * Per doc#646929 ADL N Platform Design Guide -> Power_Map_Rev1p0 |
| 44 | * |
| 45 | * +----------------+-----------+-------+-------+---------+-------------+----------+ |
| 46 | * | SKU | Setting | AC LL | DC LL | ICC MAX | TDC Current | TDC Time | |
| 47 | * | | |(mOhms)|(mOhms)| (A) | (A) | (msec) | |
| 48 | * +----------------+-----------+-------+-------+---------+-------------+----------+ |
| 49 | * | ADL-N 081(15W) | IA | 4.7 | 4.7 | 53 | 22 | 28000 | |
| 50 | * + +-----------+-------+-------+---------+-------------+----------+ |
| 51 | * | | GT | 6.5 | 6.5 | 29 | 22 | 28000 | |
| 52 | * +----------------+-----------+-------+-------+---------+-------------+----------+ |
| 53 | * | ADL-N 081(7W) | IA | 5.0 | 5.0 | 37 | 14 | 28000 | |
| 54 | * + +-----------+-------+-------+---------+-------------+----------+ |
| 55 | * | | GT | 6.5 | 6.5 | 29 | 14 | 28000 | |
| 56 | * +----------------+-----------+-------+-------+---------+-------------+----------+ |
| 57 | * | ADL-N 041(6W) | IA | 5.0 | 5.0 | 37 | 12 | 28000 | |
| 58 | * + Pentium +-----------+-------+-------+---------+-------------+----------+ |
| 59 | * | | GT | 6.5 | 6.5 | 29 | 12 | 28000 | |
| 60 | * +----------------+-----------+-------+-------+---------+-------------+----------+ |
| 61 | * | ADL-N 041(6W) | IA | 5.0 | 5.0 | 37 | 12 | 28000 | |
| 62 | * + Celeron +-----------+-------+-------+---------+-------------+----------+ |
| 63 | * | | GT | 6.5 | 6.5 | 26 | 12 | 28000 | |
| 64 | * +----------------+-----------+-------+-------+---------+-------------+----------+ |
| 65 | * | ADL-N 021(6W) | IA | 5.0 | 5.0 | 27 | 10 | 28000 | |
| 66 | * + +-----------+-------+-------+---------+-------------+----------+ |
| 67 | * | | GT | 6.5 | 6.5 | 23 | 10 | 28000 | |
| 68 | * +----------------+-----------+-------+-------+---------+-------------+----------+ |
| 69 | */ |
| 70 | |
Jeremy Compostella | 1b44c81 | 2022-06-17 15:18:02 -0700 | [diff] [blame] | 71 | /* |
| 72 | * VR Configurations for IA and GT domains for RPL-P SKU's. |
| 73 | * Per doc#686872 RPL UPH PDG - 2022, June 7th edition |
| 74 | * |
| 75 | * +----------------+-----------+-------+-------+---------+-------------+----------+ |
| 76 | * | SKU | Setting | AC LL | DC LL | ICC MAX | TDC Current | TDC Time | |
| 77 | * | | |(mOhms)|(mOhms)| (A) | (A) | (msec) | |
| 78 | * +----------------+-----------+-------+-------+---------+-------------+----------+ |
| 79 | * | RPL-P 682(45W) | IA | 2.3 | 2.3 | 160 | 86 | 28000 | |
| 80 | * + +-----------+-------+-------+---------+-------------+----------+ |
| 81 | * | | GT | 3.2 | 3.2 | 55 | 86 | 28000 | |
| 82 | * +----------------+-----------+-------+-------+---------+-------------+----------+ |
Jeremy Compostella | 0973c32 | 2023-03-27 11:57:41 -0700 | [diff] [blame] | 83 | * | RPL-P 482(28W) | IA | 2.3 | 2.3 | 102 | 33 | 28000 | |
Jeremy Compostella | 1b44c81 | 2022-06-17 15:18:02 -0700 | [diff] [blame] | 84 | * + +-----------+-------+-------+---------+-------------+----------+ |
Jeremy Compostella | 0973c32 | 2023-03-27 11:57:41 -0700 | [diff] [blame] | 85 | * | | GT | 3.2 | 3.2 | 55 | 33 | 28000 | |
Jeremy Compostella | 1b44c81 | 2022-06-17 15:18:02 -0700 | [diff] [blame] | 86 | * +----------------+-----------+-------+-------+---------+-------------+----------+ |
Jeremy Compostella | 0973c32 | 2023-03-27 11:57:41 -0700 | [diff] [blame] | 87 | * | RPL-P 282(15W) | IA | 2.8 | 2.8 | 80 | 22 | 28000 | |
Jeremy Compostella | 1b44c81 | 2022-06-17 15:18:02 -0700 | [diff] [blame] | 88 | * + +-----------+-------+-------+---------+-------------+----------+ |
Jeremy Compostella | 0973c32 | 2023-03-27 11:57:41 -0700 | [diff] [blame] | 89 | * | | GT | 3.2 | 3.2 | 40 | 22 | 28000 | |
Jeremy Compostella | 1b44c81 | 2022-06-17 15:18:02 -0700 | [diff] [blame] | 90 | * +----------------+-----------+-------+-------+---------+-------------+----------+ |
| 91 | */ |
| 92 | |
V Sowmya | c6d7166 | 2021-07-15 08:11:08 +0530 | [diff] [blame] | 93 | struct vr_lookup { |
| 94 | uint16_t mchid; |
Curtis Chen | ea1bb5f | 2021-11-25 13:17:42 +0800 | [diff] [blame] | 95 | uint8_t tdp; |
V Sowmya | c6d7166 | 2021-07-15 08:11:08 +0530 | [diff] [blame] | 96 | uint32_t conf[NUM_VR_DOMAINS]; |
| 97 | }; |
| 98 | |
| 99 | static uint32_t load_table(const struct vr_lookup *tbl, const int tbl_entries, const int domain, |
Curtis Chen | ea1bb5f | 2021-11-25 13:17:42 +0800 | [diff] [blame] | 100 | const uint16_t mch_id, uint8_t tdp) |
V Sowmya | c6d7166 | 2021-07-15 08:11:08 +0530 | [diff] [blame] | 101 | { |
| 102 | for (size_t i = 0; i < tbl_entries; i++) { |
Curtis Chen | ea1bb5f | 2021-11-25 13:17:42 +0800 | [diff] [blame] | 103 | if (tbl[i].mchid != mch_id || tbl[i].tdp != tdp) |
V Sowmya | c6d7166 | 2021-07-15 08:11:08 +0530 | [diff] [blame] | 104 | continue; |
| 105 | return tbl[i].conf[domain]; |
| 106 | } |
| 107 | |
Julius Werner | e966595 | 2022-01-21 17:06:20 -0800 | [diff] [blame] | 108 | printk(BIOS_ERR, "Unknown MCH (0x%x) in %s\n", mch_id, __func__); |
V Sowmya | c6d7166 | 2021-07-15 08:11:08 +0530 | [diff] [blame] | 109 | return 0; |
| 110 | } |
| 111 | |
Curtis Chen | 1f8563e | 2021-11-30 14:04:48 +0800 | [diff] [blame] | 112 | /* Per the power map from #613643, update ADL-P 6+8+2 (28W) VR configuration */ |
V Sowmya | c6d7166 | 2021-07-15 08:11:08 +0530 | [diff] [blame] | 113 | static const struct vr_lookup vr_config_ll[] = { |
Felix Singer | 43b7f41 | 2022-03-07 04:34:52 +0100 | [diff] [blame] | 114 | { PCI_DID_INTEL_ADL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) }, |
| 115 | { PCI_DID_INTEL_ADL_P_ID_3, 45, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) }, |
| 116 | { PCI_DID_INTEL_ADL_P_ID_4, 45, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) }, |
| 117 | { PCI_DID_INTEL_ADL_P_ID_5, 45, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) }, |
Patrick Rudolph | 4f37cf0 | 2023-03-15 15:32:26 +0100 | [diff] [blame] | 118 | { PCI_DID_INTEL_ADL_P_ID_1, 28, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) }, |
Felix Singer | 43b7f41 | 2022-03-07 04:34:52 +0100 | [diff] [blame] | 119 | { PCI_DID_INTEL_ADL_P_ID_3, 28, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) }, |
| 120 | { PCI_DID_INTEL_ADL_P_ID_5, 28, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) }, |
| 121 | { PCI_DID_INTEL_ADL_P_ID_7, 28, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) }, |
| 122 | { PCI_DID_INTEL_ADL_P_ID_6, 15, VR_CFG_ALL_DOMAINS_LOADLINE(2.8, 3.2) }, |
| 123 | { PCI_DID_INTEL_ADL_P_ID_7, 15, VR_CFG_ALL_DOMAINS_LOADLINE(2.8, 3.2) }, |
| 124 | { PCI_DID_INTEL_ADL_P_ID_10, 15, VR_CFG_ALL_DOMAINS_LOADLINE(2.8, 3.2) }, |
V Sowmya | 7de81d5 | 2022-04-05 14:45:36 +0530 | [diff] [blame] | 125 | { PCI_DID_INTEL_ADL_N_ID_1, 15, VR_CFG_ALL_DOMAINS_LOADLINE(4.7, 6.5) }, |
| 126 | { PCI_DID_INTEL_ADL_N_ID_1, 7, VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) }, |
| 127 | { PCI_DID_INTEL_ADL_N_ID_2, 6, VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) }, |
| 128 | { PCI_DID_INTEL_ADL_N_ID_3, 6, VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) }, |
| 129 | { PCI_DID_INTEL_ADL_N_ID_4, 6, VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) }, |
Sean Rhodes | 00b81ad | 2024-02-13 20:44:52 +0000 | [diff] [blame] | 130 | { PCI_DID_INTEL_ADL_N_ID_5, 6, VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) }, |
Jeremy Compostella | 1b44c81 | 2022-06-17 15:18:02 -0700 | [diff] [blame] | 131 | { PCI_DID_INTEL_RPL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) }, |
| 132 | { PCI_DID_INTEL_RPL_P_ID_2, 28, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) }, |
Tim Crawford | 198c629 | 2023-06-23 15:08:18 -0600 | [diff] [blame] | 133 | { PCI_DID_INTEL_RPL_P_ID_2, 45, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) }, |
Jeremy Compostella | 1b44c81 | 2022-06-17 15:18:02 -0700 | [diff] [blame] | 134 | { PCI_DID_INTEL_RPL_P_ID_3, 15, VR_CFG_ALL_DOMAINS_LOADLINE(2.8, 3.2) }, |
Lawrence Chang | 0a5da51 | 2022-10-19 14:38:41 +0800 | [diff] [blame] | 135 | { PCI_DID_INTEL_RPL_P_ID_4, 15, VR_CFG_ALL_DOMAINS_LOADLINE(2.8, 3.2) }, |
Marx Wang | 39ede0a | 2022-12-20 10:48:33 +0800 | [diff] [blame] | 136 | { PCI_DID_INTEL_RPL_P_ID_5, 15, VR_CFG_ALL_DOMAINS_LOADLINE(2.8, 3.2) }, |
Lean Sheng Tan | c8d4716 | 2024-03-07 17:46:25 +0100 | [diff] [blame] | 137 | { PCI_DID_INTEL_RPL_P_ID_6, 45, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) }, |
| 138 | { PCI_DID_INTEL_RPL_P_ID_7, 45, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) }, |
| 139 | { PCI_DID_INTEL_RPL_P_ID_8, 45, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) }, |
Michał Żygowski | 4b9508b | 2022-04-25 15:05:15 +0200 | [diff] [blame] | 140 | { PCI_DID_INTEL_ADL_S_ID_1, 150, VR_CFG_ALL_DOMAINS_LOADLINE(1.1, 4.0) }, |
| 141 | { PCI_DID_INTEL_ADL_S_ID_1, 125, VR_CFG_ALL_DOMAINS_LOADLINE(1.1, 4.0) }, |
| 142 | { PCI_DID_INTEL_ADL_S_ID_1, 65, VR_CFG_ALL_DOMAINS_LOADLINE(1.1, 4.0) }, |
| 143 | { PCI_DID_INTEL_ADL_S_ID_1, 35, VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) }, |
| 144 | { PCI_DID_INTEL_ADL_S_ID_3, 125, VR_CFG_ALL_DOMAINS_LOADLINE(1.1, 4.0) }, |
| 145 | { PCI_DID_INTEL_ADL_S_ID_3, 65, VR_CFG_ALL_DOMAINS_LOADLINE(1.1, 4.0) }, |
| 146 | { PCI_DID_INTEL_ADL_S_ID_3, 35, VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) }, |
| 147 | { PCI_DID_INTEL_ADL_S_ID_8, 125, VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) }, |
| 148 | { PCI_DID_INTEL_ADL_S_ID_10, 65, VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) }, |
| 149 | { PCI_DID_INTEL_ADL_S_ID_10, 35, VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) }, |
| 150 | { PCI_DID_INTEL_ADL_S_ID_11, 60, VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) }, |
| 151 | { PCI_DID_INTEL_ADL_S_ID_11, 58, VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) }, |
| 152 | { PCI_DID_INTEL_ADL_S_ID_11, 35, VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) }, |
| 153 | { PCI_DID_INTEL_ADL_S_ID_12, 46, VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) }, |
| 154 | { PCI_DID_INTEL_ADL_S_ID_12, 35, VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) }, |
Max Fritz | 573e6de | 2022-11-19 01:54:44 +0100 | [diff] [blame] | 155 | { PCI_DID_INTEL_RPL_S_ID_1, 150, VR_CFG_ALL_DOMAINS_LOADLINE(1.1, 4.0) }, |
| 156 | { PCI_DID_INTEL_RPL_S_ID_1, 125, VR_CFG_ALL_DOMAINS_LOADLINE(1.1, 4.0) }, |
| 157 | { PCI_DID_INTEL_RPL_S_ID_1, 65, VR_CFG_ALL_DOMAINS_LOADLINE(1.1, 4.0) }, |
| 158 | { PCI_DID_INTEL_RPL_S_ID_1, 35, VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) }, |
| 159 | { PCI_DID_INTEL_RPL_S_ID_3, 125, VR_CFG_ALL_DOMAINS_LOADLINE(1.1, 4.0) }, |
| 160 | { PCI_DID_INTEL_RPL_S_ID_3, 65, VR_CFG_ALL_DOMAINS_LOADLINE(1.1, 4.0) }, |
| 161 | { PCI_DID_INTEL_RPL_S_ID_3, 35, VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) }, |
| 162 | { PCI_DID_INTEL_RPL_S_ID_4, 125, VR_CFG_ALL_DOMAINS_LOADLINE(1.1, 4.0) }, |
| 163 | { PCI_DID_INTEL_RPL_S_ID_4, 65, VR_CFG_ALL_DOMAINS_LOADLINE(1.1, 4.0) }, |
| 164 | { PCI_DID_INTEL_RPL_S_ID_4, 35, VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) }, |
| 165 | { PCI_DID_INTEL_RPL_S_ID_5, 65, VR_CFG_ALL_DOMAINS_LOADLINE(1.1, 4.0) }, |
| 166 | { PCI_DID_INTEL_RPL_S_ID_5, 35, VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) }, |
Tim Crawford | 53c6eea | 2023-07-07 09:59:56 -0600 | [diff] [blame] | 167 | { PCI_DID_INTEL_RPL_HX_ID_1, 55, VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) }, |
| 168 | { PCI_DID_INTEL_RPL_HX_ID_2, 55, VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) }, |
| 169 | { PCI_DID_INTEL_RPL_HX_ID_3, 55, VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) }, |
| 170 | { PCI_DID_INTEL_RPL_HX_ID_4, 55, VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) }, |
| 171 | { PCI_DID_INTEL_RPL_HX_ID_5, 55, VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) }, |
| 172 | { PCI_DID_INTEL_RPL_HX_ID_6, 55, VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) }, |
| 173 | { PCI_DID_INTEL_RPL_HX_ID_7, 55, VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) }, |
| 174 | { PCI_DID_INTEL_RPL_HX_ID_8, 55, VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) }, |
V Sowmya | c6d7166 | 2021-07-15 08:11:08 +0530 | [diff] [blame] | 175 | }; |
| 176 | |
| 177 | static const struct vr_lookup vr_config_icc[] = { |
Felix Singer | 43b7f41 | 2022-03-07 04:34:52 +0100 | [diff] [blame] | 178 | { PCI_DID_INTEL_ADL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_ICC(120, 55) }, |
| 179 | { PCI_DID_INTEL_ADL_P_ID_3, 45, VR_CFG_ALL_DOMAINS_ICC(160, 55) }, |
| 180 | { PCI_DID_INTEL_ADL_P_ID_4, 45, VR_CFG_ALL_DOMAINS_ICC(160, 55) }, |
| 181 | { PCI_DID_INTEL_ADL_P_ID_5, 45, VR_CFG_ALL_DOMAINS_ICC(120, 55) }, |
Patrick Rudolph | 4f37cf0 | 2023-03-15 15:32:26 +0100 | [diff] [blame] | 182 | { PCI_DID_INTEL_ADL_P_ID_1, 28, VR_CFG_ALL_DOMAINS_ICC(85, 55) }, |
Felix Singer | 43b7f41 | 2022-03-07 04:34:52 +0100 | [diff] [blame] | 183 | { PCI_DID_INTEL_ADL_P_ID_3, 28, VR_CFG_ALL_DOMAINS_ICC(109, 55) }, |
| 184 | { PCI_DID_INTEL_ADL_P_ID_5, 28, VR_CFG_ALL_DOMAINS_ICC(85, 55) }, |
| 185 | { PCI_DID_INTEL_ADL_P_ID_7, 28, VR_CFG_ALL_DOMAINS_ICC(85, 55) }, |
| 186 | { PCI_DID_INTEL_ADL_P_ID_6, 15, VR_CFG_ALL_DOMAINS_ICC(80, 40) }, |
| 187 | { PCI_DID_INTEL_ADL_P_ID_7, 15, VR_CFG_ALL_DOMAINS_ICC(80, 40) }, |
| 188 | { PCI_DID_INTEL_ADL_P_ID_10, 15, VR_CFG_ALL_DOMAINS_ICC(80, 40) }, |
V Sowmya | 7de81d5 | 2022-04-05 14:45:36 +0530 | [diff] [blame] | 189 | { PCI_DID_INTEL_ADL_N_ID_1, 15, VR_CFG_ALL_DOMAINS_ICC(53, 29) }, |
| 190 | { PCI_DID_INTEL_ADL_N_ID_1, 7, VR_CFG_ALL_DOMAINS_ICC(37, 29) }, |
| 191 | { PCI_DID_INTEL_ADL_N_ID_2, 6, VR_CFG_ALL_DOMAINS_ICC(37, 29) }, |
| 192 | { PCI_DID_INTEL_ADL_N_ID_3, 6, VR_CFG_ALL_DOMAINS_ICC(37, 26) }, |
| 193 | { PCI_DID_INTEL_ADL_N_ID_4, 6, VR_CFG_ALL_DOMAINS_ICC(27, 23) }, |
Sean Rhodes | 00b81ad | 2024-02-13 20:44:52 +0000 | [diff] [blame] | 194 | { PCI_DID_INTEL_ADL_N_ID_5, 6, VR_CFG_ALL_DOMAINS_ICC(37, 29) }, |
Jeremy Compostella | 1b44c81 | 2022-06-17 15:18:02 -0700 | [diff] [blame] | 195 | { PCI_DID_INTEL_RPL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_ICC(160, 55) }, |
| 196 | { PCI_DID_INTEL_RPL_P_ID_2, 28, VR_CFG_ALL_DOMAINS_ICC(102, 55) }, |
Tim Crawford | 198c629 | 2023-06-23 15:08:18 -0600 | [diff] [blame] | 197 | { PCI_DID_INTEL_RPL_P_ID_2, 45, VR_CFG_ALL_DOMAINS_ICC(160, 55) }, |
Jeremy Compostella | 7f96c05 | 2022-08-03 09:59:16 -0700 | [diff] [blame] | 198 | { PCI_DID_INTEL_RPL_P_ID_3, 15, VR_CFG_ALL_DOMAINS_ICC(80, 40) }, |
Lawrence Chang | 0a5da51 | 2022-10-19 14:38:41 +0800 | [diff] [blame] | 199 | { PCI_DID_INTEL_RPL_P_ID_4, 15, VR_CFG_ALL_DOMAINS_ICC(80, 40) }, |
Marx Wang | 39ede0a | 2022-12-20 10:48:33 +0800 | [diff] [blame] | 200 | { PCI_DID_INTEL_RPL_P_ID_5, 15, VR_CFG_ALL_DOMAINS_ICC(80, 40) }, |
Lean Sheng Tan | c8d4716 | 2024-03-07 17:46:25 +0100 | [diff] [blame] | 201 | { PCI_DID_INTEL_RPL_P_ID_6, 45, VR_CFG_ALL_DOMAINS_ICC(160, 55) }, |
| 202 | { PCI_DID_INTEL_RPL_P_ID_7, 45, VR_CFG_ALL_DOMAINS_ICC(160, 55) }, |
| 203 | { PCI_DID_INTEL_RPL_P_ID_8, 45, VR_CFG_ALL_DOMAINS_ICC(160, 55) }, |
Michał Żygowski | 4b9508b | 2022-04-25 15:05:15 +0200 | [diff] [blame] | 204 | { PCI_DID_INTEL_ADL_S_ID_1, 150, VR_CFG_ALL_DOMAINS_ICC(280, 30) }, |
| 205 | { PCI_DID_INTEL_ADL_S_ID_1, 125, VR_CFG_ALL_DOMAINS_ICC(280, 30) }, |
| 206 | { PCI_DID_INTEL_ADL_S_ID_1, 65, VR_CFG_ALL_DOMAINS_ICC(240, 30) }, |
| 207 | { PCI_DID_INTEL_ADL_S_ID_1, 35, VR_CFG_ALL_DOMAINS_ICC(154, 30) }, |
| 208 | { PCI_DID_INTEL_ADL_S_ID_3, 125, VR_CFG_ALL_DOMAINS_ICC(240, 30) }, |
| 209 | { PCI_DID_INTEL_ADL_S_ID_3, 65, VR_CFG_ALL_DOMAINS_ICC(220, 30) }, |
| 210 | { PCI_DID_INTEL_ADL_S_ID_3, 35, VR_CFG_ALL_DOMAINS_ICC(145, 30) }, |
| 211 | { PCI_DID_INTEL_ADL_S_ID_8, 125, VR_CFG_ALL_DOMAINS_ICC(175, 30) }, |
| 212 | { PCI_DID_INTEL_ADL_S_ID_10, 65, VR_CFG_ALL_DOMAINS_ICC(151, 30) }, |
| 213 | { PCI_DID_INTEL_ADL_S_ID_10, 35, VR_CFG_ALL_DOMAINS_ICC(100, 30) }, |
| 214 | { PCI_DID_INTEL_ADL_S_ID_11, 60, VR_CFG_ALL_DOMAINS_ICC(110, 30) }, |
| 215 | { PCI_DID_INTEL_ADL_S_ID_11, 58, VR_CFG_ALL_DOMAINS_ICC(110, 30) }, |
| 216 | { PCI_DID_INTEL_ADL_S_ID_11, 35, VR_CFG_ALL_DOMAINS_ICC(90, 30) }, |
| 217 | { PCI_DID_INTEL_ADL_S_ID_12, 46, VR_CFG_ALL_DOMAINS_ICC(49, 30) }, |
| 218 | { PCI_DID_INTEL_ADL_S_ID_12, 35, VR_CFG_ALL_DOMAINS_ICC(37, 30) }, |
Max Fritz | 573e6de | 2022-11-19 01:54:44 +0100 | [diff] [blame] | 219 | { PCI_DID_INTEL_RPL_S_ID_1, 150, VR_CFG_ALL_DOMAINS_ICC(307, 30) }, |
| 220 | { PCI_DID_INTEL_RPL_S_ID_1, 125, VR_CFG_ALL_DOMAINS_ICC(307, 30) }, |
| 221 | { PCI_DID_INTEL_RPL_S_ID_1, 65, VR_CFG_ALL_DOMAINS_ICC(279, 30) }, |
| 222 | { PCI_DID_INTEL_RPL_S_ID_1, 35, VR_CFG_ALL_DOMAINS_ICC(165, 30) }, |
| 223 | { PCI_DID_INTEL_RPL_S_ID_3, 125, VR_CFG_ALL_DOMAINS_ICC(307, 30) }, |
| 224 | { PCI_DID_INTEL_RPL_S_ID_3, 65, VR_CFG_ALL_DOMAINS_ICC(279, 30) }, |
| 225 | { PCI_DID_INTEL_RPL_S_ID_3, 35, VR_CFG_ALL_DOMAINS_ICC(165, 30) }, |
| 226 | { PCI_DID_INTEL_RPL_S_ID_4, 125, VR_CFG_ALL_DOMAINS_ICC(200, 30) }, |
| 227 | { PCI_DID_INTEL_RPL_S_ID_4, 65, VR_CFG_ALL_DOMAINS_ICC(160, 30) }, |
| 228 | { PCI_DID_INTEL_RPL_S_ID_4, 35, VR_CFG_ALL_DOMAINS_ICC(120, 30) }, |
| 229 | { PCI_DID_INTEL_RPL_S_ID_5, 65, VR_CFG_ALL_DOMAINS_ICC(140, 30) }, |
| 230 | { PCI_DID_INTEL_RPL_S_ID_5, 35, VR_CFG_ALL_DOMAINS_ICC(100, 30) }, |
Tim Crawford | 53c6eea | 2023-07-07 09:59:56 -0600 | [diff] [blame] | 231 | { PCI_DID_INTEL_RPL_HX_ID_1, 55, VR_CFG_ALL_DOMAINS_ICC(215, 30) }, |
| 232 | { PCI_DID_INTEL_RPL_HX_ID_2, 55, VR_CFG_ALL_DOMAINS_ICC(215, 30) }, |
| 233 | { PCI_DID_INTEL_RPL_HX_ID_3, 55, VR_CFG_ALL_DOMAINS_ICC(215, 30) }, |
| 234 | { PCI_DID_INTEL_RPL_HX_ID_4, 55, VR_CFG_ALL_DOMAINS_ICC(160, 30) }, |
| 235 | { PCI_DID_INTEL_RPL_HX_ID_5, 55, VR_CFG_ALL_DOMAINS_ICC(160, 30) }, |
| 236 | { PCI_DID_INTEL_RPL_HX_ID_6, 55, VR_CFG_ALL_DOMAINS_ICC(215, 30) }, |
| 237 | { PCI_DID_INTEL_RPL_HX_ID_7, 55, VR_CFG_ALL_DOMAINS_ICC(160, 30) }, |
| 238 | { PCI_DID_INTEL_RPL_HX_ID_8, 55, VR_CFG_ALL_DOMAINS_ICC(160, 30) }, |
V Sowmya | c6d7166 | 2021-07-15 08:11:08 +0530 | [diff] [blame] | 239 | }; |
| 240 | |
| 241 | static const struct vr_lookup vr_config_tdc_timewindow[] = { |
Felix Singer | 43b7f41 | 2022-03-07 04:34:52 +0100 | [diff] [blame] | 242 | { PCI_DID_INTEL_ADL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, |
| 243 | { PCI_DID_INTEL_ADL_P_ID_3, 45, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, |
| 244 | { PCI_DID_INTEL_ADL_P_ID_4, 45, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, |
| 245 | { PCI_DID_INTEL_ADL_P_ID_5, 45, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, |
Patrick Rudolph | 4f37cf0 | 2023-03-15 15:32:26 +0100 | [diff] [blame] | 246 | { PCI_DID_INTEL_ADL_P_ID_1, 28, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, |
Felix Singer | 43b7f41 | 2022-03-07 04:34:52 +0100 | [diff] [blame] | 247 | { PCI_DID_INTEL_ADL_P_ID_3, 28, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, |
| 248 | { PCI_DID_INTEL_ADL_P_ID_5, 28, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, |
| 249 | { PCI_DID_INTEL_ADL_P_ID_7, 28, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, |
| 250 | { PCI_DID_INTEL_ADL_P_ID_6, 15, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, |
| 251 | { PCI_DID_INTEL_ADL_P_ID_7, 15, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, |
| 252 | { PCI_DID_INTEL_ADL_P_ID_10, 15, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, |
V Sowmya | 7de81d5 | 2022-04-05 14:45:36 +0530 | [diff] [blame] | 253 | { PCI_DID_INTEL_ADL_N_ID_1, 15, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, |
| 254 | { PCI_DID_INTEL_ADL_N_ID_1, 7, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, |
| 255 | { PCI_DID_INTEL_ADL_N_ID_2, 6, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, |
| 256 | { PCI_DID_INTEL_ADL_N_ID_3, 6, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, |
| 257 | { PCI_DID_INTEL_ADL_N_ID_4, 6, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, |
Sean Rhodes | 12781b6 | 2024-01-22 15:22:25 +0000 | [diff] [blame] | 258 | { PCI_DID_INTEL_ADL_N_ID_5, 6, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, |
Jeremy Compostella | 1b44c81 | 2022-06-17 15:18:02 -0700 | [diff] [blame] | 259 | { PCI_DID_INTEL_RPL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, |
| 260 | { PCI_DID_INTEL_RPL_P_ID_2, 28, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, |
Tim Crawford | 198c629 | 2023-06-23 15:08:18 -0600 | [diff] [blame] | 261 | { PCI_DID_INTEL_RPL_P_ID_2, 45, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, |
Jeremy Compostella | 1b44c81 | 2022-06-17 15:18:02 -0700 | [diff] [blame] | 262 | { PCI_DID_INTEL_RPL_P_ID_3, 15, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, |
Lawrence Chang | 0a5da51 | 2022-10-19 14:38:41 +0800 | [diff] [blame] | 263 | { PCI_DID_INTEL_RPL_P_ID_4, 15, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, |
Marx Wang | 39ede0a | 2022-12-20 10:48:33 +0800 | [diff] [blame] | 264 | { PCI_DID_INTEL_RPL_P_ID_5, 15, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, |
Lean Sheng Tan | c8d4716 | 2024-03-07 17:46:25 +0100 | [diff] [blame] | 265 | { PCI_DID_INTEL_RPL_P_ID_6, 45, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, |
| 266 | { PCI_DID_INTEL_RPL_P_ID_7, 45, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, |
| 267 | { PCI_DID_INTEL_RPL_P_ID_8, 45, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, |
Michał Żygowski | 4b9508b | 2022-04-25 15:05:15 +0200 | [diff] [blame] | 268 | { PCI_DID_INTEL_ADL_S_ID_1, 150, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) }, |
| 269 | { PCI_DID_INTEL_ADL_S_ID_1, 125, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) }, |
| 270 | { PCI_DID_INTEL_ADL_S_ID_1, 65, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) }, |
| 271 | { PCI_DID_INTEL_ADL_S_ID_1, 35, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) }, |
| 272 | { PCI_DID_INTEL_ADL_S_ID_3, 125, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) }, |
| 273 | { PCI_DID_INTEL_ADL_S_ID_3, 65, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) }, |
| 274 | { PCI_DID_INTEL_ADL_S_ID_3, 35, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) }, |
| 275 | { PCI_DID_INTEL_ADL_S_ID_8, 125, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) }, |
| 276 | { PCI_DID_INTEL_ADL_S_ID_10, 65, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) }, |
| 277 | { PCI_DID_INTEL_ADL_S_ID_10, 35, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) }, |
| 278 | { PCI_DID_INTEL_ADL_S_ID_11, 60, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) }, |
| 279 | { PCI_DID_INTEL_ADL_S_ID_11, 58, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) }, |
| 280 | { PCI_DID_INTEL_ADL_S_ID_11, 35, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) }, |
| 281 | { PCI_DID_INTEL_ADL_S_ID_12, 46, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) }, |
| 282 | { PCI_DID_INTEL_ADL_S_ID_12, 35, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) }, |
Max Fritz | 573e6de | 2022-11-19 01:54:44 +0100 | [diff] [blame] | 283 | { PCI_DID_INTEL_RPL_S_ID_1, 150, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) }, |
| 284 | { PCI_DID_INTEL_RPL_S_ID_1, 125, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) }, |
| 285 | { PCI_DID_INTEL_RPL_S_ID_1, 65, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) }, |
| 286 | { PCI_DID_INTEL_RPL_S_ID_1, 35, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) }, |
| 287 | { PCI_DID_INTEL_RPL_S_ID_3, 125, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) }, |
| 288 | { PCI_DID_INTEL_RPL_S_ID_3, 65, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) }, |
| 289 | { PCI_DID_INTEL_RPL_S_ID_3, 35, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) }, |
| 290 | { PCI_DID_INTEL_RPL_S_ID_4, 125, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) }, |
| 291 | { PCI_DID_INTEL_RPL_S_ID_4, 65, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) }, |
| 292 | { PCI_DID_INTEL_RPL_S_ID_4, 35, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) }, |
| 293 | { PCI_DID_INTEL_RPL_S_ID_5, 65, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) }, |
| 294 | { PCI_DID_INTEL_RPL_S_ID_5, 35, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) }, |
Tim Crawford | 53c6eea | 2023-07-07 09:59:56 -0600 | [diff] [blame] | 295 | { PCI_DID_INTEL_RPL_HX_ID_1, 55, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) }, |
| 296 | { PCI_DID_INTEL_RPL_HX_ID_2, 55, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) }, |
| 297 | { PCI_DID_INTEL_RPL_HX_ID_3, 55, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) }, |
| 298 | { PCI_DID_INTEL_RPL_HX_ID_4, 55, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) }, |
| 299 | { PCI_DID_INTEL_RPL_HX_ID_5, 55, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) }, |
| 300 | { PCI_DID_INTEL_RPL_HX_ID_6, 55, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) }, |
| 301 | { PCI_DID_INTEL_RPL_HX_ID_7, 55, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) }, |
| 302 | { PCI_DID_INTEL_RPL_HX_ID_8, 55, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) }, |
V Sowmya | c6d7166 | 2021-07-15 08:11:08 +0530 | [diff] [blame] | 303 | }; |
| 304 | |
| 305 | static const struct vr_lookup vr_config_tdc_currentlimit[] = { |
Felix Singer | 43b7f41 | 2022-03-07 04:34:52 +0100 | [diff] [blame] | 306 | { PCI_DID_INTEL_ADL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_TDC_CURRENT(47, 47) }, |
| 307 | { PCI_DID_INTEL_ADL_P_ID_3, 45, VR_CFG_ALL_DOMAINS_TDC_CURRENT(57, 57) }, |
| 308 | { PCI_DID_INTEL_ADL_P_ID_4, 45, VR_CFG_ALL_DOMAINS_TDC_CURRENT(57, 57) }, |
| 309 | { PCI_DID_INTEL_ADL_P_ID_5, 45, VR_CFG_ALL_DOMAINS_TDC_CURRENT(47, 47) }, |
Patrick Rudolph | 4f37cf0 | 2023-03-15 15:32:26 +0100 | [diff] [blame] | 310 | { PCI_DID_INTEL_ADL_P_ID_1, 28, VR_CFG_ALL_DOMAINS_TDC_CURRENT(40, 40) }, |
Felix Singer | 43b7f41 | 2022-03-07 04:34:52 +0100 | [diff] [blame] | 311 | { PCI_DID_INTEL_ADL_P_ID_3, 28, VR_CFG_ALL_DOMAINS_TDC_CURRENT(40, 40) }, |
| 312 | { PCI_DID_INTEL_ADL_P_ID_5, 28, VR_CFG_ALL_DOMAINS_TDC_CURRENT(32, 32) }, |
| 313 | { PCI_DID_INTEL_ADL_P_ID_7, 28, VR_CFG_ALL_DOMAINS_TDC_CURRENT(32, 32) }, |
| 314 | { PCI_DID_INTEL_ADL_P_ID_6, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(20, 20) }, |
| 315 | { PCI_DID_INTEL_ADL_P_ID_7, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(20, 20) }, |
| 316 | { PCI_DID_INTEL_ADL_P_ID_10, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(20, 20) }, |
V Sowmya | 7de81d5 | 2022-04-05 14:45:36 +0530 | [diff] [blame] | 317 | { PCI_DID_INTEL_ADL_N_ID_1, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(22, 22) }, |
| 318 | { PCI_DID_INTEL_ADL_N_ID_1, 7, VR_CFG_ALL_DOMAINS_TDC_CURRENT(14, 14) }, |
| 319 | { PCI_DID_INTEL_ADL_N_ID_2, 6, VR_CFG_ALL_DOMAINS_TDC_CURRENT(12, 12) }, |
| 320 | { PCI_DID_INTEL_ADL_N_ID_3, 6, VR_CFG_ALL_DOMAINS_TDC_CURRENT(12, 12) }, |
| 321 | { PCI_DID_INTEL_ADL_N_ID_4, 6, VR_CFG_ALL_DOMAINS_TDC_CURRENT(10, 10) }, |
Sean Rhodes | 12781b6 | 2024-01-22 15:22:25 +0000 | [diff] [blame] | 322 | { PCI_DID_INTEL_ADL_N_ID_5, 6, VR_CFG_ALL_DOMAINS_TDC_CURRENT(12, 12) }, |
Jeremy Compostella | 1b44c81 | 2022-06-17 15:18:02 -0700 | [diff] [blame] | 323 | { PCI_DID_INTEL_RPL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_TDC_CURRENT(86, 86) }, |
Jeremy Compostella | 0973c32 | 2023-03-27 11:57:41 -0700 | [diff] [blame] | 324 | { PCI_DID_INTEL_RPL_P_ID_2, 28, VR_CFG_ALL_DOMAINS_TDC_CURRENT(33, 33) }, |
Tim Crawford | 198c629 | 2023-06-23 15:08:18 -0600 | [diff] [blame] | 325 | { PCI_DID_INTEL_RPL_P_ID_2, 45, VR_CFG_ALL_DOMAINS_TDC_CURRENT(86, 86) }, |
Jeremy Compostella | 0973c32 | 2023-03-27 11:57:41 -0700 | [diff] [blame] | 326 | { PCI_DID_INTEL_RPL_P_ID_3, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(22, 22) }, |
| 327 | { PCI_DID_INTEL_RPL_P_ID_4, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(22, 22) }, |
| 328 | { PCI_DID_INTEL_RPL_P_ID_5, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(22, 22) }, |
Lean Sheng Tan | c8d4716 | 2024-03-07 17:46:25 +0100 | [diff] [blame] | 329 | { PCI_DID_INTEL_RPL_P_ID_6, 45, VR_CFG_ALL_DOMAINS_TDC_CURRENT(86, 86) }, |
| 330 | { PCI_DID_INTEL_RPL_P_ID_7, 45, VR_CFG_ALL_DOMAINS_TDC_CURRENT(86, 86) }, |
| 331 | { PCI_DID_INTEL_RPL_P_ID_8, 45, VR_CFG_ALL_DOMAINS_TDC_CURRENT(86, 86) }, |
Michał Żygowski | 2fffb5d | 2023-02-12 23:01:20 +0100 | [diff] [blame] | 332 | { PCI_DID_INTEL_ADL_S_ID_1, 150, VR_CFG_ALL_DOMAINS_TDC_CURRENT(132, 22) }, |
| 333 | { PCI_DID_INTEL_ADL_S_ID_1, 125, VR_CFG_ALL_DOMAINS_TDC_CURRENT(132, 22) }, |
| 334 | { PCI_DID_INTEL_ADL_S_ID_1, 65, VR_CFG_ALL_DOMAINS_TDC_CURRENT(89, 22) }, |
| 335 | { PCI_DID_INTEL_ADL_S_ID_1, 35, VR_CFG_ALL_DOMAINS_TDC_CURRENT(56, 20) }, |
| 336 | { PCI_DID_INTEL_ADL_S_ID_3, 125, VR_CFG_ALL_DOMAINS_TDC_CURRENT(109, 22) }, |
| 337 | { PCI_DID_INTEL_ADL_S_ID_3, 65, VR_CFG_ALL_DOMAINS_TDC_CURRENT(77, 22) }, |
| 338 | { PCI_DID_INTEL_ADL_S_ID_3, 35, VR_CFG_ALL_DOMAINS_TDC_CURRENT(49, 20) }, |
| 339 | { PCI_DID_INTEL_ADL_S_ID_8, 125, VR_CFG_ALL_DOMAINS_TDC_CURRENT(96, 22) }, |
| 340 | { PCI_DID_INTEL_ADL_S_ID_10, 65, VR_CFG_ALL_DOMAINS_TDC_CURRENT(66, 22) }, |
| 341 | { PCI_DID_INTEL_ADL_S_ID_10, 35, VR_CFG_ALL_DOMAINS_TDC_CURRENT(44, 20) }, |
| 342 | { PCI_DID_INTEL_ADL_S_ID_11, 60, VR_CFG_ALL_DOMAINS_TDC_CURRENT(56, 22) }, |
| 343 | { PCI_DID_INTEL_ADL_S_ID_11, 58, VR_CFG_ALL_DOMAINS_TDC_CURRENT(59, 22) }, |
| 344 | { PCI_DID_INTEL_ADL_S_ID_11, 35, VR_CFG_ALL_DOMAINS_TDC_CURRENT(40, 20) }, |
| 345 | { PCI_DID_INTEL_ADL_S_ID_12, 46, VR_CFG_ALL_DOMAINS_TDC_CURRENT(39, 20) }, |
| 346 | { PCI_DID_INTEL_ADL_S_ID_12, 35, VR_CFG_ALL_DOMAINS_TDC_CURRENT(30, 20) }, |
Max Fritz | 573e6de | 2022-11-19 01:54:44 +0100 | [diff] [blame] | 347 | { PCI_DID_INTEL_RPL_S_ID_1, 150, VR_CFG_ALL_DOMAINS_TDC_CURRENT(153, 22) }, |
| 348 | { PCI_DID_INTEL_RPL_S_ID_1, 125, VR_CFG_ALL_DOMAINS_TDC_CURRENT(140, 22) }, |
| 349 | { PCI_DID_INTEL_RPL_S_ID_1, 65, VR_CFG_ALL_DOMAINS_TDC_CURRENT(94, 22) }, |
| 350 | { PCI_DID_INTEL_RPL_S_ID_1, 35, VR_CFG_ALL_DOMAINS_TDC_CURRENT(57, 22) }, |
| 351 | { PCI_DID_INTEL_RPL_S_ID_3, 125, VR_CFG_ALL_DOMAINS_TDC_CURRENT(140, 22) }, |
| 352 | { PCI_DID_INTEL_RPL_S_ID_3, 65, VR_CFG_ALL_DOMAINS_TDC_CURRENT(94, 22) }, |
| 353 | { PCI_DID_INTEL_RPL_S_ID_3, 35, VR_CFG_ALL_DOMAINS_TDC_CURRENT(57, 22) }, |
| 354 | { PCI_DID_INTEL_RPL_S_ID_4, 125, VR_CFG_ALL_DOMAINS_TDC_CURRENT(114, 22) }, |
| 355 | { PCI_DID_INTEL_RPL_S_ID_4, 65, VR_CFG_ALL_DOMAINS_TDC_CURRENT(78, 22) }, |
| 356 | { PCI_DID_INTEL_RPL_S_ID_4, 35, VR_CFG_ALL_DOMAINS_TDC_CURRENT(51, 22) }, |
| 357 | { PCI_DID_INTEL_RPL_S_ID_5, 65, VR_CFG_ALL_DOMAINS_TDC_CURRENT(69, 22) }, |
| 358 | { PCI_DID_INTEL_RPL_S_ID_5, 35, VR_CFG_ALL_DOMAINS_TDC_CURRENT(44, 22) }, |
Tim Crawford | 53c6eea | 2023-07-07 09:59:56 -0600 | [diff] [blame] | 359 | { PCI_DID_INTEL_RPL_HX_ID_1, 55, VR_CFG_ALL_DOMAINS_TDC_CURRENT(89, 22) }, |
| 360 | { PCI_DID_INTEL_RPL_HX_ID_2, 55, VR_CFG_ALL_DOMAINS_TDC_CURRENT(89, 22) }, |
| 361 | { PCI_DID_INTEL_RPL_HX_ID_3, 55, VR_CFG_ALL_DOMAINS_TDC_CURRENT(89, 22) }, |
| 362 | { PCI_DID_INTEL_RPL_HX_ID_4, 55, VR_CFG_ALL_DOMAINS_TDC_CURRENT(89, 22) }, |
| 363 | { PCI_DID_INTEL_RPL_HX_ID_5, 55, VR_CFG_ALL_DOMAINS_TDC_CURRENT(89, 22) }, |
| 364 | { PCI_DID_INTEL_RPL_HX_ID_6, 55, VR_CFG_ALL_DOMAINS_TDC_CURRENT(89, 22) }, |
| 365 | { PCI_DID_INTEL_RPL_HX_ID_7, 55, VR_CFG_ALL_DOMAINS_TDC_CURRENT(89, 22) }, |
| 366 | { PCI_DID_INTEL_RPL_HX_ID_8, 55, VR_CFG_ALL_DOMAINS_TDC_CURRENT(89, 22) }, |
V Sowmya | c6d7166 | 2021-07-15 08:11:08 +0530 | [diff] [blame] | 367 | }; |
| 368 | |
Jeremy Compostella | 9159e1c | 2022-06-02 16:49:48 -0700 | [diff] [blame] | 369 | static void fill_vr_fast_vmode(FSP_S_CONFIG *s_cfg, |
| 370 | int domain, const struct vr_config *chip_cfg) |
| 371 | { |
Michał Żygowski | 01025d3 | 2023-07-12 13:22:09 +0200 | [diff] [blame] | 372 | #if CONFIG(SOC_INTEL_RAPTORLAKE) || CONFIG(FSP_USE_REPO) |
Jeremy Compostella | 9159e1c | 2022-06-02 16:49:48 -0700 | [diff] [blame] | 373 | s_cfg->EnableFastVmode[domain] = chip_cfg->enable_fast_vmode; |
| 374 | if (s_cfg->EnableFastVmode[domain]) |
| 375 | s_cfg->IccLimit[domain] = chip_cfg->fast_vmode_i_trip; |
| 376 | #endif |
| 377 | } |
| 378 | |
V Sowmya | c6d7166 | 2021-07-15 08:11:08 +0530 | [diff] [blame] | 379 | void fill_vr_domain_config(FSP_S_CONFIG *s_cfg, |
| 380 | int domain, const struct vr_config *chip_cfg) |
| 381 | { |
| 382 | const struct vr_config *cfg; |
| 383 | |
| 384 | if (domain < 0 || domain >= NUM_VR_DOMAINS) |
| 385 | return; |
| 386 | |
| 387 | /* Use device tree override if requested */ |
| 388 | if (chip_cfg->vr_config_enable) { |
| 389 | cfg = chip_cfg; |
| 390 | |
Bora Guvendik | f6f1258 | 2021-09-02 13:23:03 -0700 | [diff] [blame] | 391 | if (cfg->ac_loadline) |
| 392 | s_cfg->AcLoadline[domain] = cfg->ac_loadline; |
| 393 | if (cfg->dc_loadline) |
| 394 | s_cfg->DcLoadline[domain] = cfg->dc_loadline; |
| 395 | if (cfg->icc_max) |
| 396 | s_cfg->IccMax[domain] = cfg->icc_max; |
Gaggery Tsai | 517c5a8 | 2022-09-08 13:42:08 -0700 | [diff] [blame] | 397 | if (cfg->psi1threshold) |
| 398 | s_cfg->Psi1Threshold[domain] = cfg->psi1threshold; |
| 399 | if (cfg->psi2threshold) |
| 400 | s_cfg->Psi2Threshold[domain] = cfg->psi2threshold; |
| 401 | if (cfg->psi3threshold) |
| 402 | s_cfg->Psi3Threshold[domain] = cfg->psi3threshold; |
V Sowmya | c6d7166 | 2021-07-15 08:11:08 +0530 | [diff] [blame] | 403 | s_cfg->TdcTimeWindow[domain] = cfg->tdc_timewindow; |
| 404 | s_cfg->TdcCurrentLimit[domain] = cfg->tdc_currentlimit; |
V Sowmya | c6d7166 | 2021-07-15 08:11:08 +0530 | [diff] [blame] | 405 | } else { |
Curtis Chen | ea1bb5f | 2021-11-25 13:17:42 +0800 | [diff] [blame] | 406 | uint8_t tdp = get_cpu_tdp(); |
Jeremy Compostella | 14908bf | 2022-06-07 10:25:43 -0700 | [diff] [blame] | 407 | struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT); |
| 408 | uint16_t mch_id = dev ? pci_read_config16(dev, PCI_DEVICE_ID) : 0xffff; |
V Sowmya | c6d7166 | 2021-07-15 08:11:08 +0530 | [diff] [blame] | 409 | |
| 410 | s_cfg->AcLoadline[domain] = load_table(vr_config_ll, ARRAY_SIZE(vr_config_ll), |
Curtis Chen | ea1bb5f | 2021-11-25 13:17:42 +0800 | [diff] [blame] | 411 | domain, mch_id, tdp); |
V Sowmya | c6d7166 | 2021-07-15 08:11:08 +0530 | [diff] [blame] | 412 | s_cfg->DcLoadline[domain] = load_table(vr_config_ll, ARRAY_SIZE(vr_config_ll), |
Curtis Chen | ea1bb5f | 2021-11-25 13:17:42 +0800 | [diff] [blame] | 413 | domain, mch_id, tdp); |
V Sowmya | c6d7166 | 2021-07-15 08:11:08 +0530 | [diff] [blame] | 414 | s_cfg->IccMax[domain] = load_table(vr_config_icc, ARRAY_SIZE(vr_config_icc), |
Curtis Chen | ea1bb5f | 2021-11-25 13:17:42 +0800 | [diff] [blame] | 415 | domain, mch_id, tdp); |
V Sowmya | c6d7166 | 2021-07-15 08:11:08 +0530 | [diff] [blame] | 416 | s_cfg->TdcTimeWindow[domain] = load_table(vr_config_tdc_timewindow, |
| 417 | ARRAY_SIZE(vr_config_tdc_timewindow), |
Curtis Chen | ea1bb5f | 2021-11-25 13:17:42 +0800 | [diff] [blame] | 418 | domain, mch_id, tdp); |
V Sowmya | c6d7166 | 2021-07-15 08:11:08 +0530 | [diff] [blame] | 419 | s_cfg->TdcCurrentLimit[domain] = load_table(vr_config_tdc_currentlimit, |
| 420 | ARRAY_SIZE(vr_config_tdc_currentlimit), |
Curtis Chen | ea1bb5f | 2021-11-25 13:17:42 +0800 | [diff] [blame] | 421 | domain, mch_id, tdp); |
Ronak Kanabar | 1f88a71 | 2021-07-15 19:02:22 +0530 | [diff] [blame] | 422 | } |
| 423 | |
Jeremy Compostella | 9159e1c | 2022-06-02 16:49:48 -0700 | [diff] [blame] | 424 | fill_vr_fast_vmode(s_cfg, domain, chip_cfg); |
| 425 | |
Ronak Kanabar | 1f88a71 | 2021-07-15 19:02:22 +0530 | [diff] [blame] | 426 | /* Check TdcTimeWindow and TdcCurrentLimit, |
| 427 | Set TdcEnable and Set VR TDC Input current to root mean square */ |
| 428 | if (s_cfg->TdcTimeWindow[domain] != 0 && s_cfg->TdcCurrentLimit[domain] != 0) { |
| 429 | s_cfg->TdcEnable[domain] = 1; |
| 430 | s_cfg->Irms[domain] = 1; |
V Sowmya | c6d7166 | 2021-07-15 08:11:08 +0530 | [diff] [blame] | 431 | } |
| 432 | } |