Angel Pons | 4b42983 | 2020-04-02 23:48:50 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 2 | |
| 3 | |
| 4 | Name(_HID,EISAID("PNP0A08")) // PCIe |
| 5 | Name(_CID,EISAID("PNP0A03")) // PCI |
| 6 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 7 | Name(_BBN, 0) |
| 8 | |
| 9 | Device (MCHC) |
| 10 | { |
| 11 | Name(_ADR, 0x00000000) // 0:0.0 |
| 12 | |
| 13 | OperationRegion(MCHP, PCI_Config, 0x00, 0x100) |
| 14 | Field (MCHP, DWordAcc, NoLock, Preserve) |
| 15 | { |
| 16 | Offset (0x40), // EPBAR |
| 17 | EPEN, 1, // Enable |
| 18 | , 11, // |
| 19 | EPBR, 24, // EPBAR |
| 20 | |
| 21 | Offset (0x48), // MCHBAR |
| 22 | MHEN, 1, // Enable |
| 23 | , 13, // |
| 24 | MHBR, 22, // MCHBAR |
Chris Morgan | 5e5e789 | 2020-02-07 09:40:42 -0600 | [diff] [blame] | 25 | Offset (0x54), |
| 26 | DVEN, 32, |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 27 | Offset (0x60), // PCIe BAR |
| 28 | PXEN, 1, // Enable |
| 29 | PXSZ, 2, // BAR size |
| 30 | , 23, // |
| 31 | PXBR, 10, // PCIe BAR |
| 32 | |
| 33 | Offset (0x68), // DMIBAR |
| 34 | DMEN, 1, // Enable |
| 35 | , 11, // |
| 36 | DMBR, 24, // DMIBAR |
| 37 | |
| 38 | Offset (0x70), // ME Base Address |
| 39 | MEBA, 64, |
| 40 | |
| 41 | // ... |
| 42 | |
| 43 | Offset (0x80), // PAM0 |
| 44 | , 4, |
| 45 | PM0H, 2, |
| 46 | , 2, |
| 47 | Offset (0x81), // PAM1 |
| 48 | PM1L, 2, |
| 49 | , 2, |
| 50 | PM1H, 2, |
| 51 | , 2, |
| 52 | Offset (0x82), // PAM2 |
| 53 | PM2L, 2, |
| 54 | , 2, |
| 55 | PM2H, 2, |
| 56 | , 2, |
| 57 | Offset (0x83), // PAM3 |
| 58 | PM3L, 2, |
| 59 | , 2, |
| 60 | PM3H, 2, |
| 61 | , 2, |
| 62 | Offset (0x84), // PAM4 |
| 63 | PM4L, 2, |
| 64 | , 2, |
| 65 | PM4H, 2, |
| 66 | , 2, |
| 67 | Offset (0x85), // PAM5 |
| 68 | PM5L, 2, |
| 69 | , 2, |
| 70 | PM5H, 2, |
| 71 | , 2, |
| 72 | Offset (0x86), // PAM6 |
| 73 | PM6L, 2, |
| 74 | , 2, |
| 75 | PM6H, 2, |
| 76 | , 2, |
| 77 | |
| 78 | Offset (0xa0), // Top of Used Memory |
| 79 | TOM, 64, |
| 80 | |
| 81 | Offset (0xbc), // Top of Low Used Memory |
| 82 | TLUD, 32, |
| 83 | } |
| 84 | |
| 85 | Mutex (CTCM, 1) /* CTDP Switch Mutex (sync level 1) */ |
| 86 | Name (CTCC, 0) /* CTDP Current Selection */ |
| 87 | Name (CTCN, 0) /* CTDP Nominal Select */ |
| 88 | Name (CTCD, 1) /* CTDP Down Select */ |
| 89 | Name (CTCU, 2) /* CTDP Up Select */ |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame] | 90 | Name (SPL1, 0) /* Saved PL1 value */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 91 | |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame] | 92 | OperationRegion (MCHB, SystemMemory, Add(DEFAULT_MCHBAR,0x5000), 0x1000) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 93 | Field (MCHB, DWordAcc, Lock, Preserve) |
| 94 | { |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame] | 95 | Offset (0x930), /* PACKAGE_POWER_SKU */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 96 | CTDN, 15, /* CTDP Nominal PL1 */ |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame] | 97 | Offset (0x938), /* PACKAGE_POWER_SKU_UNIT */ |
| 98 | PUNI, 4, /* Power Units */ |
| 99 | , 4, |
| 100 | EUNI, 5, /* Energy Units */ |
| 101 | , 3, |
| 102 | TUNI, 4, /* Time Units */ |
| 103 | Offset (0x958), /* PLATFORM_INFO */ |
| 104 | , 40, |
| 105 | LFM_, 8, /* Maximum Efficiency Ratio (LFM) */ |
| 106 | Offset (0x9a0), /* TURBO_POWER_LIMIT1 */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 107 | PL1V, 15, /* Power Limit 1 Value */ |
| 108 | PL1E, 1, /* Power Limit 1 Enable */ |
| 109 | PL1C, 1, /* Power Limit 1 Clamp */ |
| 110 | PL1T, 7, /* Power Limit 1 Time */ |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame] | 111 | Offset (0x9a4), /* TURBO_POWER_LIMIT2 */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 112 | PL2V, 15, /* Power Limit 2 Value */ |
| 113 | PL2E, 1, /* Power Limit 2 Enable */ |
| 114 | PL2C, 1, /* Power Limit 2 Clamp */ |
| 115 | PL2T, 7, /* Power Limit 2 Time */ |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame] | 116 | Offset (0xf3c), /* CONFIG_TDP_NOMINAL */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 117 | TARN, 8, /* CTDP Nominal Turbo Activation Ratio */ |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame] | 118 | Offset (0xf40), /* CONFIG_TDP_LEVEL1 */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 119 | CTDD, 15, /* CTDP Down PL1 */ |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame] | 120 | , 1, |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 121 | TARD, 8, /* CTDP Down Turbo Activation Ratio */ |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame] | 122 | Offset (0xf48), /* MSR_CONFIG_TDP_LEVEL2 */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 123 | CTDU, 15, /* CTDP Up PL1 */ |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame] | 124 | , 1, |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 125 | TARU, 8, /* CTDP Up Turbo Activation Ratio */ |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame] | 126 | Offset (0xf50), /* CONFIG_TDP_CONTROL */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 127 | CTCS, 2, /* CTDP Select */ |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame] | 128 | Offset (0xf54), /* TURBO_ACTIVATION_RATIO */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 129 | TARS, 8, /* Turbo Activation Ratio Select */ |
| 130 | } |
| 131 | |
| 132 | /* |
Elyes HAOUAS | 69d658f | 2016-09-17 20:32:07 +0200 | [diff] [blame] | 133 | * Search CPU0 _PSS looking for control = arg0 and then |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 134 | * return previous P-state entry number for new _PPC |
| 135 | * |
| 136 | * Format of _PSS: |
| 137 | * Name (_PSS, Package () { |
| 138 | * Package (6) { freq, power, tlat, blat, control, status } |
| 139 | * } |
| 140 | */ |
Christian Walter | be3979c | 2019-12-18 15:07:59 +0100 | [diff] [blame] | 141 | External (\_SB.CP00._PSS) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 142 | Method (PSSS, 1, NotSerialized) |
| 143 | { |
Furquan Shaikh | 181e2d4 | 2020-06-01 13:03:45 -0700 | [diff] [blame^] | 144 | Local0 = One /* Start at P1 */ |
| 145 | Local1 = SizeOf (\_SB.CP00._PSS) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 146 | |
Furquan Shaikh | 181e2d4 | 2020-06-01 13:03:45 -0700 | [diff] [blame^] | 147 | While (Local0 < Local1) { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 148 | /* Store _PSS entry Control value to Local2 */ |
Furquan Shaikh | 181e2d4 | 2020-06-01 13:03:45 -0700 | [diff] [blame^] | 149 | Local2 = DeRefOf (Index (DeRefOf (Index (\_SB.CP00._PSS, Local0)), 4)) >> 8 |
| 150 | If (Local2 == Arg0) { |
| 151 | Return (Local0 - 1) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 152 | } |
Furquan Shaikh | 181e2d4 | 2020-06-01 13:03:45 -0700 | [diff] [blame^] | 153 | Local0++ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 154 | } |
| 155 | |
| 156 | Return (0) |
| 157 | } |
| 158 | |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame] | 159 | /* Calculate PL2 based on chip type */ |
| 160 | Method (CPL2, 1, NotSerialized) |
| 161 | { |
| 162 | If (\ISLP ()) { |
| 163 | /* Haswell ULT PL2 = 25W */ |
Furquan Shaikh | 181e2d4 | 2020-06-01 13:03:45 -0700 | [diff] [blame^] | 164 | Return (25 * 8) |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame] | 165 | } Else { |
| 166 | /* Haswell Mobile PL2 = 1.25 * PL1 */ |
Furquan Shaikh | 181e2d4 | 2020-06-01 13:03:45 -0700 | [diff] [blame^] | 167 | Return ((Arg0 * 125) / 100) |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame] | 168 | } |
| 169 | } |
| 170 | |
| 171 | /* Set Config TDP Down */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 172 | Method (STND, 0, Serialized) |
| 173 | { |
| 174 | If (Acquire (CTCM, 100)) { |
| 175 | Return (0) |
| 176 | } |
| 177 | If (LEqual (CTCD, CTCC)) { |
| 178 | Release (CTCM) |
| 179 | Return (0) |
| 180 | } |
| 181 | |
| 182 | Store ("Set TDP Down", Debug) |
| 183 | |
| 184 | /* Set CTC */ |
Furquan Shaikh | 181e2d4 | 2020-06-01 13:03:45 -0700 | [diff] [blame^] | 185 | CTCS = CTCD |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 186 | |
| 187 | /* Set TAR */ |
Furquan Shaikh | 181e2d4 | 2020-06-01 13:03:45 -0700 | [diff] [blame^] | 188 | TARS = TARD |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 189 | |
| 190 | /* Set PPC limit and notify OS */ |
Furquan Shaikh | 181e2d4 | 2020-06-01 13:03:45 -0700 | [diff] [blame^] | 191 | PPCM = PSSS (TARD) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 192 | PPCN () |
| 193 | |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame] | 194 | /* Set PL2 */ |
Furquan Shaikh | 181e2d4 | 2020-06-01 13:03:45 -0700 | [diff] [blame^] | 195 | PL2V = CPL2 (CTDD) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 196 | |
| 197 | /* Set PL1 */ |
Furquan Shaikh | 181e2d4 | 2020-06-01 13:03:45 -0700 | [diff] [blame^] | 198 | PL1V = CTDD |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 199 | |
| 200 | /* Store the new TDP Down setting */ |
Furquan Shaikh | 181e2d4 | 2020-06-01 13:03:45 -0700 | [diff] [blame^] | 201 | CTCC = CTCD |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 202 | |
| 203 | Release (CTCM) |
| 204 | Return (1) |
| 205 | } |
| 206 | |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame] | 207 | /* Set Config TDP Nominal from Down */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 208 | Method (STDN, 0, Serialized) |
| 209 | { |
| 210 | If (Acquire (CTCM, 100)) { |
| 211 | Return (0) |
| 212 | } |
Furquan Shaikh | 181e2d4 | 2020-06-01 13:03:45 -0700 | [diff] [blame^] | 213 | If (CTCN == CTCC) { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 214 | Release (CTCM) |
| 215 | Return (0) |
| 216 | } |
| 217 | |
| 218 | Store ("Set TDP Nominal", Debug) |
| 219 | |
| 220 | /* Set PL1 */ |
Furquan Shaikh | 181e2d4 | 2020-06-01 13:03:45 -0700 | [diff] [blame^] | 221 | PL1V = CTDN |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 222 | |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame] | 223 | /* Set PL2 */ |
Furquan Shaikh | 181e2d4 | 2020-06-01 13:03:45 -0700 | [diff] [blame^] | 224 | PL2V = CPL2 (CTDN) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 225 | |
| 226 | /* Set PPC limit and notify OS */ |
Furquan Shaikh | 181e2d4 | 2020-06-01 13:03:45 -0700 | [diff] [blame^] | 227 | PPCM = PSSS (TARN) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 228 | PPCN () |
| 229 | |
| 230 | /* Set TAR */ |
Furquan Shaikh | 181e2d4 | 2020-06-01 13:03:45 -0700 | [diff] [blame^] | 231 | TARS = TARN |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 232 | |
| 233 | /* Set CTC */ |
Furquan Shaikh | 181e2d4 | 2020-06-01 13:03:45 -0700 | [diff] [blame^] | 234 | CTCS = CTCN |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 235 | |
| 236 | /* Store the new TDP Nominal setting */ |
Furquan Shaikh | 181e2d4 | 2020-06-01 13:03:45 -0700 | [diff] [blame^] | 237 | CTCC = CTCN |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 238 | |
| 239 | Release (CTCM) |
| 240 | Return (1) |
| 241 | } |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame] | 242 | |
| 243 | /* Calculate PL1 value based on requested TDP */ |
| 244 | Method (TDPP, 1, NotSerialized) |
| 245 | { |
Furquan Shaikh | 181e2d4 | 2020-06-01 13:03:45 -0700 | [diff] [blame^] | 246 | Return (((PUNI - 1) << 2) * Arg0) |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame] | 247 | } |
| 248 | |
| 249 | /* Enable Controllable TDP to limit PL1 to requested value */ |
| 250 | Method (CTLE, 1, Serialized) |
| 251 | { |
| 252 | If (Acquire (CTCM, 100)) { |
| 253 | Return (0) |
| 254 | } |
| 255 | |
| 256 | Store ("Enable PL1 Limit", Debug) |
| 257 | |
| 258 | /* Set _PPC to LFM */ |
Furquan Shaikh | 181e2d4 | 2020-06-01 13:03:45 -0700 | [diff] [blame^] | 259 | Local0 = PSSS (LFM_) |
| 260 | PPCM = Local0 + 1 |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame] | 261 | \PPCN () |
| 262 | |
| 263 | /* Set TAR to LFM-1 */ |
Furquan Shaikh | 181e2d4 | 2020-06-01 13:03:45 -0700 | [diff] [blame^] | 264 | TARS = LFM_ - 1 |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame] | 265 | |
| 266 | /* Set PL1 to desired value */ |
Furquan Shaikh | 181e2d4 | 2020-06-01 13:03:45 -0700 | [diff] [blame^] | 267 | SPL1 = PL1V |
| 268 | PL1V = TDPP (Arg0) |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame] | 269 | |
| 270 | /* Set PL1 CLAMP bit */ |
Furquan Shaikh | 181e2d4 | 2020-06-01 13:03:45 -0700 | [diff] [blame^] | 271 | PL1C = 1 |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame] | 272 | |
| 273 | Release (CTCM) |
| 274 | Return (1) |
| 275 | } |
| 276 | |
| 277 | /* Disable Controllable TDP */ |
| 278 | Method (CTLD, 0, Serialized) |
| 279 | { |
| 280 | If (Acquire (CTCM, 100)) { |
| 281 | Return (0) |
| 282 | } |
| 283 | |
| 284 | Store ("Disable PL1 Limit", Debug) |
| 285 | |
| 286 | /* Clear PL1 CLAMP bit */ |
Furquan Shaikh | 181e2d4 | 2020-06-01 13:03:45 -0700 | [diff] [blame^] | 287 | PL1C = 0 |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame] | 288 | |
| 289 | /* Set PL1 to normal value */ |
Furquan Shaikh | 181e2d4 | 2020-06-01 13:03:45 -0700 | [diff] [blame^] | 290 | PL1V = SPL1 |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame] | 291 | |
| 292 | /* Set TAR to 0 */ |
Furquan Shaikh | 181e2d4 | 2020-06-01 13:03:45 -0700 | [diff] [blame^] | 293 | TARS = 0 |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame] | 294 | |
| 295 | /* Set _PPC to 0 */ |
Furquan Shaikh | 181e2d4 | 2020-06-01 13:03:45 -0700 | [diff] [blame^] | 296 | PPCM = 0 |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame] | 297 | \PPCN () |
| 298 | |
| 299 | Release (CTCM) |
| 300 | Return (1) |
| 301 | } |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 302 | } |
| 303 | |
| 304 | // Current Resource Settings |
Martin Roth | fc70643 | 2015-08-18 16:56:05 -0600 | [diff] [blame] | 305 | Name (MCRS, ResourceTemplate() |
| 306 | { |
| 307 | // Bus Numbers |
| 308 | WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, |
| 309 | 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,, PB00) |
| 310 | |
| 311 | // IO Region 0 |
| 312 | DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, |
| 313 | 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00) |
| 314 | |
| 315 | // PCI Config Space |
| 316 | Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) |
| 317 | |
| 318 | // IO Region 1 |
| 319 | DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, |
| 320 | 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300,,, PI01) |
| 321 | |
| 322 | // VGA memory (0xa0000-0xbffff) |
| 323 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 324 | Cacheable, ReadWrite, |
| 325 | 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, |
| 326 | 0x00020000,,, ASEG) |
| 327 | |
| 328 | // OPROM reserved (0xc0000-0xc3fff) |
| 329 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 330 | Cacheable, ReadWrite, |
| 331 | 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000, |
| 332 | 0x00004000,,, OPR0) |
| 333 | |
| 334 | // OPROM reserved (0xc4000-0xc7fff) |
| 335 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 336 | Cacheable, ReadWrite, |
| 337 | 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000, |
| 338 | 0x00004000,,, OPR1) |
| 339 | |
| 340 | // OPROM reserved (0xc8000-0xcbfff) |
| 341 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 342 | Cacheable, ReadWrite, |
| 343 | 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000, |
| 344 | 0x00004000,,, OPR2) |
| 345 | |
| 346 | // OPROM reserved (0xcc000-0xcffff) |
| 347 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 348 | Cacheable, ReadWrite, |
| 349 | 0x00000000, 0x000cc000, 0x000cffff, 0x00000000, |
| 350 | 0x00004000,,, OPR3) |
| 351 | |
| 352 | // OPROM reserved (0xd0000-0xd3fff) |
| 353 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 354 | Cacheable, ReadWrite, |
| 355 | 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000, |
| 356 | 0x00004000,,, OPR4) |
| 357 | |
| 358 | // OPROM reserved (0xd4000-0xd7fff) |
| 359 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 360 | Cacheable, ReadWrite, |
| 361 | 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000, |
| 362 | 0x00004000,,, OPR5) |
| 363 | |
| 364 | // OPROM reserved (0xd8000-0xdbfff) |
| 365 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 366 | Cacheable, ReadWrite, |
| 367 | 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000, |
| 368 | 0x00004000,,, OPR6) |
| 369 | |
| 370 | // OPROM reserved (0xdc000-0xdffff) |
| 371 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 372 | Cacheable, ReadWrite, |
| 373 | 0x00000000, 0x000dc000, 0x000dffff, 0x00000000, |
| 374 | 0x00004000,,, OPR7) |
| 375 | |
| 376 | // BIOS Extension (0xe0000-0xe3fff) |
| 377 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 378 | Cacheable, ReadWrite, |
| 379 | 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000, |
| 380 | 0x00004000,,, ESG0) |
| 381 | |
| 382 | // BIOS Extension (0xe4000-0xe7fff) |
| 383 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 384 | Cacheable, ReadWrite, |
| 385 | 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000, |
| 386 | 0x00004000,,, ESG1) |
| 387 | |
| 388 | // BIOS Extension (0xe8000-0xebfff) |
| 389 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 390 | Cacheable, ReadWrite, |
| 391 | 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000, |
| 392 | 0x00004000,,, ESG2) |
| 393 | |
| 394 | // BIOS Extension (0xec000-0xeffff) |
| 395 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 396 | Cacheable, ReadWrite, |
| 397 | 0x00000000, 0x000ec000, 0x000effff, 0x00000000, |
| 398 | 0x00004000,,, ESG3) |
| 399 | |
| 400 | // System BIOS (0xf0000-0xfffff) |
| 401 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 402 | Cacheable, ReadWrite, |
| 403 | 0x00000000, 0x000f0000, 0x000fffff, 0x00000000, |
| 404 | 0x00010000,,, FSEG) |
| 405 | |
| 406 | // PCI Memory Region (Top of memory-CONFIG_MMCONF_BASE_ADDRESS) |
| 407 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 408 | Cacheable, ReadWrite, |
| 409 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 410 | 0x00000000,,, PM01) |
| 411 | |
| 412 | // TPM Area (0xfed40000-0xfed44fff) |
| 413 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 414 | Cacheable, ReadWrite, |
| 415 | 0x00000000, 0xfed40000, 0xfed44fff, 0x00000000, |
| 416 | 0x00005000,,, TPMR) |
| 417 | }) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 418 | |
| 419 | Method (_CRS, 0, Serialized) |
| 420 | { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 421 | // Find PCI resource area in MCRS |
Martin Roth | fc70643 | 2015-08-18 16:56:05 -0600 | [diff] [blame] | 422 | CreateDwordField(MCRS, ^PM01._MIN, PMIN) |
| 423 | CreateDwordField(MCRS, ^PM01._MAX, PMAX) |
| 424 | CreateDwordField(MCRS, ^PM01._LEN, PLEN) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 425 | |
| 426 | // Fix up PCI memory region |
| 427 | // Start with Top of Lower Usable DRAM |
Furquan Shaikh | 181e2d4 | 2020-06-01 13:03:45 -0700 | [diff] [blame^] | 428 | Local0 = ^MCHC.TLUD |
| 429 | Local1 = ^MCHC.MEBA |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 430 | |
| 431 | // Check if ME base is equal |
Furquan Shaikh | 181e2d4 | 2020-06-01 13:03:45 -0700 | [diff] [blame^] | 432 | If (Local0 == Local1) { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 433 | // Use Top Of Memory instead |
Furquan Shaikh | 181e2d4 | 2020-06-01 13:03:45 -0700 | [diff] [blame^] | 434 | Local0 = ^MCHC.TOM |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 435 | } |
| 436 | |
Furquan Shaikh | 181e2d4 | 2020-06-01 13:03:45 -0700 | [diff] [blame^] | 437 | PMIN = Local0 |
| 438 | PMAX = CONFIG_MMCONF_BASE_ADDRESS - 1 |
| 439 | PLEN = PMAX - PMIN + 1 |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 440 | |
| 441 | Return (MCRS) |
| 442 | } |