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Angel Ponsa21dff62020-04-03 01:22:24 +02001/* SPDX-License-Identifier: GPL-2.0-only */
Nico Huberefe1fed2013-04-29 18:00:57 +02002
Arthur Heymansfa5d0f82019-11-12 19:11:50 +01003#include <bootblock_common.h>
Nico Huberefe1fed2013-04-29 18:00:57 +02004#include <stdint.h>
Elyes HAOUAS92c4bc12020-08-26 20:07:31 +02005#include <device/pnp_def.h>
Kyösti Mälkki3855c012019-03-03 08:45:19 +02006#include <device/pnp_ops.h>
Kyösti Mälkkif1b58b72019-03-01 13:43:02 +02007#include <device/pci_ops.h>
Elyes HAOUAS8c905a82019-02-07 09:00:47 +01008#include <device/pci_def.h>
Vladimir Serbinenkoa50478f2016-02-10 03:03:41 +01009#include <northbridge/intel/sandybridge/raminit_native.h>
Elyes HAOUAS8c905a82019-02-07 09:00:47 +010010#include <northbridge/intel/sandybridge/raminit.h>
11#include <northbridge/intel/sandybridge/sandybridge.h>
Edward O'Callaghan77757c22015-01-04 21:33:39 +110012#include <southbridge/intel/bd82x6x/pch.h>
Patrick Rudolphe8e66f42016-02-06 17:42:42 +010013#include <southbridge/intel/common/gpio.h>
Elyes HAOUASe051dc02018-08-06 10:55:59 +020014#include <superio/winbond/common/winbond.h>
Nico Huberefe1fed2013-04-29 18:00:57 +020015
Arthur Heymans2b28a162019-11-12 17:21:08 +010016void mainboard_pch_lpc_setup(void)
Nico Huberefe1fed2013-04-29 18:00:57 +020017{
18 /* Set COM3/COM1 decode ranges: 0x3e8/0x3f8 */
19 pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0070);
20
21 /* Enable KBC on 0x06/0x64 (KBC),
22 * EC on 0x62/0x66 (MC),
23 * EC on 0x20c-0x20f (GAMEH),
24 * Super I/O on 0x2e/0x2f (CNF1),
25 * COM1/COM3 decode ranges. */
26 pci_write_config16(PCH_LPC_DEV, LPC_EN,
27 KBC_LPC_EN | MC_LPC_EN |
28 CNF1_LPC_EN | GAMEH_LPC_EN |
29 COMA_LPC_EN | COMB_LPC_EN);
30}
31
Arthur Heymansfa5d0f82019-11-12 19:11:50 +010032void bootblock_mainboard_early_init(void)
Nico Huberefe1fed2013-04-29 18:00:57 +020033{
Elyes HAOUASf10b5ff2016-10-06 19:49:55 +020034 int lvds_3v = 0; /* 0 (5V) or 1 (3V3) */
35 int dis_bl_inv = 1; /* backlight inversion: 1 = disabled, 0 = enabled */
Elyes HAOUASefc3d042020-04-08 12:15:16 +020036 const pnp_devfn_t dev = PNP_DEV(0x2e, 0x9);
Elyes HAOUASe051dc02018-08-06 10:55:59 +020037 pnp_enter_conf_state(dev);
Nico Huber40f9ce92013-10-22 11:07:23 +020038 pnp_write_config(dev, 0x29, 0x02); /* Pins 119, 120 are GPIO21, 20 */
Elyes HAOUAS92c4bc12020-08-26 20:07:31 +020039 pnp_write_config(dev, PNP_IDX_EN, 0x03); /* Enable GPIO2+3 */
Nico Huber40f9ce92013-10-22 11:07:23 +020040 pnp_write_config(dev, 0x2a, 0x01); /* Pins 62, 63, 65, 66 are
41 GPIO27, 26, 25, 24 */
42 pnp_write_config(dev, 0x2c, 0xc3); /* Pin 90 is GPIO32,
43 Pins 78~85 are UART B */
44 pnp_write_config(dev, 0x2d, 0x00); /* Pins 67, 68, 70~73, 75, 77 are
45 GPIO57~50 */
Nico Huberefe1fed2013-04-29 18:00:57 +020046 pnp_set_logical_device(dev);
47 /* Values can only be changed, when devices are enabled. */
Nico Huberefe1fed2013-04-29 18:00:57 +020048 pnp_write_config(dev, 0xe3, 0xdd); /* GPIO2 bits 1, 5 are output */
Nico Huber40f9ce92013-10-22 11:07:23 +020049 pnp_write_config(dev, 0xe4, (dis_bl_inv << 5) | (lvds_3v << 1)); /* GPIO2 bits 1, 5 */
Elyes HAOUAS92c4bc12020-08-26 20:07:31 +020050 /* Disable suspend LED during normal operation */
51 pnp_write_config(dev, PNP_IDX_MSC3, 0x40);
Elyes HAOUASe051dc02018-08-06 10:55:59 +020052 pnp_exit_conf_state(dev);
Nico Huberefe1fed2013-04-29 18:00:57 +020053}
54
Vladimir Serbinenkoffbb3c02016-02-10 01:36:25 +010055void mainboard_fill_pei_data(struct pei_data *pei_data)
Nico Huberefe1fed2013-04-29 18:00:57 +020056{
Vladimir Serbinenkoffbb3c02016-02-10 01:36:25 +010057 struct pei_data pei_data_template = {
Edward O'Callaghan6f49f692014-05-24 02:04:52 +100058 .pei_version = PEI_VERSION,
Angel Ponsd9e58dc2021-01-20 01:22:20 +010059 .mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE,
60 .dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE,
61 .epbar = CONFIG_FIXED_EPBAR_MMIO_BASE,
Shelley Chen4e9bb332021-10-20 15:43:45 -070062 .pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS,
Angel Ponsb21bffa2020-07-03 01:02:28 +020063 .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
Edward O'Callaghan6f49f692014-05-24 02:04:52 +100064 .wdbbar = 0x4000000,
65 .wdbsize = 0x1000,
66 .hpet_address = CONFIG_HPET_ADDRESS,
Angel Pons92717ff2020-09-14 16:22:22 +020067 .rcba = (uintptr_t)DEFAULT_RCBA,
Edward O'Callaghan6f49f692014-05-24 02:04:52 +100068 .pmbase = DEFAULT_PMBASE,
69 .gpiobase = DEFAULT_GPIOBASE,
70 .thermalbase = 0xfed08000,
Elyes HAOUASf10b5ff2016-10-06 19:49:55 +020071 .system_type = 0, /* 0 Mobile, 1 Desktop/Server */
Edward O'Callaghan6f49f692014-05-24 02:04:52 +100072 .tseg_size = CONFIG_SMM_TSEG_SIZE,
73 .spd_addresses = { 0xA0, 0x00,0xA4,0x00 },
74 .ts_addresses = { 0x00, 0x00, 0x00, 0x00 },
75 .ec_present = 1,
76 .gbe_enable = 1,
77 .ddr3lv_support = 0,
Edward O'Callaghan6f49f692014-05-24 02:04:52 +100078 .max_ddr3_freq = 1600,
79 .usb_port_config = {
Elyes HAOUAS44f558e2020-02-24 13:26:04 +010080 /* enabled USB oc pin length */
Nico Huberefe1fed2013-04-29 18:00:57 +020081 { 1, 0, 0x0040 }, /* P0: lower left USB 3.0 (OC0) */
82 { 1, 0, 0x0040 }, /* P1: upper left USB 3.0 (OC0) */
83 { 1, 0, 0x0040 }, /* P2: lower right USB 3.0 (OC0) */
84 { 1, 0, 0x0040 }, /* P3: upper right USB 3.0 (OC0) */
85 { 1, 0, 0x0040 }, /* P4: lower USB 2.0 (OC0) */
86 { 1, 0, 0x0040 }, /* P5: upper USB 2.0 (OC0) */
87 { 1, 0, 0x0040 }, /* P6: front panel USB 2.0 (OC0) */
88 { 1, 0, 0x0040 }, /* P7: front panel USB 2.0 (OC0) */
89 { 1, 4, 0x0040 }, /* P8: internal USB 2.0 (OC4) */
90 { 1, 4, 0x0040 }, /* P9: internal USB 2.0 (OC4) */
91 { 1, 4, 0x0040 }, /* P10: internal USB 2.0 (OC4) */
92 { 1, 4, 0x0040 }, /* P11: internal USB 2.0 (OC4) */
93 { 1, 4, 0x0040 }, /* P12: internal USB 2.0 (OC4) */
94 { 1, 4, 0x0040 }, /* P13: internal USB 2.0 (OC4) */
95 },
Edward O'Callaghan6f49f692014-05-24 02:04:52 +100096 .usb3 = {
97 .mode = 3, /* Smart Auto? */
98 .hs_port_switch_mask = 0xf, /* All four ports. */
99 .preboot_support = 1, /* preOS driver? */
100 .xhci_streams = 1, /* Enable. */
Nico Huberefe1fed2013-04-29 18:00:57 +0200101 },
Edward O'Callaghan6f49f692014-05-24 02:04:52 +1000102 .pcie_init = 1,
Nico Huberefe1fed2013-04-29 18:00:57 +0200103 };
Vladimir Serbinenkoffbb3c02016-02-10 01:36:25 +0100104 *pei_data = pei_data_template;
105}
Nico Huberefe1fed2013-04-29 18:00:57 +0200106
Vladimir Serbinenkoa50478f2016-02-10 03:03:41 +0100107const struct southbridge_usb_port mainboard_usb_ports[] = {
Elyes HAOUAS44f558e2020-02-24 13:26:04 +0100108 /* enabled power USB oc pin */
Vladimir Serbinenkoa50478f2016-02-10 03:03:41 +0100109 { 1, 0, 0 }, /* P0: lower left USB 3.0 (OC0) */
110 { 1, 0, 0 }, /* P1: upper left USB 3.0 (OC0) */
111 { 1, 0, 0 }, /* P2: lower right USB 3.0 (OC0) */
112 { 1, 0, 0 }, /* P3: upper right USB 3.0 (OC0) */
113 { 1, 0, 0 }, /* P4: lower USB 2.0 (OC0) */
114 { 1, 0, 0 }, /* P5: upper USB 2.0 (OC0) */
115 { 1, 0, 0 }, /* P6: front panel USB 2.0 (OC0) */
116 { 1, 0, 0 }, /* P7: front panel USB 2.0 (OC0) */
117 { 1, 0, 4 }, /* P8: internal USB 2.0 (OC4) */
118 { 1, 0, 4 }, /* P9: internal USB 2.0 (OC4) */
119 { 1, 0, 4 }, /* P10: internal USB 2.0 (OC4) */
120 { 1, 0, 4 }, /* P11: internal USB 2.0 (OC4) */
121 { 1, 0, 4 }, /* P12: internal USB 2.0 (OC4) */
122 { 1, 0, 4 }, /* P13: internal USB 2.0 (OC4) */
123};
124
Peter Lemenkov498f1cc2019-02-07 10:48:10 +0100125void mainboard_get_spd(spd_raw_data *spd, bool id_only)
126{
Kyösti Mälkkie258b9a2016-11-18 19:59:23 +0200127 read_spd(&spd[0], 0x50, id_only);
128 read_spd(&spd[2], 0x52, id_only);
Vladimir Serbinenkoa50478f2016-02-10 03:03:41 +0100129}
130
Vladimir Serbinenkoffbb3c02016-02-10 01:36:25 +0100131void mainboard_early_init(int s3resume)
132{
Nico Huberefe1fed2013-04-29 18:00:57 +0200133 /* Enable PEG10 (1x16) */
134 pci_write_config32(PCI_DEV(0, 0, 0), DEVEN,
135 pci_read_config32(PCI_DEV(0, 0, 0), DEVEN) |
136 DEVEN_PEG10);
Vladimir Serbinenkoffbb3c02016-02-10 01:36:25 +0100137}
Nico Huberefe1fed2013-04-29 18:00:57 +0200138
Vladimir Serbinenkoffbb3c02016-02-10 01:36:25 +0100139int mainboard_should_reset_usb(int s3resume)
140{
141 return !s3resume;
Nico Huberefe1fed2013-04-29 18:00:57 +0200142}