Nico Huber | efe1fed | 2013-04-29 18:00:57 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2010 coresystems GmbH |
| 5 | * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Nico Huber | efe1fed | 2013-04-29 18:00:57 +0200 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | #include <stdint.h> |
| 18 | #include <string.h> |
| 19 | #include <lib.h> |
| 20 | #include <timestamp.h> |
| 21 | #include <arch/io.h> |
| 22 | #include <device/pci_def.h> |
| 23 | #include <device/pnp_def.h> |
| 24 | #include <cpu/x86/lapic.h> |
| 25 | #include <pc80/mc146818rtc.h> |
Kyösti Mälkki | 6722f8d | 2014-06-16 09:14:49 +0300 | [diff] [blame] | 26 | #include <arch/acpi.h> |
Nico Huber | efe1fed | 2013-04-29 18:00:57 +0200 | [diff] [blame] | 27 | #include <cbmem.h> |
| 28 | #include <console/console.h> |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 29 | #include <northbridge/intel/sandybridge/sandybridge.h> |
| 30 | #include <northbridge/intel/sandybridge/raminit.h> |
Vladimir Serbinenko | a50478f | 2016-02-10 03:03:41 +0100 | [diff] [blame^] | 31 | #include <northbridge/intel/sandybridge/raminit_native.h> |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 32 | #include <southbridge/intel/bd82x6x/pch.h> |
Nico Huber | efe1fed | 2013-04-29 18:00:57 +0200 | [diff] [blame] | 33 | #include <arch/cpu.h> |
Nico Huber | efe1fed | 2013-04-29 18:00:57 +0200 | [diff] [blame] | 34 | #include <cpu/x86/msr.h> |
Patrick Georgi | bd79c5e | 2014-11-28 22:35:36 +0100 | [diff] [blame] | 35 | #include <halt.h> |
Nico Huber | efe1fed | 2013-04-29 18:00:57 +0200 | [diff] [blame] | 36 | |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 37 | void pch_enable_lpc(void) |
Nico Huber | efe1fed | 2013-04-29 18:00:57 +0200 | [diff] [blame] | 38 | { |
| 39 | /* Set COM3/COM1 decode ranges: 0x3e8/0x3f8 */ |
| 40 | pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0070); |
| 41 | |
| 42 | /* Enable KBC on 0x06/0x64 (KBC), |
| 43 | * EC on 0x62/0x66 (MC), |
| 44 | * EC on 0x20c-0x20f (GAMEH), |
| 45 | * Super I/O on 0x2e/0x2f (CNF1), |
| 46 | * COM1/COM3 decode ranges. */ |
| 47 | pci_write_config16(PCH_LPC_DEV, LPC_EN, |
| 48 | KBC_LPC_EN | MC_LPC_EN | |
| 49 | CNF1_LPC_EN | GAMEH_LPC_EN | |
| 50 | COMA_LPC_EN | COMB_LPC_EN); |
| 51 | } |
| 52 | |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 53 | void rcba_config(void) |
Nico Huber | efe1fed | 2013-04-29 18:00:57 +0200 | [diff] [blame] | 54 | { |
| 55 | u32 reg32; |
| 56 | |
Nico Huber | efe1fed | 2013-04-29 18:00:57 +0200 | [diff] [blame] | 57 | /* Disable unused devices (board specific) */ |
| 58 | reg32 = RCBA32(FD); |
| 59 | reg32 |= PCH_DISABLE_ALWAYS; |
| 60 | /* Disable PCI bridge so MRC does not probe this bus */ |
| 61 | reg32 |= PCH_DISABLE_P2P; |
| 62 | RCBA32(FD) = reg32; |
| 63 | } |
| 64 | |
| 65 | static void pnp_enter_ext_func_mode(device_t dev) |
| 66 | { |
| 67 | u16 port = dev >> 8; |
| 68 | outb(0x87, port); |
| 69 | outb(0x87, port); |
| 70 | } |
| 71 | |
| 72 | static void pnp_exit_ext_func_mode(device_t dev) |
| 73 | { |
| 74 | u16 port = dev >> 8; |
| 75 | outb(0xaa, port); |
| 76 | } |
| 77 | |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 78 | void mainboard_config_superio(void) |
Nico Huber | efe1fed | 2013-04-29 18:00:57 +0200 | [diff] [blame] | 79 | { |
Nico Huber | 40f9ce9 | 2013-10-22 11:07:23 +0200 | [diff] [blame] | 80 | int lvds_3v = 0; // 0 (5V) or 1 (3V3) |
| 81 | int dis_bl_inv = 1; // backlight inversion: 1 = disabled, 0 = enabled |
Nico Huber | efe1fed | 2013-04-29 18:00:57 +0200 | [diff] [blame] | 82 | device_t dev = PNP_DEV(0x2e, 0x9); |
| 83 | pnp_enter_ext_func_mode(dev); |
Nico Huber | 40f9ce9 | 2013-10-22 11:07:23 +0200 | [diff] [blame] | 84 | pnp_write_config(dev, 0x29, 0x02); /* Pins 119, 120 are GPIO21, 20 */ |
| 85 | pnp_write_config(dev, 0x30, 0x03); /* Enable GPIO2+3 */ |
| 86 | pnp_write_config(dev, 0x2a, 0x01); /* Pins 62, 63, 65, 66 are |
| 87 | GPIO27, 26, 25, 24 */ |
| 88 | pnp_write_config(dev, 0x2c, 0xc3); /* Pin 90 is GPIO32, |
| 89 | Pins 78~85 are UART B */ |
| 90 | pnp_write_config(dev, 0x2d, 0x00); /* Pins 67, 68, 70~73, 75, 77 are |
| 91 | GPIO57~50 */ |
Nico Huber | efe1fed | 2013-04-29 18:00:57 +0200 | [diff] [blame] | 92 | pnp_set_logical_device(dev); |
| 93 | /* Values can only be changed, when devices are enabled. */ |
Nico Huber | efe1fed | 2013-04-29 18:00:57 +0200 | [diff] [blame] | 94 | pnp_write_config(dev, 0xe3, 0xdd); /* GPIO2 bits 1, 5 are output */ |
Nico Huber | 40f9ce9 | 2013-10-22 11:07:23 +0200 | [diff] [blame] | 95 | pnp_write_config(dev, 0xe4, (dis_bl_inv << 5) | (lvds_3v << 1)); /* GPIO2 bits 1, 5 */ |
Nico Huber | efe1fed | 2013-04-29 18:00:57 +0200 | [diff] [blame] | 96 | pnp_exit_ext_func_mode(dev); |
| 97 | } |
| 98 | |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 99 | void mainboard_fill_pei_data(struct pei_data *pei_data) |
Nico Huber | efe1fed | 2013-04-29 18:00:57 +0200 | [diff] [blame] | 100 | { |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 101 | struct pei_data pei_data_template = { |
Edward O'Callaghan | 6f49f69 | 2014-05-24 02:04:52 +1000 | [diff] [blame] | 102 | .pei_version = PEI_VERSION, |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 103 | .mchbar = (uintptr_t)DEFAULT_MCHBAR, |
| 104 | .dmibar = (uintptr_t)DEFAULT_DMIBAR, |
Edward O'Callaghan | 6f49f69 | 2014-05-24 02:04:52 +1000 | [diff] [blame] | 105 | .epbar = DEFAULT_EPBAR, |
| 106 | .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, |
| 107 | .smbusbar = SMBUS_IO_BASE, |
| 108 | .wdbbar = 0x4000000, |
| 109 | .wdbsize = 0x1000, |
| 110 | .hpet_address = CONFIG_HPET_ADDRESS, |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 111 | .rcba = (uintptr_t)DEFAULT_RCBABASE, |
Edward O'Callaghan | 6f49f69 | 2014-05-24 02:04:52 +1000 | [diff] [blame] | 112 | .pmbase = DEFAULT_PMBASE, |
| 113 | .gpiobase = DEFAULT_GPIOBASE, |
| 114 | .thermalbase = 0xfed08000, |
| 115 | .system_type = 0, // 0 Mobile, 1 Desktop/Server |
| 116 | .tseg_size = CONFIG_SMM_TSEG_SIZE, |
| 117 | .spd_addresses = { 0xA0, 0x00,0xA4,0x00 }, |
| 118 | .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, |
| 119 | .ec_present = 1, |
| 120 | .gbe_enable = 1, |
| 121 | .ddr3lv_support = 0, |
Nico Huber | efe1fed | 2013-04-29 18:00:57 +0200 | [diff] [blame] | 122 | // 0 = leave channel enabled |
| 123 | // 1 = disable dimm 0 on channel |
| 124 | // 2 = disable dimm 1 on channel |
| 125 | // 3 = disable dimm 0+1 on channel |
Edward O'Callaghan | 6f49f69 | 2014-05-24 02:04:52 +1000 | [diff] [blame] | 126 | .dimm_channel0_disabled = 2, |
| 127 | .dimm_channel1_disabled = 2, |
| 128 | .max_ddr3_freq = 1600, |
| 129 | .usb_port_config = { |
Nico Huber | efe1fed | 2013-04-29 18:00:57 +0200 | [diff] [blame] | 130 | /* enabled usb oc pin length */ |
| 131 | { 1, 0, 0x0040 }, /* P0: lower left USB 3.0 (OC0) */ |
| 132 | { 1, 0, 0x0040 }, /* P1: upper left USB 3.0 (OC0) */ |
| 133 | { 1, 0, 0x0040 }, /* P2: lower right USB 3.0 (OC0) */ |
| 134 | { 1, 0, 0x0040 }, /* P3: upper right USB 3.0 (OC0) */ |
| 135 | { 1, 0, 0x0040 }, /* P4: lower USB 2.0 (OC0) */ |
| 136 | { 1, 0, 0x0040 }, /* P5: upper USB 2.0 (OC0) */ |
| 137 | { 1, 0, 0x0040 }, /* P6: front panel USB 2.0 (OC0) */ |
| 138 | { 1, 0, 0x0040 }, /* P7: front panel USB 2.0 (OC0) */ |
| 139 | { 1, 4, 0x0040 }, /* P8: internal USB 2.0 (OC4) */ |
| 140 | { 1, 4, 0x0040 }, /* P9: internal USB 2.0 (OC4) */ |
| 141 | { 1, 4, 0x0040 }, /* P10: internal USB 2.0 (OC4) */ |
| 142 | { 1, 4, 0x0040 }, /* P11: internal USB 2.0 (OC4) */ |
| 143 | { 1, 4, 0x0040 }, /* P12: internal USB 2.0 (OC4) */ |
| 144 | { 1, 4, 0x0040 }, /* P13: internal USB 2.0 (OC4) */ |
| 145 | }, |
Edward O'Callaghan | 6f49f69 | 2014-05-24 02:04:52 +1000 | [diff] [blame] | 146 | .usb3 = { |
| 147 | .mode = 3, /* Smart Auto? */ |
| 148 | .hs_port_switch_mask = 0xf, /* All four ports. */ |
| 149 | .preboot_support = 1, /* preOS driver? */ |
| 150 | .xhci_streams = 1, /* Enable. */ |
Nico Huber | efe1fed | 2013-04-29 18:00:57 +0200 | [diff] [blame] | 151 | }, |
Edward O'Callaghan | 6f49f69 | 2014-05-24 02:04:52 +1000 | [diff] [blame] | 152 | .pcie_init = 1, |
Nico Huber | efe1fed | 2013-04-29 18:00:57 +0200 | [diff] [blame] | 153 | }; |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 154 | *pei_data = pei_data_template; |
| 155 | } |
Nico Huber | efe1fed | 2013-04-29 18:00:57 +0200 | [diff] [blame] | 156 | |
Vladimir Serbinenko | a50478f | 2016-02-10 03:03:41 +0100 | [diff] [blame^] | 157 | const struct southbridge_usb_port mainboard_usb_ports[] = { |
| 158 | /* enabled power usb oc pin */ |
| 159 | { 1, 0, 0 }, /* P0: lower left USB 3.0 (OC0) */ |
| 160 | { 1, 0, 0 }, /* P1: upper left USB 3.0 (OC0) */ |
| 161 | { 1, 0, 0 }, /* P2: lower right USB 3.0 (OC0) */ |
| 162 | { 1, 0, 0 }, /* P3: upper right USB 3.0 (OC0) */ |
| 163 | { 1, 0, 0 }, /* P4: lower USB 2.0 (OC0) */ |
| 164 | { 1, 0, 0 }, /* P5: upper USB 2.0 (OC0) */ |
| 165 | { 1, 0, 0 }, /* P6: front panel USB 2.0 (OC0) */ |
| 166 | { 1, 0, 0 }, /* P7: front panel USB 2.0 (OC0) */ |
| 167 | { 1, 0, 4 }, /* P8: internal USB 2.0 (OC4) */ |
| 168 | { 1, 0, 4 }, /* P9: internal USB 2.0 (OC4) */ |
| 169 | { 1, 0, 4 }, /* P10: internal USB 2.0 (OC4) */ |
| 170 | { 1, 0, 4 }, /* P11: internal USB 2.0 (OC4) */ |
| 171 | { 1, 0, 4 }, /* P12: internal USB 2.0 (OC4) */ |
| 172 | { 1, 0, 4 }, /* P13: internal USB 2.0 (OC4) */ |
| 173 | }; |
| 174 | |
| 175 | void mainboard_get_spd(spd_raw_data *spd) { |
| 176 | read_spd(&spd[0], 0x50); |
| 177 | read_spd(&spd[2], 0x52); |
| 178 | } |
| 179 | |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 180 | void mainboard_early_init(int s3resume) |
| 181 | { |
Nico Huber | efe1fed | 2013-04-29 18:00:57 +0200 | [diff] [blame] | 182 | /* Enable PEG10 (1x16) */ |
| 183 | pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, |
| 184 | pci_read_config32(PCI_DEV(0, 0, 0), DEVEN) | |
| 185 | DEVEN_PEG10); |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 186 | } |
Nico Huber | efe1fed | 2013-04-29 18:00:57 +0200 | [diff] [blame] | 187 | |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 188 | int mainboard_should_reset_usb(int s3resume) |
| 189 | { |
| 190 | return !s3resume; |
Nico Huber | efe1fed | 2013-04-29 18:00:57 +0200 | [diff] [blame] | 191 | } |