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Lee Leahy2ed7eb72016-01-01 18:08:48 -08001##
2## This file is part of the coreboot project.
3##
4## Copyright (C) 2015-2016 Intel Corp.
5##
6## This program is free software; you can redistribute it and/or modify
7## it under the terms of the GNU General Public License as published by
8## the Free Software Foundation; version 2 of the License.
9##
10## This program is distributed in the hope that it will be useful,
11## but WITHOUT ANY WARRANTY; without even the implied warranty of
12## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13## GNU General Public License for more details.
14##
15
16config SOC_INTEL_QUARK
17 bool
18 help
19 Intel Quark support
20
21if SOC_INTEL_QUARK
22
23config CPU_SPECIFIC_OPTIONS
24 def_bool y
25 select ARCH_BOOTBLOCK_X86_32
26 select ARCH_RAMSTAGE_X86_32
27 select ARCH_ROMSTAGE_X86_32
28 select ARCH_VERSTAGE_X86_32
Lee Leahy87df8d02016-02-07 14:37:13 -080029 select SOC_INTEL_COMMON
Lee Leahy43cdff62016-02-07 14:52:22 -080030 select SOC_SETS_MTRRS
Lee Leahy87df8d02016-02-07 14:37:13 -080031 select TSC_CONSTANT_RATE
32 select UDELAY_TSC
Lee Leahy43cdff62016-02-07 14:52:22 -080033 select UNCOMPRESSED_RAMSTAGE
Lee Leahy2ed7eb72016-01-01 18:08:48 -080034 select USE_MARCH_586
35
Lee Leahy9fd08952016-02-02 07:17:06 -080036#####
Lee Leahy87df8d02016-02-07 14:37:13 -080037# Debug serial output
38# The following options configure the debug serial port
39#####
40
41config ENABLE_BUILTIN_HSUART1
42 bool "Enable built-in HSUART1"
43 default y
44 select NO_UART_ON_SUPERIO
45 select DRIVERS_UART_8250MEM_32
46 help
47 The Quark SoC has two HSUART. Choose this option to configure the pads
48 and enable HSUART1, which can be used for the debug console.
49
50config TTYS0_BASE
51 hex "HSUART1 Base Address"
52 depends on ENABLE_BUILTIN_HSUART1
53 default 0xA0019000
54 help
55 Memory mapped MMIO of HSUART1.
56
57config TTYS0_LCS
58 int
59 depends on ENABLE_BUILTIN_HSUART1
60 default 3
61
62#####
Lee Leahya7ba56e2016-02-07 10:42:14 -080063# Debug support
64# The following options provide debug support for the Quark coreboot
65# code. The SD LED is used as a binary marker to determine if a
66# specific point in the execution flow has been reached.
67#####
68
69config ENABLE_DEBUG_LED
70 bool
71 default n
72 help
73 Enable the use of the SD LED for early debugging before serial output
74 is available. Setting this LED indicates that control has reached the
75 desired check point.
76
77config ENABLE_DEBUG_LED_ESRAM
78 bool "SD LED indicates ESRAM initialized"
79 default n
80 select ENABLE_DEBUG_LED
81 help
82 Indicate that ESRAM has been successfully initialized.
83
84config ENABLE_DEBUG_LED_FINDFSP
85 bool "SD LED indicates fsp.bin file was found"
86 default n
87 select ENABLE_DEBUG_LED
88 help
89 Indicate that fsp.bin was found.
90
91config ENABLE_DEBUG_LED_TEMPRAMINIT
92 bool "SD LED indicates TempRamInit was successful"
93 default n
94 select ENABLE_DEBUG_LED
95 help
96 Indicate that TempRamInit was successful.
97
98#####
Lee Leahy87df8d02016-02-07 14:37:13 -080099# ESRAM layout
100# Specify the portion of the ESRAM for coreboot to use as its data area.
101#####
102
103config DCACHE_RAM_BASE
104 hex
105 default 0x80070000
106
107config DCACHE_RAM_SIZE
108 hex
109 default 0x00008000
110
111#####
Lee Leahy9fd08952016-02-02 07:17:06 -0800112# Flash layout
113# Specify the size of the coreboot file system in the read-only
114# (recovery) portion of the flash part.
115#####
116
117config CBFS_SIZE
118 hex
119 default 0x200000
120 help
121 Specify the size of the coreboot file system in the read-only (recovery)
122 portion of the flash part. On Quark systems the firmware image stores
123 more than just coreboot, including:
124 - The chipset microcode (RMU) binary file located at 0xFFF00000
125 - Intel Trusted Execution Engine firmware
126
127#####
Lee Leahya7ba56e2016-02-07 10:42:14 -0800128# FSP binary
129# The following options control the FSP binary file placement in
130# the flash image and ESRAM. This file is required by the Quark
131# SoC code to boot coreboot and its payload.
132#####
133
134config ADD_FSP_RAW_BIN
135 bool "Add the Intel FSP binary to the flash image without relocation"
136 default n
137 depends on PLATFORM_USES_FSP1_1
138 help
139 Select this option to add an Intel FSP binary to
140 the resulting coreboot image.
141
142 Note: Without this binary, coreboot builds relying on the FSP
143 will not boot
144
145config FSP_FILE
146 string "Intel FSP binary path and filename"
147 default "3rdparty/blobs/soc/intel/quark/fsp.bin"
148 depends on PLATFORM_USES_FSP1_1
149 depends on ADD_FSP_RAW_BIN
150 help
151 The path and filename of the Intel FSP binary for this platform.
152
153config FSP_IMAGE_ID_STRING
154 string "8 byte platform string identifying the FSP platform"
155 default "QUK-FSP0"
156 depends on PLATFORM_USES_FSP1_1
157 help
158 8 ASCII character byte signature string that will help match the FSP
159 binary to a supported hardware configuration.
160
161config FSP_LOC
162 hex
163 default 0xfff80000
164 depends on PLATFORM_USES_FSP1_1
165 help
166 The location in CBFS that the FSP is located. This must match the
167 value that is set in the FSP binary. If the FSP needs to be moved,
168 rebase the FSP with Intel's BCT (tool).
169
170config FSP_ESRAM_LOC
171 hex
172 default 0x80000000
173 depends on PLATFORM_USES_FSP1_1
174 help
175 The location in ESRAM where a copy of the FSP binary is placed.
176
Lee Leahyd4edacb2016-02-08 07:12:30 -0800177config RELOCATE_FSP_INTO_DRAM
178 bool "Relocate FSP into DRAM"
179 default n
180 depends on PLATFORM_USES_FSP1_1
181 help
182 Relocate the FSP binary into DRAM before the call to SiliconInit.
183
Lee Leahya7ba56e2016-02-07 10:42:14 -0800184#####
185# FSP PDAT binary
186# The following options control the FSP platform data binary
187# file placement in the flash image.
188#####
189
190config ADD_FSP_PDAT_FILE
191 bool "Should the PDAT binary be added to the flash image?"
192 default n
193 depends on PLATFORM_USES_FSP1_1
194 help
195 The PDAT file is required for the FSP 1.1 binary
196
197config FSP_PDAT_FILE
198 string
199 default "3rdparty/blobs/soc/intel/quark/pdat.bin"
200 depends on PLATFORM_USES_FSP1_1
201 depends on ADD_FSP_PDAT_FILE
202 help
203 The path and filename of the Intel Galileo platform-data-patch (PDAT)
204 binary. This binary file is generated by the platform-data-patch.py
205 script released with the Quark BSP and contains the Ethernet address.
206
207config FSP_PDAT_LOC
208 hex
209 default 0xfff10000
210 depends on PLATFORM_USES_FSP1_1
211 depends on ADD_FSP_PDAT_FILE
212 help
213 The location in CBFS that the PDAT is located. It must match the
214 PCD PcdPlatformDataBaseAddress of Quark SoC FSP.
215
216#####
Lee Leahy9fd08952016-02-02 07:17:06 -0800217# RMU binary
218# The following options control the Quark chipset microcode file
219# placement in the flash image. This file is required to bring
220# the Quark processor out of reset.
221#####
222
223config ADD_RMU_FILE
224 bool "Should the RMU binary be added to the flash image?"
225 default n
226 help
227 The RMU file is required to get the chip out of reset.
228
229config RMU_FILE
230 string
231 default "3rdparty/blobs/soc/intel/quark/rmu.bin"
232 depends on ADD_RMU_FILE
233 help
234 The path and filename of the Intel Quark RMU binary.
235
236config RMU_LOC
237 hex
238 default 0xfff00000
239 depends on ADD_RMU_FILE
240 help
241 The location in CBFS that the RMU is located. It must match the
242 strap-determined base address.
243
Lee Leahy2ed7eb72016-01-01 18:08:48 -0800244endif # SOC_INTEL_QUARK