Patrick Georgi | 7333a11 | 2020-05-08 20:48:04 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 2 | |
| 3 | /* |
Zheng Bao | dd4c542 | 2021-10-14 16:14:09 +0800 | [diff] [blame] | 4 | * ROMSIG At ROMBASE + 0x[0,2,4,8]20000: |
zbao | c3b0b72 | 2016-02-19 13:47:31 +0800 | [diff] [blame] | 5 | * 0 4 8 C |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 6 | * +------------+---------------+----------------+------------+ |
| 7 | * | 0x55AA55AA |EC ROM Address |GEC ROM Address |USB3 ROM | |
| 8 | * +------------+---------------+----------------+------------+ |
Zheng Bao | dd4c542 | 2021-10-14 16:14:09 +0800 | [diff] [blame] | 9 | * | PSPDIR ADDR|PSPDIR ADDR(C) | BDT ADDR 0 | BDT ADDR 1 | |
| 10 | * +------------+---------------+----------------+------------+ |
| 11 | * | BDT ADDR 2 | | BDT ADDR 3(C) | | |
| 12 | * +------------+---------------+----------------+------------+ |
| 13 | * (C): Could be a combo header |
| 14 | * |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 15 | * EC ROM should be 64K aligned. |
| 16 | * |
Zheng Bao | 4fcc9f2 | 2015-11-20 12:29:04 +0800 | [diff] [blame] | 17 | * PSP directory (Where "PSPDIR ADDR" points) |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 18 | * +------------+---------------+----------------+------------+ |
| 19 | * | 'PSP$' | Fletcher | Count | Reserved | |
| 20 | * +------------+---------------+----------------+------------+ |
| 21 | * | 0 | size | Base address | Reserved | Pubkey |
| 22 | * +------------+---------------+----------------+------------+ |
| 23 | * | 1 | size | Base address | Reserved | Bootloader |
| 24 | * +------------+---------------+----------------+------------+ |
| 25 | * | 8 | size | Base address | Reserved | Smu Firmware |
| 26 | * +------------+---------------+----------------+------------+ |
| 27 | * | 3 | size | Base address | Reserved | Recovery Firmware |
| 28 | * +------------+---------------+----------------+------------+ |
| 29 | * | | |
| 30 | * | | |
Zheng Bao | dd4c542 | 2021-10-14 16:14:09 +0800 | [diff] [blame] | 31 | * | Other PSP Firmware | |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 32 | * | | |
| 33 | * +------------+---------------+----------------+------------+ |
Zheng Bao | dd4c542 | 2021-10-14 16:14:09 +0800 | [diff] [blame] | 34 | * | 40 | size | Base address | Reserved |---+ |
| 35 | * +------------+---------------+----------------+------------+ | |
| 36 | * :or 48(A/B A): size : Base address : Reserved : | |
| 37 | * + - - + - - + - - + - - + | |
| 38 | * : 4A(A/B B): size : Base address : Reserved : | |
| 39 | * +------------+---------------+----------------+------------+ | |
| 40 | * (A/B A) & (A/B B): Similar as 40, pointing to PSP level 2 | |
| 41 | * for A/B recovery | |
| 42 | * | |
| 43 | * | |
| 44 | * +------------+---------------+----------------+------------+ | |
| 45 | * | '2LP$' | Fletcher | Count | Reserved |<--+ |
| 46 | * +------------+---------------+----------------+------------+ |
| 47 | * | | |
| 48 | * | | |
| 49 | * | PSP Firmware | |
| 50 | * | (2nd-level is not required on all families) | |
| 51 | * | | |
| 52 | * +------------+---------------+----------------+------------+ |
| 53 | * BIOS Directory Table (BDT) is similar |
Zheng Bao | 4fcc9f2 | 2015-11-20 12:29:04 +0800 | [diff] [blame] | 54 | * |
zbao | c3b0b72 | 2016-02-19 13:47:31 +0800 | [diff] [blame] | 55 | * PSP Combo directory |
Zheng Bao | 4fcc9f2 | 2015-11-20 12:29:04 +0800 | [diff] [blame] | 56 | * +------------+---------------+----------------+------------+ |
zbao | 6e2f3d1 | 2016-02-19 13:34:59 +0800 | [diff] [blame] | 57 | * | 'PSP2' | Fletcher | Count |Look up mode| |
Zheng Bao | 4fcc9f2 | 2015-11-20 12:29:04 +0800 | [diff] [blame] | 58 | * +------------+---------------+----------------+------------+ |
zbao | c3a08a9 | 2016-03-02 14:47:27 +0800 | [diff] [blame] | 59 | * | R e s e r v e d | |
| 60 | * +------------+---------------+----------------+------------+ |
Zheng Bao | dd4c542 | 2021-10-14 16:14:09 +0800 | [diff] [blame] | 61 | * | ID-Sel | PSP ID | PSPDIR ADDR | | 1st PSP directory |
Zheng Bao | 4fcc9f2 | 2015-11-20 12:29:04 +0800 | [diff] [blame] | 62 | * +------------+---------------+----------------+------------+ |
Zheng Bao | dd4c542 | 2021-10-14 16:14:09 +0800 | [diff] [blame] | 63 | * | ID-Sel | PSP ID | PSPDIR ADDR | | 2nd PSP directory |
Zheng Bao | 4fcc9f2 | 2015-11-20 12:29:04 +0800 | [diff] [blame] | 64 | * +------------+---------------+----------------+------------+ |
| 65 | * | | |
| 66 | * | Other PSP | |
| 67 | * | | |
| 68 | * +------------+---------------+----------------+------------+ |
Zheng Bao | dd4c542 | 2021-10-14 16:14:09 +0800 | [diff] [blame] | 69 | * BDT Combo is similar |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 70 | */ |
| 71 | |
Elyes Haouas | 7d67a19 | 2022-10-14 09:58:29 +0200 | [diff] [blame] | 72 | #include <commonlib/bsd/helpers.h> |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 73 | #include <fcntl.h> |
| 74 | #include <errno.h> |
Karthikeyan Ramasubramanian | ecb4e31 | 2022-11-02 16:53:54 -0600 | [diff] [blame] | 75 | #include <limits.h> |
Kangheui Won | 5b84dfd | 2021-12-21 15:45:06 +1100 | [diff] [blame] | 76 | #include <openssl/sha.h> |
Martin Roth | 37305e7 | 2020-04-07 14:16:39 -0600 | [diff] [blame] | 77 | #include <stdbool.h> |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 78 | #include <stdio.h> |
| 79 | #include <sys/stat.h> |
| 80 | #include <sys/types.h> |
| 81 | #include <unistd.h> |
| 82 | #include <string.h> |
| 83 | #include <stdlib.h> |
| 84 | #include <getopt.h> |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 85 | #include <libgen.h> |
Idwer Vollering | 93df1d9 | 2020-12-30 00:01:59 +0100 | [diff] [blame] | 86 | #include <stdint.h> |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 87 | |
| 88 | #include "amdfwtool.h" |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 89 | |
Martin Roth | 60f1551 | 2016-11-08 09:55:01 -0700 | [diff] [blame] | 90 | #define AMD_ROMSIG_OFFSET 0x20000 |
| 91 | #define MIN_ROM_KB 256 |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 92 | |
Marshall Dawson | 7c1e142 | 2019-04-11 09:44:43 -0600 | [diff] [blame] | 93 | #define _MAX(A, B) (((A) > (B)) ? (A) : (B)) |
| 94 | #define ERASE_ALIGNMENT 0x1000U |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 95 | #define TABLE_ALIGNMENT 0x1000U |
| 96 | #define BLOB_ALIGNMENT 0x100U |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 97 | #define TABLE_ERASE_ALIGNMENT _MAX(TABLE_ALIGNMENT, ERASE_ALIGNMENT) |
Marshall Dawson | 7c1e142 | 2019-04-11 09:44:43 -0600 | [diff] [blame] | 98 | #define BLOB_ERASE_ALIGNMENT _MAX(BLOB_ALIGNMENT, ERASE_ALIGNMENT) |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 99 | |
Marshall Dawson | ef79fcc | 2019-04-01 10:16:41 -0600 | [diff] [blame] | 100 | #define DEFAULT_SOFT_FUSE_CHAIN "0x1" |
| 101 | |
Kangheui Won | 5b84dfd | 2021-12-21 15:45:06 +1100 | [diff] [blame] | 102 | /* Defines related to hashing signed binaries */ |
| 103 | enum hash_header_ver { |
| 104 | HASH_HDR_V1 = 1, |
| 105 | }; |
| 106 | /* Signature ID enums are defined by PSP based on the algorithm used. */ |
| 107 | enum signature_id { |
| 108 | SIG_ID_RSA2048, |
| 109 | SIG_ID_RSA4096 = 2, |
| 110 | }; |
| 111 | #define HASH_FILE_SUFFIX ".hash" |
Karthikeyan Ramasubramanian | ecb4e31 | 2022-11-02 16:53:54 -0600 | [diff] [blame] | 112 | #define EFS_FILE_SUFFIX ".efs" |
| 113 | #define TMP_FILE_SUFFIX ".tmp" |
Kangheui Won | 5b84dfd | 2021-12-21 15:45:06 +1100 | [diff] [blame] | 114 | |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 115 | /* |
Marshall Dawson | 0e02ce8 | 2019-03-04 16:50:37 -0700 | [diff] [blame] | 116 | * Beginning with Family 15h Models 70h-7F, a.k.a Stoney Ridge, the PSP |
| 117 | * can support an optional "combo" implementation. If the PSP sees the |
| 118 | * PSP2 cookie, it interprets the table as a roadmap to additional PSP |
| 119 | * tables. Using this, support for multiple product generations may be |
| 120 | * built into one image. If the PSP$ cookie is found, the table is a |
| 121 | * normal directory table. |
| 122 | * |
| 123 | * Modern generations supporting the combo directories require the |
| 124 | * pointer to be at offset 0x14 of the Embedded Firmware Structure, |
| 125 | * regardless of the type of directory used. The --combo-capable |
| 126 | * argument enforces this placement. |
| 127 | * |
| 128 | * TODO: Future work may require fully implementing the PSP_COMBO feature. |
zbao | c3b0b72 | 2016-02-19 13:47:31 +0800 | [diff] [blame] | 129 | */ |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 130 | |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 131 | /* |
| 132 | * Creates the OSI Fletcher checksum. See 8473-1, Appendix C, section C.3. |
| 133 | * The checksum field of the passed PDU does not need to be reset to zero. |
| 134 | * |
| 135 | * The "Fletcher Checksum" was proposed in a paper by John G. Fletcher of |
| 136 | * Lawrence Livermore Labs. The Fletcher Checksum was proposed as an |
| 137 | * alternative to cyclical redundancy checks because it provides error- |
| 138 | * detection properties similar to cyclical redundancy checks but at the |
| 139 | * cost of a simple summation technique. Its characteristics were first |
| 140 | * published in IEEE Transactions on Communications in January 1982. One |
| 141 | * version has been adopted by ISO for use in the class-4 transport layer |
| 142 | * of the network protocol. |
| 143 | * |
| 144 | * This program expects: |
| 145 | * stdin: The input file to compute a checksum for. The input file |
| 146 | * not be longer than 256 bytes. |
| 147 | * stdout: Copied from the input file with the Fletcher's Checksum |
| 148 | * inserted 8 bytes after the beginning of the file. |
| 149 | * stderr: Used to print out error messages. |
| 150 | */ |
Marshall Dawson | 8a45a4d | 2019-02-24 07:18:44 -0700 | [diff] [blame] | 151 | static uint32_t fletcher32(const void *data, int length) |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 152 | { |
| 153 | uint32_t c0; |
| 154 | uint32_t c1; |
| 155 | uint32_t checksum; |
| 156 | int index; |
Marshall Dawson | 8a45a4d | 2019-02-24 07:18:44 -0700 | [diff] [blame] | 157 | const uint16_t *pptr = data; |
| 158 | |
| 159 | length /= 2; |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 160 | |
| 161 | c0 = 0xFFFF; |
| 162 | c1 = 0xFFFF; |
| 163 | |
Marshall Dawson | b85ddc5 | 2019-07-23 07:24:30 -0600 | [diff] [blame] | 164 | while (length) { |
| 165 | index = length >= 359 ? 359 : length; |
| 166 | length -= index; |
Zheng Bao | c88f2b5 | 2021-10-14 16:15:11 +0800 | [diff] [blame] | 167 | do { |
| 168 | c0 += *(pptr++); |
| 169 | c1 += c0; |
| 170 | } while (--index); |
Marshall Dawson | b85ddc5 | 2019-07-23 07:24:30 -0600 | [diff] [blame] | 171 | c0 = (c0 & 0xFFFF) + (c0 >> 16); |
| 172 | c1 = (c1 & 0xFFFF) + (c1 >> 16); |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 173 | } |
| 174 | |
Marshall Dawson | 8a45a4d | 2019-02-24 07:18:44 -0700 | [diff] [blame] | 175 | /* Sums[0,1] mod 64K + overflow */ |
| 176 | c0 = (c0 & 0xFFFF) + (c0 >> 16); |
| 177 | c1 = (c1 & 0xFFFF) + (c1 >> 16); |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 178 | checksum = (c1 << 16) | c0; |
| 179 | |
| 180 | return checksum; |
| 181 | } |
| 182 | |
Martin Roth | 8806f7f | 2016-11-08 10:44:18 -0700 | [diff] [blame] | 183 | static void usage(void) |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 184 | { |
Martin Roth | 0e94062 | 2016-11-08 10:37:53 -0700 | [diff] [blame] | 185 | printf("amdfwtool: Create AMD Firmware combination\n"); |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 186 | printf("Usage: amdfwtool [options] --flashsize <size> --output <filename>\n"); |
| 187 | printf("--xhci <FILE> Add XHCI blob\n"); |
| 188 | printf("--imc <FILE> Add IMC blob\n"); |
| 189 | printf("--gec <FILE> Add GEC blob\n"); |
Martin Roth | 0e94062 | 2016-11-08 10:37:53 -0700 | [diff] [blame] | 190 | |
| 191 | printf("\nPSP options:\n"); |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 192 | printf("--combo-capable Place PSP directory pointer at Embedded\n"); |
| 193 | printf(" Firmware\n"); |
Marshall Dawson | 67d868d | 2019-02-28 11:43:40 -0700 | [diff] [blame] | 194 | printf(" offset able to support combo directory\n"); |
Zheng Bao | 993b43f | 2021-11-10 12:21:46 +0800 | [diff] [blame] | 195 | printf("--use-combo Use the COMBO layout\n"); |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 196 | printf("--multilevel Generate primary and secondary tables\n"); |
| 197 | printf("--nvram <FILE> Add nvram binary\n"); |
| 198 | printf("--soft-fuse Set soft fuse\n"); |
| 199 | printf("--token-unlock Set token unlock\n"); |
Ritul Guru | a2cb340 | 2022-08-29 00:51:08 +0530 | [diff] [blame] | 200 | printf("--nvram-base <HEX_VAL> Base address of nvram\n"); |
| 201 | printf("--nvram-size <HEX_VAL> Size of nvram\n"); |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 202 | printf("--whitelist Set if there is a whitelist\n"); |
| 203 | printf("--use-pspsecureos Set if psp secure OS is needed\n"); |
| 204 | printf("--load-mp2-fw Set if load MP2 firmware\n"); |
| 205 | printf("--load-s0i3 Set if load s0i3 firmware\n"); |
| 206 | printf("--verstage <FILE> Add verstage\n"); |
| 207 | printf("--verstage_sig Add verstage signature\n"); |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 208 | printf("--recovery-ab Use the recovery A/B layout\n"); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 209 | printf("\nBIOS options:\n"); |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 210 | printf("--instance <number> Sets instance field for the next BIOS\n"); |
Zheng Bao | 6f0b361 | 2021-04-27 17:19:43 +0800 | [diff] [blame] | 211 | printf(" firmware\n"); |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 212 | printf("--apcb <FILE> Add AGESA PSP customization block\n"); |
| 213 | printf("--apob-base <HEX_VAL> Destination for AGESA PSP output block\n"); |
| 214 | printf("--apob-nv-base <HEX_VAL> Location of S3 resume data\n"); |
| 215 | printf("--apob-nv-size <HEX_VAL> Size of S3 resume data\n"); |
| 216 | printf("--ucode <FILE> Add microcode patch\n"); |
| 217 | printf("--bios-bin <FILE> Add compressed image; auto source address\n"); |
| 218 | printf("--bios-bin-src <HEX_VAL> Address in flash of source if -V not used\n"); |
| 219 | printf("--bios-bin-dest <HEX_VAL> Destination for uncompressed BIOS\n"); |
| 220 | printf("--bios-uncomp-size <HEX> Uncompressed size of BIOS image\n"); |
| 221 | printf("--output <filename> output filename\n"); |
| 222 | printf("--flashsize <HEX_VAL> ROM size in bytes\n"); |
Marshall Dawson | f4b9b41 | 2017-03-17 16:30:51 -0600 | [diff] [blame] | 223 | printf(" size must be larger than %dKB\n", |
Martin Roth | 0e94062 | 2016-11-08 10:37:53 -0700 | [diff] [blame] | 224 | MIN_ROM_KB); |
Marshall Dawson | f4b9b41 | 2017-03-17 16:30:51 -0600 | [diff] [blame] | 225 | printf(" and must a multiple of 1024\n"); |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 226 | printf("--location Location of Directory\n"); |
| 227 | printf("--anywhere Use any 64-byte aligned addr for Directory\n"); |
| 228 | printf("--sharedmem Location of PSP/FW shared memory\n"); |
| 229 | printf("--sharedmem-size Maximum size of the PSP/FW shared memory\n"); |
Zheng Bao | 6f0b361 | 2021-04-27 17:19:43 +0800 | [diff] [blame] | 230 | printf(" area\n"); |
Matt Papageorge | be4376c | 2020-06-15 11:18:15 -0500 | [diff] [blame] | 231 | printf("\nEmbedded Firmware Structure options used by the PSP:\n"); |
| 232 | printf("--spi-speed <HEX_VAL> SPI fast speed to place in EFS Table\n"); |
| 233 | printf(" 0x0 66.66Mhz\n"); |
| 234 | printf(" 0x1 33.33MHz\n"); |
| 235 | printf(" 0x2 22.22MHz\n"); |
| 236 | printf(" 0x3 16.66MHz\n"); |
| 237 | printf(" 0x4 100MHz\n"); |
| 238 | printf(" 0x5 800KHz\n"); |
| 239 | printf("--spi-read-mode <HEX_VAL> SPI read mode to place in EFS Table\n"); |
| 240 | printf(" 0x0 Normal Read (up to 33M)\n"); |
| 241 | printf(" 0x1 Reserved\n"); |
| 242 | printf(" 0x2 Dual IO (1-1-2)\n"); |
| 243 | printf(" 0x3 Quad IO (1-1-4)\n"); |
| 244 | printf(" 0x4 Dual IO (1-2-2)\n"); |
| 245 | printf(" 0x5 Quad IO (1-4-4)\n"); |
| 246 | printf(" 0x6 Normal Read (up to 66M)\n"); |
| 247 | printf(" 0x7 Fast Read\n"); |
| 248 | printf("--spi-micron-flag <HEX_VAL> Micron SPI part support for RV and later SOC\n"); |
| 249 | printf(" 0x0 Micron parts are not used\n"); |
| 250 | printf(" 0x1 Micron parts are always used\n"); |
| 251 | printf(" 0x2 Micron parts optional, this option is only\n"); |
| 252 | printf(" supported with RN/LCN SOC\n"); |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 253 | printf("\nGeneral options:\n"); |
| 254 | printf("-c|--config <config file> Config file\n"); |
| 255 | printf("-d|--debug Print debug message\n"); |
| 256 | printf("-l|--list List out the firmware files\n"); |
| 257 | printf("-h|--help Show this help\n"); |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 258 | } |
| 259 | |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 260 | amd_fw_entry amd_psp_fw_table[] = { |
Kangheui Won | 3c164e1 | 2021-12-03 20:25:05 +1100 | [diff] [blame] | 261 | { .type = AMD_FW_PSP_PUBKEY, .level = PSP_BOTH | PSP_LVL2_AB, .skip_hashing = true }, |
Zheng Bao | fb9b784 | 2022-02-24 15:15:50 +0800 | [diff] [blame] | 262 | { .type = AMD_FW_PSP_BOOTLOADER, .level = PSP_BOTH | PSP_LVL2_AB }, |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 263 | { .type = AMD_FW_PSP_SECURED_OS, .level = PSP_LVL2 | PSP_LVL2_AB }, |
Arthur Heymans | aafbe13 | 2022-09-30 08:33:28 +0200 | [diff] [blame] | 264 | { .type = AMD_FW_PSP_RECOVERY, .level = PSP_LVL1 }, |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 265 | { .type = AMD_FW_PSP_NVRAM, .level = PSP_LVL2 | PSP_LVL2_AB }, |
Arthur Heymans | aafbe13 | 2022-09-30 08:33:28 +0200 | [diff] [blame] | 266 | { .type = AMD_FW_PSP_RTM_PUBKEY, .level = PSP_BOTH }, |
| 267 | { .type = AMD_FW_PSP_SMU_FIRMWARE, .subprog = 0, .level = PSP_BOTH | PSP_LVL2_AB }, |
| 268 | { .type = AMD_FW_PSP_SMU_FIRMWARE, .subprog = 1, .level = PSP_BOTH | PSP_LVL2_AB }, |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 269 | { .type = AMD_FW_PSP_SMU_FIRMWARE, .subprog = 2, .level = PSP_BOTH | PSP_LVL2_AB }, |
Kangheui Won | 3c164e1 | 2021-12-03 20:25:05 +1100 | [diff] [blame] | 270 | { .type = AMD_FW_PSP_SECURED_DEBUG, .level = PSP_LVL2 | PSP_LVL2_AB, |
| 271 | .skip_hashing = true }, |
Arthur Heymans | 1f05c80 | 2022-10-04 17:50:21 +0200 | [diff] [blame] | 272 | { .type = AMD_FW_ABL_PUBKEY, .level = PSP_BOTH | PSP_BOTH_AB }, |
Arthur Heymans | aafbe13 | 2022-09-30 08:33:28 +0200 | [diff] [blame] | 273 | { .type = AMD_PSP_FUSE_CHAIN, .level = PSP_LVL2 | PSP_LVL2_AB }, |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 274 | { .type = AMD_FW_PSP_TRUSTLETS, .level = PSP_LVL2 | PSP_LVL2_AB }, |
| 275 | { .type = AMD_FW_PSP_TRUSTLETKEY, .level = PSP_LVL2 | PSP_LVL2_AB }, |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 276 | { .type = AMD_FW_PSP_SMU_FIRMWARE2, .level = PSP_BOTH | PSP_LVL2_AB }, |
Arthur Heymans | aafbe13 | 2022-09-30 08:33:28 +0200 | [diff] [blame] | 277 | { .type = AMD_FW_PSP_SMU_FIRMWARE2, .subprog = 1, .level = PSP_BOTH | PSP_LVL2_AB }, |
| 278 | { .type = AMD_FW_PSP_SMU_FIRMWARE2, .subprog = 2, .level = PSP_BOTH | PSP_LVL2_AB }, |
Zheng Bao | 8eba662 | 2022-10-16 20:29:03 +0800 | [diff] [blame] | 279 | { .type = AMD_BOOT_DRIVER, .level = PSP_BOTH | PSP_LVL2_AB }, |
| 280 | { .type = AMD_SOC_DRIVER, .level = PSP_BOTH | PSP_LVL2_AB }, |
| 281 | { .type = AMD_DEBUG_DRIVER, .level = PSP_BOTH | PSP_LVL2_AB }, |
| 282 | { .type = AMD_INTERFACE_DRIVER, .level = PSP_BOTH | PSP_LVL2_AB }, |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 283 | { .type = AMD_DEBUG_UNLOCK, .level = PSP_LVL2 | PSP_LVL2_AB }, |
| 284 | { .type = AMD_HW_IPCFG, .level = PSP_LVL2 | PSP_LVL2_AB }, |
Kangheui Won | 3c164e1 | 2021-12-03 20:25:05 +1100 | [diff] [blame] | 285 | { .type = AMD_WRAPPED_IKEK, .level = PSP_BOTH | PSP_LVL2_AB, .skip_hashing = true }, |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 286 | { .type = AMD_TOKEN_UNLOCK, .level = PSP_BOTH | PSP_LVL2_AB }, |
| 287 | { .type = AMD_SEC_GASKET, .subprog = 0, .level = PSP_BOTH | PSP_LVL2_AB }, |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 288 | { .type = AMD_SEC_GASKET, .subprog = 1, .level = PSP_BOTH | PSP_LVL2_AB }, |
Arthur Heymans | aafbe13 | 2022-09-30 08:33:28 +0200 | [diff] [blame] | 289 | { .type = AMD_SEC_GASKET, .subprog = 2, .level = PSP_BOTH | PSP_LVL2_AB }, |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 290 | { .type = AMD_MP2_FW, .subprog = 0, .level = PSP_LVL2 | PSP_LVL2_AB }, |
Arthur Heymans | aafbe13 | 2022-09-30 08:33:28 +0200 | [diff] [blame] | 291 | { .type = AMD_MP2_FW, .subprog = 1, .level = PSP_LVL2 | PSP_LVL2_AB }, |
| 292 | { .type = AMD_MP2_FW, .subprog = 2, .level = PSP_LVL2 | PSP_LVL2_AB }, |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 293 | { .type = AMD_DRIVER_ENTRIES, .level = PSP_LVL2 | PSP_LVL2_AB }, |
| 294 | { .type = AMD_FW_KVM_IMAGE, .level = PSP_LVL2 | PSP_LVL2_AB }, |
Arthur Heymans | 1f05c80 | 2022-10-04 17:50:21 +0200 | [diff] [blame] | 295 | { .type = AMD_FW_MP5, .subprog = 0, .level = PSP_BOTH | PSP_BOTH_AB }, |
| 296 | { .type = AMD_FW_MP5, .subprog = 1, .level = PSP_BOTH | PSP_BOTH_AB }, |
| 297 | { .type = AMD_FW_MP5, .subprog = 2, .level = PSP_BOTH | PSP_BOTH_AB }, |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 298 | { .type = AMD_S0I3_DRIVER, .level = PSP_LVL2 | PSP_LVL2_AB }, |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 299 | { .type = AMD_ABL0, .level = PSP_BOTH | PSP_LVL2_AB }, |
| 300 | { .type = AMD_ABL1, .level = PSP_BOTH | PSP_LVL2_AB }, |
| 301 | { .type = AMD_ABL2, .level = PSP_BOTH | PSP_LVL2_AB }, |
| 302 | { .type = AMD_ABL3, .level = PSP_BOTH | PSP_LVL2_AB }, |
| 303 | { .type = AMD_ABL4, .level = PSP_BOTH | PSP_LVL2_AB }, |
| 304 | { .type = AMD_ABL5, .level = PSP_BOTH | PSP_LVL2_AB }, |
| 305 | { .type = AMD_ABL6, .level = PSP_BOTH | PSP_LVL2_AB }, |
| 306 | { .type = AMD_ABL7, .level = PSP_BOTH | PSP_LVL2_AB }, |
Arthur Heymans | 1f05c80 | 2022-10-04 17:50:21 +0200 | [diff] [blame] | 307 | { .type = AMD_SEV_DATA, .level = PSP_LVL2 | PSP_LVL2_AB }, |
| 308 | { .type = AMD_SEV_CODE, .level = PSP_LVL2 | PSP_LVL2_AB }, |
Karthikeyan Ramasubramanian | 51f914d | 2022-07-28 16:42:12 -0600 | [diff] [blame] | 309 | { .type = AMD_FW_PSP_WHITELIST, .level = PSP_LVL2 | PSP_LVL2_AB }, |
Arthur Heymans | aafbe13 | 2022-09-30 08:33:28 +0200 | [diff] [blame] | 310 | { .type = AMD_VBIOS_BTLOADER, .level = PSP_BOTH | PSP_LVL2_AB }, |
Arthur Heymans | 1f05c80 | 2022-10-04 17:50:21 +0200 | [diff] [blame] | 311 | { .type = AMD_FW_DXIO, .level = PSP_BOTH | PSP_BOTH_AB }, |
Arthur Heymans | aafbe13 | 2022-09-30 08:33:28 +0200 | [diff] [blame] | 312 | { .type = AMD_FW_USB_PHY, .level = PSP_LVL2 | PSP_LVL2_AB }, |
| 313 | { .type = AMD_FW_TOS_SEC_POLICY, .level = PSP_BOTH | PSP_LVL2_AB }, |
| 314 | { .type = AMD_FW_DRTM_TA, .level = PSP_LVL2 | PSP_LVL2_AB }, |
| 315 | { .type = AMD_FW_KEYDB_BL, .level = PSP_BOTH | PSP_LVL2_AB }, |
| 316 | { .type = AMD_FW_KEYDB_TOS, .level = PSP_LVL2 | PSP_LVL2_AB }, |
Karthikeyan Ramasubramanian | 234e370 | 2022-07-25 09:49:24 -0600 | [diff] [blame] | 317 | { .type = AMD_FW_PSP_VERSTAGE, .level = PSP_BOTH | PSP_LVL2_AB }, |
| 318 | { .type = AMD_FW_VERSTAGE_SIG, .level = PSP_BOTH | PSP_LVL2_AB }, |
Arthur Heymans | aafbe13 | 2022-09-30 08:33:28 +0200 | [diff] [blame] | 319 | { .type = AMD_RPMC_NVRAM, .level = PSP_LVL2 | PSP_LVL2_AB }, |
| 320 | { .type = AMD_FW_SPL, .level = PSP_LVL2 | PSP_LVL2_AB }, |
| 321 | { .type = AMD_FW_DMCU_ERAM, .level = PSP_LVL2 | PSP_LVL2_AB }, |
| 322 | { .type = AMD_FW_DMCU_ISR, .level = PSP_LVL2 | PSP_LVL2_AB }, |
| 323 | { .type = AMD_FW_MSMU, .level = PSP_LVL2 | PSP_LVL2_AB }, |
| 324 | { .type = AMD_FW_SPIROM_CFG, .level = PSP_LVL2 | PSP_LVL2_AB }, |
Zheng Bao | 8eba662 | 2022-10-16 20:29:03 +0800 | [diff] [blame] | 325 | { .type = AMD_FW_MPIO, .level = PSP_LVL2 | PSP_BOTH_AB }, |
| 326 | { .type = AMD_FW_PSP_SMUSCS, .level = PSP_BOTH | PSP_LVL2_AB }, |
Arthur Heymans | aafbe13 | 2022-09-30 08:33:28 +0200 | [diff] [blame] | 327 | { .type = AMD_FW_DMCUB, .level = PSP_LVL2 | PSP_LVL2_AB }, |
| 328 | { .type = AMD_FW_PSP_BOOTLOADER_AB, .level = PSP_LVL2 | PSP_LVL2_AB }, |
Zheng Bao | 85ee1fd | 2023-01-30 13:52:30 +0800 | [diff] [blame] | 329 | { .type = AMD_RIB, .subprog = 0, .level = PSP_LVL2 | PSP_LVL2_AB }, |
| 330 | { .type = AMD_RIB, .subprog = 1, .level = PSP_LVL2 | PSP_LVL2_AB }, |
Arthur Heymans | 1f05c80 | 2022-10-04 17:50:21 +0200 | [diff] [blame] | 331 | { .type = AMD_FW_MPDMA_TF, .level = PSP_BOTH | PSP_BOTH_AB }, |
Arthur Heymans | aafbe13 | 2022-09-30 08:33:28 +0200 | [diff] [blame] | 332 | { .type = AMD_TA_IKEK, .level = PSP_BOTH | PSP_LVL2_AB, .skip_hashing = true }, |
Arthur Heymans | 1f05c80 | 2022-10-04 17:50:21 +0200 | [diff] [blame] | 333 | { .type = AMD_FW_GMI3_PHY, .level = PSP_BOTH | PSP_BOTH_AB }, |
| 334 | { .type = AMD_FW_MPDMA_PM, .level = PSP_BOTH | PSP_BOTH_AB }, |
Zheng Bao | 8eba662 | 2022-10-16 20:29:03 +0800 | [diff] [blame] | 335 | { .type = AMD_FW_AMF_SRAM, .level = PSP_LVL2 | PSP_LVL2_AB }, |
| 336 | { .type = AMD_FW_AMF_DRAM, .inst = 0, .level = PSP_LVL2 | PSP_LVL2_AB }, |
| 337 | { .type = AMD_FW_AMF_DRAM, .inst = 1, .level = PSP_LVL2 | PSP_LVL2_AB }, |
| 338 | { .type = AMD_FW_FCFG_TABLE, .level = PSP_LVL2 | PSP_LVL2_AB }, |
| 339 | { .type = AMD_FW_AMF_WLAN, .inst = 0, .level = PSP_LVL2 | PSP_LVL2_AB }, |
| 340 | { .type = AMD_FW_AMF_WLAN, .inst = 1, .level = PSP_LVL2 | PSP_LVL2_AB }, |
| 341 | { .type = AMD_FW_AMF_MFD, .level = PSP_LVL2 | PSP_LVL2_AB }, |
| 342 | { .type = AMD_TA_IKEK, .level = PSP_BOTH | PSP_LVL2_AB, .skip_hashing = true }, |
| 343 | { .type = AMD_FW_MPCCX, .level = PSP_LVL2 | PSP_LVL2_AB }, |
| 344 | { .type = AMD_FW_LSDMA, .level = PSP_LVL2 | PSP_LVL2_AB }, |
| 345 | { .type = AMD_FW_C20_MP, .level = PSP_BOTH | PSP_LVL2_AB }, |
| 346 | { .type = AMD_FW_MINIMSMU, .inst = 0, .level = PSP_BOTH | PSP_LVL2_AB }, |
| 347 | { .type = AMD_FW_MINIMSMU, .inst = 1, .level = PSP_BOTH | PSP_LVL2_AB }, |
| 348 | { .type = AMD_FW_SRAM_FW_EXT, .level = PSP_LVL2 | PSP_LVL2_AB }, |
Fred Reitberger | c4f3a33 | 2023-02-07 12:12:40 -0500 | [diff] [blame] | 349 | { .type = AMD_FW_UMSMU, .level = PSP_LVL2 | PSP_LVL2_AB }, |
zbao | c3a08a9 | 2016-03-02 14:47:27 +0800 | [diff] [blame] | 350 | { .type = AMD_FW_INVALID }, |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 351 | }; |
| 352 | |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 353 | amd_fw_entry amd_fw_table[] = { |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 354 | { .type = AMD_FW_XHCI }, |
| 355 | { .type = AMD_FW_IMC }, |
| 356 | { .type = AMD_FW_GEC }, |
zbao | c3a08a9 | 2016-03-02 14:47:27 +0800 | [diff] [blame] | 357 | { .type = AMD_FW_INVALID }, |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 358 | }; |
| 359 | |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 360 | amd_bios_entry amd_bios_table[] = { |
Zheng Bao | bf29a0d | 2020-12-03 23:00:48 +0800 | [diff] [blame] | 361 | { .type = AMD_BIOS_RTM_PUBKEY, .inst = 0, .level = BDT_BOTH }, |
Ritul Guru | 9a321f3 | 2022-07-29 11:06:40 +0530 | [diff] [blame] | 362 | { .type = AMD_BIOS_SIG, .inst = 0, .level = BDT_BOTH }, |
Marshall Dawson | 0581bf6 | 2019-09-25 11:03:53 -0600 | [diff] [blame] | 363 | { .type = AMD_BIOS_APCB, .inst = 0, .level = BDT_BOTH }, |
| 364 | { .type = AMD_BIOS_APCB, .inst = 1, .level = BDT_BOTH }, |
| 365 | { .type = AMD_BIOS_APCB, .inst = 2, .level = BDT_BOTH }, |
| 366 | { .type = AMD_BIOS_APCB, .inst = 3, .level = BDT_BOTH }, |
| 367 | { .type = AMD_BIOS_APCB, .inst = 4, .level = BDT_BOTH }, |
Rob Barnes | 18fd26c | 2020-03-03 10:35:02 -0700 | [diff] [blame] | 368 | { .type = AMD_BIOS_APCB, .inst = 5, .level = BDT_BOTH }, |
| 369 | { .type = AMD_BIOS_APCB, .inst = 6, .level = BDT_BOTH }, |
| 370 | { .type = AMD_BIOS_APCB, .inst = 7, .level = BDT_BOTH }, |
| 371 | { .type = AMD_BIOS_APCB, .inst = 8, .level = BDT_BOTH }, |
| 372 | { .type = AMD_BIOS_APCB, .inst = 9, .level = BDT_BOTH }, |
| 373 | { .type = AMD_BIOS_APCB, .inst = 10, .level = BDT_BOTH }, |
| 374 | { .type = AMD_BIOS_APCB, .inst = 11, .level = BDT_BOTH }, |
| 375 | { .type = AMD_BIOS_APCB, .inst = 12, .level = BDT_BOTH }, |
| 376 | { .type = AMD_BIOS_APCB, .inst = 13, .level = BDT_BOTH }, |
| 377 | { .type = AMD_BIOS_APCB, .inst = 14, .level = BDT_BOTH }, |
| 378 | { .type = AMD_BIOS_APCB, .inst = 15, .level = BDT_BOTH }, |
Marshall Dawson | 2dd3b5c | 2020-01-03 17:57:48 -0700 | [diff] [blame] | 379 | { .type = AMD_BIOS_APCB_BK, .inst = 0, .level = BDT_BOTH }, |
| 380 | { .type = AMD_BIOS_APCB_BK, .inst = 1, .level = BDT_BOTH }, |
| 381 | { .type = AMD_BIOS_APCB_BK, .inst = 2, .level = BDT_BOTH }, |
| 382 | { .type = AMD_BIOS_APCB_BK, .inst = 3, .level = BDT_BOTH }, |
| 383 | { .type = AMD_BIOS_APCB_BK, .inst = 4, .level = BDT_BOTH }, |
Rob Barnes | 18fd26c | 2020-03-03 10:35:02 -0700 | [diff] [blame] | 384 | { .type = AMD_BIOS_APCB_BK, .inst = 5, .level = BDT_BOTH }, |
| 385 | { .type = AMD_BIOS_APCB_BK, .inst = 6, .level = BDT_BOTH }, |
| 386 | { .type = AMD_BIOS_APCB_BK, .inst = 7, .level = BDT_BOTH }, |
| 387 | { .type = AMD_BIOS_APCB_BK, .inst = 8, .level = BDT_BOTH }, |
| 388 | { .type = AMD_BIOS_APCB_BK, .inst = 9, .level = BDT_BOTH }, |
| 389 | { .type = AMD_BIOS_APCB_BK, .inst = 10, .level = BDT_BOTH }, |
| 390 | { .type = AMD_BIOS_APCB_BK, .inst = 11, .level = BDT_BOTH }, |
| 391 | { .type = AMD_BIOS_APCB_BK, .inst = 12, .level = BDT_BOTH }, |
| 392 | { .type = AMD_BIOS_APCB_BK, .inst = 13, .level = BDT_BOTH }, |
| 393 | { .type = AMD_BIOS_APCB_BK, .inst = 14, .level = BDT_BOTH }, |
| 394 | { .type = AMD_BIOS_APCB_BK, .inst = 15, .level = BDT_BOTH }, |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 395 | { .type = AMD_BIOS_APOB, .level = BDT_BOTH }, |
| 396 | { .type = AMD_BIOS_BIN, |
Zheng Bao | 3d426f3 | 2022-10-16 20:34:57 +0800 | [diff] [blame] | 397 | .reset = 1, .copy = 1, .zlib = 1, .inst = 0, .level = BDT_BOTH }, |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 398 | { .type = AMD_BIOS_APOB_NV, .level = BDT_LVL2 }, |
| 399 | { .type = AMD_BIOS_PMUI, .inst = 1, .subpr = 0, .level = BDT_BOTH }, |
| 400 | { .type = AMD_BIOS_PMUD, .inst = 1, .subpr = 0, .level = BDT_BOTH }, |
Zheng Bao | e220faa | 2022-02-17 17:22:15 +0800 | [diff] [blame] | 401 | { .type = AMD_BIOS_PMUI, .inst = 2, .subpr = 0, .level = BDT_BOTH }, |
| 402 | { .type = AMD_BIOS_PMUD, .inst = 2, .subpr = 0, .level = BDT_BOTH }, |
Arthur Heymans | a83c502 | 2022-10-04 20:37:10 +0200 | [diff] [blame] | 403 | { .type = AMD_BIOS_PMUI, .inst = 3, .subpr = 0, .level = BDT_BOTH }, |
| 404 | { .type = AMD_BIOS_PMUD, .inst = 3, .subpr = 0, .level = BDT_BOTH }, |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 405 | { .type = AMD_BIOS_PMUI, .inst = 4, .subpr = 0, .level = BDT_BOTH }, |
| 406 | { .type = AMD_BIOS_PMUD, .inst = 4, .subpr = 0, .level = BDT_BOTH }, |
Zheng Bao | 8eba662 | 2022-10-16 20:29:03 +0800 | [diff] [blame] | 407 | { .type = AMD_BIOS_PMUI, .inst = 5, .subpr = 0, .level = BDT_BOTH }, |
| 408 | { .type = AMD_BIOS_PMUD, .inst = 5, .subpr = 0, .level = BDT_BOTH }, |
| 409 | { .type = AMD_BIOS_PMUI, .inst = 6, .subpr = 0, .level = BDT_BOTH }, |
| 410 | { .type = AMD_BIOS_PMUD, .inst = 6, .subpr = 0, .level = BDT_BOTH }, |
| 411 | { .type = AMD_BIOS_PMUI, .inst = 7, .subpr = 0, .level = BDT_BOTH }, |
| 412 | { .type = AMD_BIOS_PMUD, .inst = 7, .subpr = 0, .level = BDT_BOTH }, |
Arthur Heymans | a83c502 | 2022-10-04 20:37:10 +0200 | [diff] [blame] | 413 | { .type = AMD_BIOS_PMUI, .inst = 9, .subpr = 0, .level = BDT_BOTH }, |
| 414 | { .type = AMD_BIOS_PMUD, .inst = 9, .subpr = 0, .level = BDT_BOTH }, |
| 415 | { .type = AMD_BIOS_PMUI, .inst = 10, .subpr = 0, .level = BDT_BOTH }, |
| 416 | { .type = AMD_BIOS_PMUD, .inst = 10, .subpr = 0, .level = BDT_BOTH }, |
Zheng Bao | 8eba662 | 2022-10-16 20:29:03 +0800 | [diff] [blame] | 417 | { .type = AMD_BIOS_PMUI, .inst = 11, .subpr = 0, .level = BDT_BOTH }, |
| 418 | { .type = AMD_BIOS_PMUD, .inst = 11, .subpr = 0, .level = BDT_BOTH }, |
| 419 | { .type = AMD_BIOS_PMUI, .inst = 12, .subpr = 0, .level = BDT_BOTH }, |
| 420 | { .type = AMD_BIOS_PMUD, .inst = 12, .subpr = 0, .level = BDT_BOTH }, |
| 421 | { .type = AMD_BIOS_PMUI, .inst = 13, .subpr = 0, .level = BDT_BOTH }, |
| 422 | { .type = AMD_BIOS_PMUD, .inst = 13, .subpr = 0, .level = BDT_BOTH }, |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 423 | { .type = AMD_BIOS_PMUI, .inst = 1, .subpr = 1, .level = BDT_BOTH }, |
| 424 | { .type = AMD_BIOS_PMUD, .inst = 1, .subpr = 1, .level = BDT_BOTH }, |
Zheng Bao | e220faa | 2022-02-17 17:22:15 +0800 | [diff] [blame] | 425 | { .type = AMD_BIOS_PMUI, .inst = 2, .subpr = 1, .level = BDT_BOTH }, |
| 426 | { .type = AMD_BIOS_PMUD, .inst = 2, .subpr = 1, .level = BDT_BOTH }, |
Arthur Heymans | a83c502 | 2022-10-04 20:37:10 +0200 | [diff] [blame] | 427 | { .type = AMD_BIOS_PMUI, .inst = 3, .subpr = 1, .level = BDT_BOTH }, |
| 428 | { .type = AMD_BIOS_PMUD, .inst = 3, .subpr = 1, .level = BDT_BOTH }, |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 429 | { .type = AMD_BIOS_PMUI, .inst = 4, .subpr = 1, .level = BDT_BOTH }, |
| 430 | { .type = AMD_BIOS_PMUD, .inst = 4, .subpr = 1, .level = BDT_BOTH }, |
Zheng Bao | 8eba662 | 2022-10-16 20:29:03 +0800 | [diff] [blame] | 431 | { .type = AMD_BIOS_PMUI, .inst = 5, .subpr = 1, .level = BDT_BOTH }, |
| 432 | { .type = AMD_BIOS_PMUD, .inst = 5, .subpr = 1, .level = BDT_BOTH }, |
| 433 | { .type = AMD_BIOS_PMUI, .inst = 6, .subpr = 1, .level = BDT_BOTH }, |
| 434 | { .type = AMD_BIOS_PMUD, .inst = 6, .subpr = 1, .level = BDT_BOTH }, |
| 435 | { .type = AMD_BIOS_PMUI, .inst = 7, .subpr = 1, .level = BDT_BOTH }, |
| 436 | { .type = AMD_BIOS_PMUD, .inst = 7, .subpr = 1, .level = BDT_BOTH }, |
Arthur Heymans | a83c502 | 2022-10-04 20:37:10 +0200 | [diff] [blame] | 437 | { .type = AMD_BIOS_PMUI, .inst = 9, .subpr = 1, .level = BDT_BOTH }, |
| 438 | { .type = AMD_BIOS_PMUD, .inst = 9, .subpr = 1, .level = BDT_BOTH }, |
| 439 | { .type = AMD_BIOS_PMUI, .inst = 10, .subpr = 1, .level = BDT_BOTH }, |
| 440 | { .type = AMD_BIOS_PMUD, .inst = 10, .subpr = 1, .level = BDT_BOTH }, |
Zheng Bao | 8eba662 | 2022-10-16 20:29:03 +0800 | [diff] [blame] | 441 | { .type = AMD_BIOS_PMUI, .inst = 11, .subpr = 1, .level = BDT_BOTH }, |
| 442 | { .type = AMD_BIOS_PMUD, .inst = 11, .subpr = 1, .level = BDT_BOTH }, |
| 443 | { .type = AMD_BIOS_PMUI, .inst = 12, .subpr = 1, .level = BDT_BOTH }, |
| 444 | { .type = AMD_BIOS_PMUD, .inst = 12, .subpr = 1, .level = BDT_BOTH }, |
| 445 | { .type = AMD_BIOS_PMUI, .inst = 13, .subpr = 1, .level = BDT_BOTH }, |
| 446 | { .type = AMD_BIOS_PMUD, .inst = 13, .subpr = 1, .level = BDT_BOTH }, |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 447 | { .type = AMD_BIOS_UCODE, .inst = 0, .level = BDT_LVL2 }, |
| 448 | { .type = AMD_BIOS_UCODE, .inst = 1, .level = BDT_LVL2 }, |
| 449 | { .type = AMD_BIOS_UCODE, .inst = 2, .level = BDT_LVL2 }, |
Arthur Heymans | a83c502 | 2022-10-04 20:37:10 +0200 | [diff] [blame] | 450 | { .type = AMD_BIOS_UCODE, .inst = 3, .level = BDT_LVL2 }, |
| 451 | { .type = AMD_BIOS_UCODE, .inst = 4, .level = BDT_LVL2 }, |
| 452 | { .type = AMD_BIOS_UCODE, .inst = 5, .level = BDT_LVL2 }, |
| 453 | { .type = AMD_BIOS_UCODE, .inst = 6, .level = BDT_LVL2 }, |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 454 | { .type = AMD_BIOS_MP2_CFG, .level = BDT_LVL2 }, |
Martin Roth | 9455474 | 2020-04-14 14:59:36 -0600 | [diff] [blame] | 455 | { .type = AMD_BIOS_PSP_SHARED_MEM, .inst = 0, .level = BDT_BOTH }, |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 456 | { .type = AMD_BIOS_INVALID }, |
| 457 | }; |
| 458 | |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 459 | typedef struct _context { |
| 460 | char *rom; /* target buffer, size of flash device */ |
| 461 | uint32_t rom_size; /* size of flash device */ |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 462 | uint32_t address_mode; /* 0:abs address; 1:relative to flash; 2: relative to table */ |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 463 | uint32_t current; /* pointer within flash & proxy buffer */ |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 464 | uint32_t current_table; |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 465 | } context; |
| 466 | |
| 467 | #define RUN_BASE(ctx) (0xFFFFFFFF - (ctx).rom_size + 1) |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 468 | #define RUN_OFFSET_MODE(ctx, offset, mode) \ |
Robert Zieba | 29bc79f | 2022-03-14 15:59:12 -0600 | [diff] [blame] | 469 | ((mode) == AMD_ADDR_PHYSICAL ? RUN_BASE(ctx) + (offset) : \ |
| 470 | ((mode) == AMD_ADDR_REL_BIOS ? (offset) : \ |
| 471 | ((mode) == AMD_ADDR_REL_TAB ? (offset) - ctx.current_table : (offset)))) |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 472 | #define RUN_OFFSET(ctx, offset) RUN_OFFSET_MODE((ctx), (offset), (ctx).address_mode) |
Robert Zieba | 29bc79f | 2022-03-14 15:59:12 -0600 | [diff] [blame] | 473 | #define RUN_TO_OFFSET(ctx, run) ((ctx).address_mode == AMD_ADDR_PHYSICAL ? \ |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 474 | (run) - RUN_BASE(ctx) : (run)) /* TODO: */ |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 475 | #define RUN_CURRENT(ctx) RUN_OFFSET((ctx), (ctx).current) |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 476 | /* The mode in entry can not be higher than the header's. |
| 477 | For example, if table mode is 0, all the entry mode will be 0. */ |
| 478 | #define RUN_CURRENT_MODE(ctx, mode) RUN_OFFSET_MODE((ctx), (ctx).current, \ |
| 479 | (ctx).address_mode < (mode) ? (ctx).address_mode : (mode)) |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 480 | #define BUFF_OFFSET(ctx, offset) ((void *)((ctx).rom + (offset))) |
| 481 | #define BUFF_CURRENT(ctx) BUFF_OFFSET((ctx), (ctx).current) |
| 482 | #define BUFF_TO_RUN(ctx, ptr) RUN_OFFSET((ctx), ((char *)(ptr) - (ctx).rom)) |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 483 | #define BUFF_TO_RUN_MODE(ctx, ptr, mode) RUN_OFFSET_MODE((ctx), ((char *)(ptr) - (ctx).rom), \ |
| 484 | (ctx).address_mode < (mode) ? (ctx).address_mode : (mode)) |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 485 | #define BUFF_ROOM(ctx) ((ctx).rom_size - (ctx).current) |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 486 | /* Only set the address mode in entry if the table is mode 2. */ |
| 487 | #define SET_ADDR_MODE(table, mode) \ |
| 488 | ((table)->header.additional_info_fields.address_mode == \ |
Robert Zieba | 29bc79f | 2022-03-14 15:59:12 -0600 | [diff] [blame] | 489 | AMD_ADDR_REL_TAB ? (mode) : 0) |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 490 | #define SET_ADDR_MODE_BY_TABLE(table) \ |
| 491 | SET_ADDR_MODE((table), (table)->header.additional_info_fields.address_mode) |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 492 | |
Zheng Bao | 5164e4b | 2021-10-30 12:09:07 +0800 | [diff] [blame] | 493 | void assert_fw_entry(uint32_t count, uint32_t max, context *ctx) |
| 494 | { |
| 495 | if (count >= max) { |
| 496 | fprintf(stderr, "Error: BIOS entries (%d) exceeds max allowed items " |
| 497 | "(%d)\n", count, max); |
| 498 | free(ctx->rom); |
| 499 | exit(1); |
| 500 | } |
| 501 | } |
| 502 | |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 503 | static void *new_psp_dir(context *ctx, int multi) |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 504 | { |
| 505 | void *ptr; |
| 506 | |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 507 | /* |
| 508 | * Force both onto boundary when multi. Primary table is after |
| 509 | * updatable table, so alignment ensures primary can stay intact |
| 510 | * if secondary is reprogrammed. |
| 511 | */ |
| 512 | if (multi) |
Elyes Haouas | 7d67a19 | 2022-10-14 09:58:29 +0200 | [diff] [blame] | 513 | ctx->current = ALIGN_UP(ctx->current, TABLE_ERASE_ALIGNMENT); |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 514 | else |
Elyes Haouas | 7d67a19 | 2022-10-14 09:58:29 +0200 | [diff] [blame] | 515 | ctx->current = ALIGN_UP(ctx->current, TABLE_ALIGNMENT); |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 516 | |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 517 | ptr = BUFF_CURRENT(*ctx); |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 518 | ((psp_directory_header *)ptr)->num_entries = 0; |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 519 | ((psp_directory_header *)ptr)->additional_info = 0; |
| 520 | ((psp_directory_header *)ptr)->additional_info_fields.address_mode = ctx->address_mode; |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 521 | ctx->current += sizeof(psp_directory_header) |
| 522 | + MAX_PSP_ENTRIES * sizeof(psp_directory_entry); |
| 523 | return ptr; |
| 524 | } |
| 525 | |
Zheng Bao | fdd47ef | 2021-09-17 13:30:08 +0800 | [diff] [blame] | 526 | static void *new_ish_dir(context *ctx) |
| 527 | { |
| 528 | void *ptr; |
Elyes Haouas | 7d67a19 | 2022-10-14 09:58:29 +0200 | [diff] [blame] | 529 | ctx->current = ALIGN_UP(ctx->current, TABLE_ALIGNMENT); |
Zheng Bao | fdd47ef | 2021-09-17 13:30:08 +0800 | [diff] [blame] | 530 | ptr = BUFF_CURRENT(*ctx); |
| 531 | ctx->current += TABLE_ALIGNMENT; |
| 532 | return ptr; |
| 533 | } |
| 534 | |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 535 | static void *new_combo_dir(context *ctx) |
| 536 | { |
| 537 | void *ptr; |
| 538 | |
Elyes Haouas | 7d67a19 | 2022-10-14 09:58:29 +0200 | [diff] [blame] | 539 | ctx->current = ALIGN_UP(ctx->current, TABLE_ALIGNMENT); |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 540 | ptr = BUFF_CURRENT(*ctx); |
| 541 | ctx->current += sizeof(psp_combo_header) |
| 542 | + MAX_COMBO_ENTRIES * sizeof(psp_combo_entry); |
| 543 | return ptr; |
| 544 | } |
| 545 | |
Zheng Bao | bf29a0d | 2020-12-03 23:00:48 +0800 | [diff] [blame] | 546 | static void fill_dir_header(void *directory, uint32_t count, uint32_t cookie, context *ctx) |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 547 | { |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 548 | psp_combo_directory *cdir = directory; |
| 549 | psp_directory_table *dir = directory; |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 550 | bios_directory_table *bdir = directory; |
Zheng Bao | bf29a0d | 2020-12-03 23:00:48 +0800 | [diff] [blame] | 551 | uint32_t table_size = 0; |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 552 | |
| 553 | if (!count) |
| 554 | return; |
Zheng Bao | b035f58 | 2021-05-27 11:26:12 +0800 | [diff] [blame] | 555 | if (ctx == NULL || directory == NULL) { |
| 556 | fprintf(stderr, "Calling %s with NULL pointers\n", __func__); |
| 557 | return; |
| 558 | } |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 559 | |
Zheng Bao | bf29a0d | 2020-12-03 23:00:48 +0800 | [diff] [blame] | 560 | /* The table size needs to be 0x1000 aligned. So align the end of table. */ |
Elyes Haouas | 7d67a19 | 2022-10-14 09:58:29 +0200 | [diff] [blame] | 561 | ctx->current = ALIGN_UP(ctx->current, TABLE_ALIGNMENT); |
Zheng Bao | bf29a0d | 2020-12-03 23:00:48 +0800 | [diff] [blame] | 562 | |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 563 | switch (cookie) { |
| 564 | case PSP2_COOKIE: |
Marshall Dawson | a378c22 | 2019-03-04 16:52:07 -0700 | [diff] [blame] | 565 | /* caller is responsible for lookup mode */ |
Marshall Dawson | a378c22 | 2019-03-04 16:52:07 -0700 | [diff] [blame] | 566 | cdir->header.cookie = cookie; |
| 567 | cdir->header.num_entries = count; |
| 568 | cdir->header.reserved[0] = 0; |
| 569 | cdir->header.reserved[1] = 0; |
| 570 | /* checksum everything that comes after the Checksum field */ |
| 571 | cdir->header.checksum = fletcher32(&cdir->header.num_entries, |
| 572 | count * sizeof(psp_combo_entry) |
| 573 | + sizeof(cdir->header.num_entries) |
| 574 | + sizeof(cdir->header.lookup) |
| 575 | + 2 * sizeof(cdir->header.reserved[0])); |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 576 | break; |
| 577 | case PSP_COOKIE: |
| 578 | case PSPL2_COOKIE: |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 579 | table_size = ctx->current - ctx->current_table; |
Zheng Bao | bf29a0d | 2020-12-03 23:00:48 +0800 | [diff] [blame] | 580 | if ((table_size % TABLE_ALIGNMENT) != 0) { |
| 581 | fprintf(stderr, "The PSP table size should be 4K aligned\n"); |
| 582 | exit(1); |
| 583 | } |
Marshall Dawson | a378c22 | 2019-03-04 16:52:07 -0700 | [diff] [blame] | 584 | dir->header.cookie = cookie; |
| 585 | dir->header.num_entries = count; |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 586 | dir->header.additional_info_fields.dir_size = table_size / TABLE_ALIGNMENT; |
| 587 | dir->header.additional_info_fields.spi_block_size = 1; |
| 588 | dir->header.additional_info_fields.base_addr = 0; |
Marshall Dawson | a378c22 | 2019-03-04 16:52:07 -0700 | [diff] [blame] | 589 | /* checksum everything that comes after the Checksum field */ |
| 590 | dir->header.checksum = fletcher32(&dir->header.num_entries, |
Marshall Dawson | 8a45a4d | 2019-02-24 07:18:44 -0700 | [diff] [blame] | 591 | count * sizeof(psp_directory_entry) |
Marshall Dawson | a378c22 | 2019-03-04 16:52:07 -0700 | [diff] [blame] | 592 | + sizeof(dir->header.num_entries) |
Zheng Bao | bf29a0d | 2020-12-03 23:00:48 +0800 | [diff] [blame] | 593 | + sizeof(dir->header.additional_info)); |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 594 | break; |
Zheng Bao | 96a3371 | 2021-06-11 15:54:40 +0800 | [diff] [blame] | 595 | case BHD_COOKIE: |
| 596 | case BHDL2_COOKIE: |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 597 | table_size = ctx->current - ctx->current_table; |
Zheng Bao | bf29a0d | 2020-12-03 23:00:48 +0800 | [diff] [blame] | 598 | if ((table_size % TABLE_ALIGNMENT) != 0) { |
| 599 | fprintf(stderr, "The BIOS table size should be 4K aligned\n"); |
| 600 | exit(1); |
| 601 | } |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 602 | bdir->header.cookie = cookie; |
| 603 | bdir->header.num_entries = count; |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 604 | bdir->header.additional_info_fields.dir_size = table_size / TABLE_ALIGNMENT; |
| 605 | bdir->header.additional_info_fields.spi_block_size = 1; |
| 606 | bdir->header.additional_info_fields.base_addr = 0; |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 607 | /* checksum everything that comes after the Checksum field */ |
| 608 | bdir->header.checksum = fletcher32(&bdir->header.num_entries, |
| 609 | count * sizeof(bios_directory_entry) |
| 610 | + sizeof(bdir->header.num_entries) |
Zheng Bao | bf29a0d | 2020-12-03 23:00:48 +0800 | [diff] [blame] | 611 | + sizeof(bdir->header.additional_info)); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 612 | break; |
Marshall Dawson | a378c22 | 2019-03-04 16:52:07 -0700 | [diff] [blame] | 613 | } |
Zheng Bao | bf29a0d | 2020-12-03 23:00:48 +0800 | [diff] [blame] | 614 | |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 615 | } |
| 616 | |
Marshall Dawson | 8e0dca0 | 2019-02-27 18:40:49 -0700 | [diff] [blame] | 617 | static ssize_t copy_blob(void *dest, const char *src_file, size_t room) |
| 618 | { |
| 619 | int fd; |
| 620 | struct stat fd_stat; |
| 621 | ssize_t bytes; |
| 622 | |
| 623 | fd = open(src_file, O_RDONLY); |
| 624 | if (fd < 0) { |
Zheng Bao | 77a2c67 | 2020-10-01 17:05:43 +0800 | [diff] [blame] | 625 | fprintf(stderr, "Error opening file: %s: %s\n", |
Eric Peers | af50567 | 2020-03-05 16:04:15 -0700 | [diff] [blame] | 626 | src_file, strerror(errno)); |
Marshall Dawson | 8e0dca0 | 2019-02-27 18:40:49 -0700 | [diff] [blame] | 627 | return -1; |
| 628 | } |
| 629 | |
| 630 | if (fstat(fd, &fd_stat)) { |
Zheng Bao | 77a2c67 | 2020-10-01 17:05:43 +0800 | [diff] [blame] | 631 | fprintf(stderr, "fstat error: %s\n", strerror(errno)); |
Jacob Garber | 967f862 | 2019-07-02 10:35:10 -0600 | [diff] [blame] | 632 | close(fd); |
Marshall Dawson | 8e0dca0 | 2019-02-27 18:40:49 -0700 | [diff] [blame] | 633 | return -2; |
| 634 | } |
| 635 | |
Zheng Bao | 6d402ac | 2020-10-01 16:16:30 +0800 | [diff] [blame] | 636 | if ((size_t)fd_stat.st_size > room) { |
Zheng Bao | 77a2c67 | 2020-10-01 17:05:43 +0800 | [diff] [blame] | 637 | fprintf(stderr, "Error: %s will not fit. Exiting.\n", src_file); |
Jacob Garber | 967f862 | 2019-07-02 10:35:10 -0600 | [diff] [blame] | 638 | close(fd); |
Marshall Dawson | 8e0dca0 | 2019-02-27 18:40:49 -0700 | [diff] [blame] | 639 | return -3; |
| 640 | } |
| 641 | |
| 642 | bytes = read(fd, dest, (size_t)fd_stat.st_size); |
| 643 | close(fd); |
| 644 | if (bytes != (ssize_t)fd_stat.st_size) { |
Zheng Bao | 77a2c67 | 2020-10-01 17:05:43 +0800 | [diff] [blame] | 645 | fprintf(stderr, "Error while reading %s\n", src_file); |
Marshall Dawson | 8e0dca0 | 2019-02-27 18:40:49 -0700 | [diff] [blame] | 646 | return -4; |
| 647 | } |
| 648 | |
| 649 | return bytes; |
| 650 | } |
| 651 | |
Kangheui Won | 3c164e1 | 2021-12-03 20:25:05 +1100 | [diff] [blame] | 652 | static ssize_t read_from_file_to_buf(int fd, void *buf, size_t buf_size) |
| 653 | { |
| 654 | ssize_t bytes; |
| 655 | size_t total_bytes = 0; |
| 656 | |
| 657 | do { |
| 658 | bytes = read(fd, buf + total_bytes, buf_size - total_bytes); |
| 659 | if (bytes == 0) { |
| 660 | fprintf(stderr, "Reached EOF probably\n"); |
| 661 | break; |
| 662 | } |
| 663 | |
| 664 | if (bytes < 0 && errno == EAGAIN) |
| 665 | bytes = 0; |
| 666 | |
| 667 | if (bytes < 0) { |
| 668 | fprintf(stderr, "Read failure %s\n", strerror(errno)); |
| 669 | return bytes; |
| 670 | } |
| 671 | |
| 672 | total_bytes += bytes; |
| 673 | } while (total_bytes < buf_size); |
| 674 | |
| 675 | if (total_bytes != buf_size) { |
| 676 | fprintf(stderr, "Read data size(%zu) != buffer size(%zu)\n", |
| 677 | total_bytes, buf_size); |
| 678 | return -1; |
| 679 | } |
| 680 | return buf_size; |
| 681 | } |
| 682 | |
| 683 | static ssize_t write_from_buf_to_file(int fd, const void *buf, size_t buf_size) |
| 684 | { |
| 685 | ssize_t bytes; |
| 686 | size_t total_bytes = 0; |
| 687 | |
| 688 | do { |
| 689 | bytes = write(fd, buf + total_bytes, buf_size - total_bytes); |
| 690 | if (bytes < 0 && errno == EAGAIN) |
| 691 | bytes = 0; |
| 692 | |
| 693 | if (bytes < 0) { |
| 694 | fprintf(stderr, "Write failure %s\n", strerror(errno)); |
| 695 | lseek(fd, SEEK_CUR, -total_bytes); |
| 696 | return bytes; |
| 697 | } |
| 698 | |
| 699 | total_bytes += bytes; |
| 700 | } while (total_bytes < buf_size); |
| 701 | |
| 702 | if (total_bytes != buf_size) { |
| 703 | fprintf(stderr, "Wrote more data(%zu) than buffer size(%zu)\n", |
| 704 | total_bytes, buf_size); |
| 705 | lseek(fd, SEEK_CUR, -total_bytes); |
| 706 | return -1; |
| 707 | } |
| 708 | |
| 709 | return buf_size; |
| 710 | } |
| 711 | |
Zheng Bao | eb0404e | 2021-10-14 15:09:09 +0800 | [diff] [blame] | 712 | static uint32_t get_psp_id(enum platform soc_id) |
| 713 | { |
| 714 | uint32_t psp_id; |
| 715 | switch (soc_id) { |
| 716 | case PLATFORM_RAVEN: |
| 717 | case PLATFORM_PICASSO: |
| 718 | psp_id = 0xBC0A0000; |
| 719 | break; |
| 720 | case PLATFORM_RENOIR: |
| 721 | case PLATFORM_LUCIENNE: |
| 722 | psp_id = 0xBC0C0000; |
| 723 | break; |
| 724 | case PLATFORM_CEZANNE: |
| 725 | psp_id = 0xBC0C0140; |
| 726 | break; |
| 727 | case PLATFORM_MENDOCINO: |
| 728 | psp_id = 0xBC0D0900; |
| 729 | break; |
| 730 | case PLATFORM_STONEYRIDGE: |
| 731 | psp_id = 0x10220B00; |
| 732 | break; |
Zheng Bao | de6f198 | 2022-10-16 20:32:43 +0800 | [diff] [blame] | 733 | case PLATFORM_GLINDA: |
| 734 | psp_id = 0xBC0E0200; |
| 735 | break; |
| 736 | case PLATFORM_PHOENIX: |
| 737 | psp_id = 0xBC0D0400; |
| 738 | break; |
Zheng Bao | 3d7623f | 2022-08-17 11:52:30 +0800 | [diff] [blame] | 739 | case PLATFORM_CARRIZO: |
Zheng Bao | eb0404e | 2021-10-14 15:09:09 +0800 | [diff] [blame] | 740 | default: |
| 741 | psp_id = 0; |
| 742 | break; |
| 743 | } |
| 744 | return psp_id; |
| 745 | } |
| 746 | |
Kangheui Won | 3c164e1 | 2021-12-03 20:25:05 +1100 | [diff] [blame] | 747 | static uint16_t get_psp_fw_type(enum platform soc_id, struct amd_fw_header *header) |
| 748 | { |
| 749 | switch (soc_id) { |
| 750 | case PLATFORM_MENDOCINO: |
Zheng Bao | 4044e85 | 2023-02-02 09:26:20 +0800 | [diff] [blame] | 751 | case PLATFORM_PHOENIX: |
| 752 | case PLATFORM_GLINDA: |
Kangheui Won | 3c164e1 | 2021-12-03 20:25:05 +1100 | [diff] [blame] | 753 | /* Fallback to fw_type if fw_id is not populated, which serves the same |
| 754 | purpose on older SoCs. */ |
| 755 | return header->fw_id ? header->fw_id : header->fw_type; |
| 756 | default: |
| 757 | return header->fw_type; |
| 758 | } |
| 759 | } |
| 760 | |
Kangheui Won | 5b84dfd | 2021-12-21 15:45:06 +1100 | [diff] [blame] | 761 | static int add_single_sha(amd_fw_entry_hash *entry, void *buf, enum platform soc_id) |
| 762 | { |
| 763 | uint8_t hash[SHA384_DIGEST_LENGTH]; |
| 764 | struct amd_fw_header *header = (struct amd_fw_header *)buf; |
| 765 | /* Include only signed part for hash calculation. */ |
| 766 | size_t len = header->fw_size_signed + sizeof(struct amd_fw_header); |
| 767 | uint8_t *body = (uint8_t *)buf; |
| 768 | |
| 769 | if (len > header->size_total) |
| 770 | return -1; |
| 771 | |
| 772 | if (header->sig_id == SIG_ID_RSA4096) { |
| 773 | SHA384(body, len, hash); |
| 774 | entry->sha_len = SHA384_DIGEST_LENGTH; |
| 775 | } else if (header->sig_id == SIG_ID_RSA2048) { |
| 776 | SHA256(body, len, hash); |
| 777 | entry->sha_len = SHA256_DIGEST_LENGTH; |
| 778 | } else { |
| 779 | fprintf(stderr, "%s: Unknown signature id: 0x%08x\n", |
| 780 | __func__, header->sig_id); |
| 781 | return -1; |
| 782 | } |
| 783 | |
| 784 | memcpy(entry->sha, hash, entry->sha_len); |
| 785 | entry->fw_id = get_psp_fw_type(soc_id, header); |
| 786 | entry->subtype = header->fw_subtype; |
| 787 | |
| 788 | return 0; |
| 789 | } |
| 790 | |
| 791 | static int get_num_binaries(void *buf, size_t buf_size) |
| 792 | { |
| 793 | struct amd_fw_header *header = (struct amd_fw_header *)buf; |
| 794 | size_t total_len = 0; |
| 795 | int num_binaries = 0; |
| 796 | |
| 797 | while (total_len < buf_size) { |
| 798 | num_binaries++; |
| 799 | total_len += header->size_total; |
| 800 | header = (struct amd_fw_header *)(buf + total_len); |
| 801 | } |
| 802 | |
| 803 | if (total_len != buf_size) { |
| 804 | fprintf(stderr, "Malformed binary\n"); |
| 805 | return -1; |
| 806 | } |
| 807 | return num_binaries; |
| 808 | } |
| 809 | |
| 810 | static int add_sha(amd_fw_entry *entry, void *buf, size_t buf_size, enum platform soc_id) |
| 811 | { |
| 812 | struct amd_fw_header *header = (struct amd_fw_header *)buf; |
| 813 | /* Include only signed part for hash calculation. */ |
| 814 | size_t total_len = 0; |
| 815 | int num_binaries = get_num_binaries(buf, buf_size); |
| 816 | |
| 817 | if (num_binaries <= 0) |
| 818 | return num_binaries; |
| 819 | |
| 820 | entry->hash_entries = malloc(num_binaries * sizeof(amd_fw_entry_hash)); |
| 821 | if (!entry->hash_entries) { |
| 822 | fprintf(stderr, "Error allocating memory to add FW hash\n"); |
| 823 | return -1; |
| 824 | } |
| 825 | entry->num_hash_entries = num_binaries; |
| 826 | |
| 827 | /* Iterate through each binary */ |
| 828 | for (int i = 0; i < num_binaries; i++) { |
| 829 | if (add_single_sha(&entry->hash_entries[i], buf + total_len, soc_id)) { |
| 830 | free(entry->hash_entries); |
| 831 | return -1; |
| 832 | } |
| 833 | total_len += header->size_total; |
| 834 | header = (struct amd_fw_header *)(buf + total_len); |
| 835 | } |
| 836 | |
| 837 | return 0; |
| 838 | } |
| 839 | |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 840 | static void integrate_firmwares(context *ctx, |
Marshall Dawson | 239286c | 2019-02-23 16:42:46 -0700 | [diff] [blame] | 841 | embedded_firmware *romsig, |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 842 | amd_fw_entry *fw_table) |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 843 | { |
Richard Spiegel | 137484d | 2018-01-17 10:23:19 -0700 | [diff] [blame] | 844 | ssize_t bytes; |
Zheng Bao | 6d402ac | 2020-10-01 16:16:30 +0800 | [diff] [blame] | 845 | uint32_t i; |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 846 | |
Elyes Haouas | 7d67a19 | 2022-10-14 09:58:29 +0200 | [diff] [blame] | 847 | ctx->current = ALIGN_UP(ctx->current, BLOB_ALIGNMENT); |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 848 | |
Martin Roth | cd15bc8 | 2016-11-08 11:34:02 -0700 | [diff] [blame] | 849 | for (i = 0; fw_table[i].type != AMD_FW_INVALID; i++) { |
zbao | c3a08a9 | 2016-03-02 14:47:27 +0800 | [diff] [blame] | 850 | if (fw_table[i].filename != NULL) { |
zbao | c3a08a9 | 2016-03-02 14:47:27 +0800 | [diff] [blame] | 851 | switch (fw_table[i].type) { |
| 852 | case AMD_FW_IMC: |
Elyes Haouas | 7d67a19 | 2022-10-14 09:58:29 +0200 | [diff] [blame] | 853 | ctx->current = ALIGN_UP(ctx->current, 0x10000U); |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 854 | romsig->imc_entry = RUN_CURRENT(*ctx); |
zbao | c3a08a9 | 2016-03-02 14:47:27 +0800 | [diff] [blame] | 855 | break; |
| 856 | case AMD_FW_GEC: |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 857 | romsig->gec_entry = RUN_CURRENT(*ctx); |
zbao | c3a08a9 | 2016-03-02 14:47:27 +0800 | [diff] [blame] | 858 | break; |
| 859 | case AMD_FW_XHCI: |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 860 | romsig->xhci_entry = RUN_CURRENT(*ctx); |
zbao | c3a08a9 | 2016-03-02 14:47:27 +0800 | [diff] [blame] | 861 | break; |
| 862 | default: |
| 863 | /* Error */ |
| 864 | break; |
| 865 | } |
| 866 | |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 867 | bytes = copy_blob(BUFF_CURRENT(*ctx), |
| 868 | fw_table[i].filename, BUFF_ROOM(*ctx)); |
Marshall Dawson | 02bd773 | 2019-03-13 14:43:17 -0600 | [diff] [blame] | 869 | if (bytes < 0) { |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 870 | free(ctx->rom); |
Martin Roth | 60f1551 | 2016-11-08 09:55:01 -0700 | [diff] [blame] | 871 | exit(1); |
| 872 | } |
| 873 | |
Elyes Haouas | 7d67a19 | 2022-10-14 09:58:29 +0200 | [diff] [blame] | 874 | ctx->current = ALIGN_UP(ctx->current + bytes, |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 875 | BLOB_ALIGNMENT); |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 876 | } |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 877 | } |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 878 | } |
| 879 | |
Zheng Bao | 9e90807 | 2020-10-28 11:39:13 +0800 | [diff] [blame] | 880 | /* For debugging */ |
| 881 | static void dump_psp_firmwares(amd_fw_entry *fw_table) |
| 882 | { |
| 883 | amd_fw_entry *index; |
| 884 | |
| 885 | printf("PSP firmware components:"); |
| 886 | for (index = fw_table; index->type != AMD_FW_INVALID; index++) { |
| 887 | if (index->filename) |
Zheng Bao | 826f1c4 | 2021-05-25 16:26:55 +0800 | [diff] [blame] | 888 | printf(" %2x: %s\n", index->type, index->filename); |
Zheng Bao | 9e90807 | 2020-10-28 11:39:13 +0800 | [diff] [blame] | 889 | } |
| 890 | } |
| 891 | |
| 892 | static void dump_bdt_firmwares(amd_bios_entry *fw_table) |
| 893 | { |
| 894 | amd_bios_entry *index; |
| 895 | |
| 896 | printf("BIOS Directory Table (BDT) components:"); |
| 897 | for (index = fw_table; index->type != AMD_BIOS_INVALID; index++) { |
| 898 | if (index->filename) |
Zheng Bao | 826f1c4 | 2021-05-25 16:26:55 +0800 | [diff] [blame] | 899 | printf(" %2x: %s\n", index->type, index->filename); |
Zheng Bao | 9e90807 | 2020-10-28 11:39:13 +0800 | [diff] [blame] | 900 | } |
| 901 | } |
| 902 | |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 903 | static void free_psp_firmware_filenames(amd_fw_entry *fw_table) |
| 904 | { |
| 905 | amd_fw_entry *index; |
| 906 | |
| 907 | for (index = fw_table; index->type != AMD_FW_INVALID; index++) { |
| 908 | if (index->filename && |
| 909 | index->type != AMD_FW_VERSTAGE_SIG && |
| 910 | index->type != AMD_FW_PSP_VERSTAGE && |
Zheng Bao | 6c5ec8e | 2022-02-11 11:51:26 +0800 | [diff] [blame] | 911 | index->type != AMD_FW_SPL && |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 912 | index->type != AMD_FW_PSP_WHITELIST) { |
| 913 | free(index->filename); |
| 914 | } |
| 915 | } |
| 916 | } |
| 917 | |
| 918 | static void free_bdt_firmware_filenames(amd_bios_entry *fw_table) |
| 919 | { |
| 920 | amd_bios_entry *index; |
| 921 | |
| 922 | for (index = fw_table; index->type != AMD_BIOS_INVALID; index++) { |
| 923 | if (index->filename && |
| 924 | index->type != AMD_BIOS_APCB && |
| 925 | index->type != AMD_BIOS_BIN && |
Arthur Heymans | 1cffc55 | 2022-10-19 20:08:35 +0200 | [diff] [blame] | 926 | index->type != AMD_BIOS_APCB_BK && |
| 927 | index->type != AMD_BIOS_UCODE) |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 928 | free(index->filename); |
| 929 | } |
| 930 | } |
| 931 | |
Kangheui Won | 5b84dfd | 2021-12-21 15:45:06 +1100 | [diff] [blame] | 932 | static void write_or_fail(int fd, void *ptr, size_t size) |
| 933 | { |
| 934 | ssize_t written; |
| 935 | |
| 936 | written = write_from_buf_to_file(fd, ptr, size); |
| 937 | if (written < 0 || (size_t)written != size) { |
| 938 | fprintf(stderr, "%s: Error writing %zu bytes - written %zd bytes\n", |
| 939 | __func__, size, written); |
| 940 | exit(-1); |
| 941 | } |
| 942 | } |
| 943 | |
| 944 | static void write_one_psp_firmware_hash_entry(int fd, amd_fw_entry_hash *entry) |
| 945 | { |
| 946 | uint16_t type = entry->fw_id; |
| 947 | uint16_t subtype = entry->subtype; |
| 948 | |
| 949 | write_or_fail(fd, &type, sizeof(type)); |
| 950 | write_or_fail(fd, &subtype, sizeof(subtype)); |
| 951 | write_or_fail(fd, entry->sha, entry->sha_len); |
| 952 | } |
| 953 | |
| 954 | static void write_psp_firmware_hash(const char *filename, |
| 955 | amd_fw_entry *fw_table) |
| 956 | { |
| 957 | struct psp_fw_hash_table hash_header = {0}; |
| 958 | int fd = open(filename, O_RDWR | O_CREAT | O_TRUNC, 0666); |
| 959 | |
| 960 | if (fd < 0) { |
| 961 | fprintf(stderr, "Error opening file: %s: %s\n", |
| 962 | filename, strerror(errno)); |
| 963 | exit(-1); |
| 964 | } |
| 965 | |
| 966 | hash_header.version = HASH_HDR_V1; |
| 967 | for (unsigned int i = 0; fw_table[i].type != AMD_FW_INVALID; i++) { |
| 968 | for (unsigned int j = 0; j < fw_table[i].num_hash_entries; j++) { |
| 969 | if (fw_table[i].hash_entries[j].sha_len == SHA256_DIGEST_LENGTH) { |
| 970 | hash_header.no_of_entries_256++; |
| 971 | } else if (fw_table[i].hash_entries[j].sha_len == |
| 972 | SHA384_DIGEST_LENGTH) { |
| 973 | hash_header.no_of_entries_384++; |
| 974 | } else if (fw_table[i].hash_entries[j].sha_len) { |
| 975 | fprintf(stderr, "%s: Error invalid sha_len %d\n", |
| 976 | __func__, fw_table[i].hash_entries[j].sha_len); |
| 977 | exit(-1); |
| 978 | } |
| 979 | } |
| 980 | } |
| 981 | |
| 982 | write_or_fail(fd, &hash_header, sizeof(hash_header)); |
| 983 | |
| 984 | /* Add all the SHA256 hash entries first followed by SHA384 entries. PSP verstage |
| 985 | processes the table in that order. Mixing and matching SHA256 and SHA384 entries |
| 986 | will cause the hash verification failure at run-time. */ |
| 987 | for (unsigned int i = 0; fw_table[i].type != AMD_FW_INVALID; i++) { |
| 988 | for (unsigned int j = 0; j < fw_table[i].num_hash_entries; j++) { |
| 989 | if (fw_table[i].hash_entries[j].sha_len == SHA256_DIGEST_LENGTH) |
| 990 | write_one_psp_firmware_hash_entry(fd, |
| 991 | &fw_table[i].hash_entries[j]); |
| 992 | } |
| 993 | } |
| 994 | |
| 995 | for (unsigned int i = 0; fw_table[i].type != AMD_FW_INVALID; i++) { |
| 996 | for (unsigned int j = 0; j < fw_table[i].num_hash_entries; j++) { |
| 997 | if (fw_table[i].hash_entries[j].sha_len == SHA384_DIGEST_LENGTH) |
| 998 | write_one_psp_firmware_hash_entry(fd, |
| 999 | &fw_table[i].hash_entries[j]); |
| 1000 | } |
| 1001 | } |
| 1002 | |
| 1003 | close(fd); |
| 1004 | for (unsigned int i = 0; fw_table[i].type != AMD_FW_INVALID; i++) { |
| 1005 | if (!fw_table[i].num_hash_entries || !fw_table[i].hash_entries) |
| 1006 | continue; |
| 1007 | |
| 1008 | free(fw_table[i].hash_entries); |
| 1009 | fw_table[i].hash_entries = NULL; |
| 1010 | fw_table[i].num_hash_entries = 0; |
| 1011 | } |
| 1012 | } |
| 1013 | |
Kangheui Won | 3c164e1 | 2021-12-03 20:25:05 +1100 | [diff] [blame] | 1014 | /** |
| 1015 | * process_signed_psp_firmwares() - Process the signed PSP binaries to keep them separate |
| 1016 | * @signed_rom: Output file path grouping all the signed PSP binaries. |
| 1017 | * @fw_table: Table of all the PSP firmware entries/binaries to be processed. |
| 1018 | * @signed_start_addr: Offset of the FMAP section, within the flash device, to hold |
| 1019 | * the signed PSP binaries. |
| 1020 | * @soc_id: SoC ID of the PSP binaries. |
| 1021 | */ |
| 1022 | static void process_signed_psp_firmwares(const char *signed_rom, |
| 1023 | amd_fw_entry *fw_table, |
| 1024 | uint64_t signed_start_addr, |
| 1025 | enum platform soc_id) |
| 1026 | { |
| 1027 | unsigned int i; |
| 1028 | int fd; |
| 1029 | int signed_rom_fd; |
| 1030 | ssize_t bytes, align_bytes; |
| 1031 | uint8_t *buf; |
Kangheui Won | 5b84dfd | 2021-12-21 15:45:06 +1100 | [diff] [blame] | 1032 | char *signed_rom_hash; |
| 1033 | size_t signed_rom_hash_strlen; |
Kangheui Won | 3c164e1 | 2021-12-03 20:25:05 +1100 | [diff] [blame] | 1034 | struct amd_fw_header header; |
| 1035 | struct stat fd_stat; |
| 1036 | /* Every blob in amdfw*.rom has to start at address aligned to 0x100. Prepare an |
| 1037 | alignment data with 0xff to pad the blobs and meet the alignment requirement. */ |
| 1038 | uint8_t align_data[BLOB_ALIGNMENT - 1]; |
| 1039 | |
| 1040 | memset(align_data, 0xff, sizeof(align_data)); |
| 1041 | signed_rom_fd = open(signed_rom, O_RDWR | O_CREAT | O_TRUNC, |
| 1042 | S_IRUSR | S_IWUSR | S_IRGRP | S_IWGRP | S_IROTH | S_IWOTH); |
| 1043 | if (signed_rom_fd < 0) { |
| 1044 | fprintf(stderr, "Error opening file: %s: %s\n", |
| 1045 | signed_rom, strerror(errno)); |
| 1046 | return; |
| 1047 | } |
| 1048 | |
| 1049 | for (i = 0; fw_table[i].type != AMD_FW_INVALID; i++) { |
Kangheui Won | 5b84dfd | 2021-12-21 15:45:06 +1100 | [diff] [blame] | 1050 | fw_table[i].num_hash_entries = 0; |
| 1051 | fw_table[i].hash_entries = NULL; |
| 1052 | |
Kangheui Won | 3c164e1 | 2021-12-03 20:25:05 +1100 | [diff] [blame] | 1053 | if (!(fw_table[i].filename) || fw_table[i].skip_hashing) |
| 1054 | continue; |
| 1055 | |
| 1056 | memset(&header, 0, sizeof(header)); |
| 1057 | |
| 1058 | fd = open(fw_table[i].filename, O_RDONLY); |
| 1059 | if (fd < 0) { |
| 1060 | /* Keep the file along with set of unsigned PSP binaries & continue. */ |
| 1061 | fprintf(stderr, "Error opening file: %s: %s\n", |
| 1062 | fw_table[i].filename, strerror(errno)); |
| 1063 | continue; |
| 1064 | } |
| 1065 | |
| 1066 | if (fstat(fd, &fd_stat)) { |
| 1067 | /* Keep the file along with set of unsigned PSP binaries & continue. */ |
| 1068 | fprintf(stderr, "fstat error: %s\n", strerror(errno)); |
| 1069 | close(fd); |
| 1070 | continue; |
| 1071 | } |
| 1072 | |
| 1073 | bytes = read_from_file_to_buf(fd, &header, sizeof(struct amd_fw_header)); |
| 1074 | if (bytes != (ssize_t)sizeof(struct amd_fw_header)) { |
| 1075 | /* Keep the file along with set of unsigned PSP binaries & continue. */ |
| 1076 | fprintf(stderr, "%s: Error reading header from %s\n", |
| 1077 | __func__, fw_table[i].filename); |
| 1078 | close(fd); |
| 1079 | continue; |
| 1080 | } |
| 1081 | |
| 1082 | /* If firmware header looks like invalid, assume it's not signed */ |
| 1083 | if (!header.fw_type && !header.fw_id) { |
| 1084 | fprintf(stderr, "%s: Invalid FWID for %s\n", |
| 1085 | __func__, fw_table[i].filename); |
| 1086 | close(fd); |
| 1087 | continue; |
| 1088 | } |
| 1089 | |
Kangheui Won | 3c164e1 | 2021-12-03 20:25:05 +1100 | [diff] [blame] | 1090 | |
| 1091 | /* PSP binary is not signed and should not be part of signed PSP binaries |
| 1092 | set. */ |
| 1093 | if (header.sig_opt != 1) { |
| 1094 | close(fd); |
| 1095 | continue; |
| 1096 | } |
| 1097 | |
| 1098 | buf = malloc(fd_stat.st_size); |
| 1099 | if (!buf) { |
| 1100 | /* Keep the file along with set of unsigned PSP binaries & continue. */ |
| 1101 | fprintf(stderr, "%s: failed to allocate memory with size %lld\n", |
| 1102 | __func__, (long long)fd_stat.st_size); |
| 1103 | close(fd); |
| 1104 | continue; |
| 1105 | } |
| 1106 | |
| 1107 | lseek(fd, SEEK_SET, 0); |
| 1108 | bytes = read_from_file_to_buf(fd, buf, fd_stat.st_size); |
| 1109 | if (bytes != fd_stat.st_size) { |
| 1110 | /* Keep the file along with set of unsigned PSP binaries & continue. */ |
| 1111 | fprintf(stderr, "%s: failed to read %s\n", |
| 1112 | __func__, fw_table[i].filename); |
| 1113 | free(buf); |
| 1114 | close(fd); |
| 1115 | continue; |
| 1116 | } |
| 1117 | |
| 1118 | bytes = write_from_buf_to_file(signed_rom_fd, buf, fd_stat.st_size); |
| 1119 | if (bytes != fd_stat.st_size) { |
| 1120 | /* Keep the file along with set of unsigned PSP binaries & continue. */ |
| 1121 | fprintf(stderr, "%s: failed to write %s\n", |
| 1122 | __func__, fw_table[i].filename); |
| 1123 | free(buf); |
| 1124 | close(fd); |
| 1125 | continue; |
| 1126 | } |
| 1127 | |
| 1128 | /* Write Blob alignment bytes */ |
| 1129 | align_bytes = 0; |
| 1130 | if (fd_stat.st_size & (BLOB_ALIGNMENT - 1)) { |
| 1131 | align_bytes = BLOB_ALIGNMENT - |
| 1132 | (fd_stat.st_size & (BLOB_ALIGNMENT - 1)); |
| 1133 | bytes = write_from_buf_to_file(signed_rom_fd, align_data, align_bytes); |
| 1134 | if (bytes != align_bytes) { |
| 1135 | fprintf(stderr, "%s: failed to write alignment data for %s\n", |
| 1136 | __func__, fw_table[i].filename); |
| 1137 | lseek(signed_rom_fd, SEEK_CUR, -fd_stat.st_size); |
| 1138 | free(buf); |
| 1139 | close(fd); |
| 1140 | continue; |
| 1141 | } |
| 1142 | } |
| 1143 | |
Kangheui Won | 5b84dfd | 2021-12-21 15:45:06 +1100 | [diff] [blame] | 1144 | if (add_sha(&fw_table[i], buf, fd_stat.st_size, soc_id)) |
| 1145 | exit(-1); |
| 1146 | |
Kangheui Won | 3c164e1 | 2021-12-03 20:25:05 +1100 | [diff] [blame] | 1147 | /* File is successfully processed and is part of signed PSP binaries set. */ |
| 1148 | fw_table[i].fw_id = get_psp_fw_type(soc_id, &header); |
| 1149 | fw_table[i].addr_signed = signed_start_addr; |
| 1150 | fw_table[i].file_size = (uint32_t)fd_stat.st_size; |
| 1151 | |
| 1152 | signed_start_addr += fd_stat.st_size + align_bytes; |
| 1153 | |
| 1154 | free(buf); |
| 1155 | close(fd); |
| 1156 | } |
| 1157 | |
| 1158 | close(signed_rom_fd); |
Kangheui Won | 5b84dfd | 2021-12-21 15:45:06 +1100 | [diff] [blame] | 1159 | |
| 1160 | /* signed_rom file name + ".hash" + '\0' */ |
| 1161 | signed_rom_hash_strlen = strlen(signed_rom) + strlen(HASH_FILE_SUFFIX) + 1; |
| 1162 | signed_rom_hash = malloc(signed_rom_hash_strlen); |
| 1163 | if (!signed_rom_hash) { |
| 1164 | fprintf(stderr, "malloc(%lu) failed\n", signed_rom_hash_strlen); |
| 1165 | exit(-1); |
| 1166 | } |
| 1167 | strcpy(signed_rom_hash, signed_rom); |
| 1168 | strcat(signed_rom_hash, HASH_FILE_SUFFIX); |
| 1169 | write_psp_firmware_hash(signed_rom_hash, fw_table); |
| 1170 | free(signed_rom_hash); |
Kangheui Won | 3c164e1 | 2021-12-03 20:25:05 +1100 | [diff] [blame] | 1171 | } |
| 1172 | |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 1173 | static void integrate_psp_ab(context *ctx, psp_directory_table *pspdir, |
Zheng Bao | fdd47ef | 2021-09-17 13:30:08 +0800 | [diff] [blame] | 1174 | psp_directory_table *pspdir2, ish_directory_table *ish, |
| 1175 | amd_fw_type ab, enum platform soc_id) |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 1176 | { |
| 1177 | uint32_t count; |
| 1178 | uint32_t current_table_save; |
| 1179 | |
| 1180 | current_table_save = ctx->current_table; |
| 1181 | ctx->current_table = (char *)pspdir - ctx->rom; |
| 1182 | count = pspdir->header.num_entries; |
| 1183 | assert_fw_entry(count, MAX_PSP_ENTRIES, ctx); |
| 1184 | pspdir->entries[count].type = (uint8_t)ab; |
| 1185 | pspdir->entries[count].subprog = 0; |
| 1186 | pspdir->entries[count].rsvd = 0; |
Zheng Bao | fdd47ef | 2021-09-17 13:30:08 +0800 | [diff] [blame] | 1187 | if (ish != NULL) { |
Robert Zieba | 29bc79f | 2022-03-14 15:59:12 -0600 | [diff] [blame] | 1188 | ish->pl2_location = BUFF_TO_RUN_MODE(*ctx, pspdir2, AMD_ADDR_REL_BIOS); |
Zheng Bao | fdd47ef | 2021-09-17 13:30:08 +0800 | [diff] [blame] | 1189 | ish->boot_priority = ab == AMD_FW_RECOVERYAB_A ? 0xFFFFFFFF : 1; |
| 1190 | ish->update_retry_count = 2; |
| 1191 | ish->glitch_retry_count = 0; |
| 1192 | ish->psp_id = get_psp_id(soc_id); |
| 1193 | ish->checksum = fletcher32(&ish->boot_priority, |
| 1194 | sizeof(ish_directory_table) - sizeof(uint32_t)); |
| 1195 | pspdir->entries[count].addr = |
Robert Zieba | 29bc79f | 2022-03-14 15:59:12 -0600 | [diff] [blame] | 1196 | BUFF_TO_RUN_MODE(*ctx, ish, AMD_ADDR_REL_BIOS); |
Zheng Bao | fdd47ef | 2021-09-17 13:30:08 +0800 | [diff] [blame] | 1197 | pspdir->entries[count].address_mode = |
Robert Zieba | 29bc79f | 2022-03-14 15:59:12 -0600 | [diff] [blame] | 1198 | SET_ADDR_MODE(pspdir, AMD_ADDR_REL_BIOS); |
Zheng Bao | fdd47ef | 2021-09-17 13:30:08 +0800 | [diff] [blame] | 1199 | pspdir->entries[count].size = TABLE_ALIGNMENT; |
| 1200 | } else { |
| 1201 | pspdir->entries[count].addr = |
Robert Zieba | 29bc79f | 2022-03-14 15:59:12 -0600 | [diff] [blame] | 1202 | BUFF_TO_RUN_MODE(*ctx, pspdir2, AMD_ADDR_REL_BIOS); |
Zheng Bao | fdd47ef | 2021-09-17 13:30:08 +0800 | [diff] [blame] | 1203 | pspdir->entries[count].address_mode = |
Robert Zieba | 29bc79f | 2022-03-14 15:59:12 -0600 | [diff] [blame] | 1204 | SET_ADDR_MODE(pspdir, AMD_ADDR_REL_BIOS); |
Zheng Bao | fdd47ef | 2021-09-17 13:30:08 +0800 | [diff] [blame] | 1205 | pspdir->entries[count].size = pspdir2->header.num_entries * |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 1206 | sizeof(psp_directory_entry) + |
| 1207 | sizeof(psp_directory_header); |
Zheng Bao | fdd47ef | 2021-09-17 13:30:08 +0800 | [diff] [blame] | 1208 | } |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 1209 | |
| 1210 | count++; |
| 1211 | pspdir->header.num_entries = count; |
| 1212 | ctx->current_table = current_table_save; |
| 1213 | } |
| 1214 | |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 1215 | static void integrate_psp_firmwares(context *ctx, |
Marshall Dawson | 239286c | 2019-02-23 16:42:46 -0700 | [diff] [blame] | 1216 | psp_directory_table *pspdir, |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 1217 | psp_directory_table *pspdir2, |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 1218 | psp_directory_table *pspdir2_b, |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 1219 | amd_fw_entry *fw_table, |
Zheng Bao | 2079589 | 2021-08-20 14:58:22 +0800 | [diff] [blame] | 1220 | uint32_t cookie, |
| 1221 | amd_cb_config *cb_config) |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1222 | { |
Richard Spiegel | 137484d | 2018-01-17 10:23:19 -0700 | [diff] [blame] | 1223 | ssize_t bytes; |
Marshall Dawson | c38c0c9 | 2019-02-23 16:41:35 -0700 | [diff] [blame] | 1224 | unsigned int i, count; |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 1225 | int level; |
Ritul Guru | a2cb340 | 2022-08-29 00:51:08 +0530 | [diff] [blame] | 1226 | uint32_t size; |
| 1227 | uint64_t addr; |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 1228 | uint32_t current_table_save; |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 1229 | bool recovery_ab = cb_config->recovery_ab; |
Zheng Bao | fdd47ef | 2021-09-17 13:30:08 +0800 | [diff] [blame] | 1230 | ish_directory_table *ish_a_dir = NULL, *ish_b_dir = NULL; |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 1231 | |
| 1232 | /* This function can create a primary table, a secondary table, or a |
| 1233 | * flattened table which contains all applicable types. These if-else |
| 1234 | * statements infer what the caller intended. If a 2nd-level cookie |
| 1235 | * is passed, clearly a 2nd-level table is intended. However, a |
| 1236 | * 1st-level cookie may indicate level 1 or flattened. If the caller |
| 1237 | * passes a pointer to a 2nd-level table, then assume not flat. |
| 1238 | */ |
Zheng Bao | ba3af5e | 2021-11-04 18:56:47 +0800 | [diff] [blame] | 1239 | if (!cb_config->multi_level) |
Zheng Bao | 2079589 | 2021-08-20 14:58:22 +0800 | [diff] [blame] | 1240 | level = PSP_BOTH; |
| 1241 | else if (cookie == PSPL2_COOKIE) |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 1242 | level = PSP_LVL2; |
| 1243 | else if (pspdir2) |
| 1244 | level = PSP_LVL1; |
| 1245 | else |
| 1246 | level = PSP_BOTH; |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 1247 | |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 1248 | if (recovery_ab) { |
| 1249 | if (cookie == PSPL2_COOKIE) |
| 1250 | level = PSP_LVL2_AB; |
| 1251 | else if (pspdir2) |
| 1252 | level = PSP_LVL1_AB; |
| 1253 | else |
| 1254 | level = PSP_BOTH_AB; |
| 1255 | } |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 1256 | current_table_save = ctx->current_table; |
| 1257 | ctx->current_table = (char *)pspdir - ctx->rom; |
Elyes Haouas | 7d67a19 | 2022-10-14 09:58:29 +0200 | [diff] [blame] | 1258 | ctx->current = ALIGN_UP(ctx->current, TABLE_ALIGNMENT); |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1259 | |
Marshall Dawson | c38c0c9 | 2019-02-23 16:41:35 -0700 | [diff] [blame] | 1260 | for (i = 0, count = 0; fw_table[i].type != AMD_FW_INVALID; i++) { |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 1261 | if (!(fw_table[i].level & level)) |
| 1262 | continue; |
| 1263 | |
Zheng Bao | 5164e4b | 2021-10-30 12:09:07 +0800 | [diff] [blame] | 1264 | assert_fw_entry(count, MAX_PSP_ENTRIES, ctx); |
| 1265 | |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1266 | if (fw_table[i].type == AMD_TOKEN_UNLOCK) { |
| 1267 | if (!fw_table[i].other) |
| 1268 | continue; |
Elyes Haouas | 7d67a19 | 2022-10-14 09:58:29 +0200 | [diff] [blame] | 1269 | ctx->current = ALIGN_UP(ctx->current, ERASE_ALIGNMENT); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1270 | pspdir->entries[count].type = fw_table[i].type; |
| 1271 | pspdir->entries[count].size = 4096; /* TODO: doc? */ |
| 1272 | pspdir->entries[count].addr = RUN_CURRENT(*ctx); |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 1273 | pspdir->entries[count].address_mode = SET_ADDR_MODE_BY_TABLE(pspdir); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1274 | pspdir->entries[count].subprog = fw_table[i].subprog; |
| 1275 | pspdir->entries[count].rsvd = 0; |
Elyes Haouas | 7d67a19 | 2022-10-14 09:58:29 +0200 | [diff] [blame] | 1276 | ctx->current = ALIGN_UP(ctx->current + 4096, 0x100U); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1277 | count++; |
| 1278 | } else if (fw_table[i].type == AMD_PSP_FUSE_CHAIN) { |
Marshall Dawson | 239286c | 2019-02-23 16:42:46 -0700 | [diff] [blame] | 1279 | pspdir->entries[count].type = fw_table[i].type; |
Marshall Dawson | dbae632 | 2019-03-04 10:31:03 -0700 | [diff] [blame] | 1280 | pspdir->entries[count].subprog = fw_table[i].subprog; |
| 1281 | pspdir->entries[count].rsvd = 0; |
Marshall Dawson | 239286c | 2019-02-23 16:42:46 -0700 | [diff] [blame] | 1282 | pspdir->entries[count].size = 0xFFFFFFFF; |
Marshall Dawson | ef79fcc | 2019-04-01 10:16:41 -0600 | [diff] [blame] | 1283 | pspdir->entries[count].addr = fw_table[i].other; |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 1284 | pspdir->entries[count].address_mode = 0; |
Marshall Dawson | c38c0c9 | 2019-02-23 16:41:35 -0700 | [diff] [blame] | 1285 | count++; |
Marshall Dawson | 7c1e142 | 2019-04-11 09:44:43 -0600 | [diff] [blame] | 1286 | } else if (fw_table[i].type == AMD_FW_PSP_NVRAM) { |
Ritul Guru | a2cb340 | 2022-08-29 00:51:08 +0530 | [diff] [blame] | 1287 | if (fw_table[i].filename == NULL) { |
| 1288 | if (fw_table[i].size == 0) |
| 1289 | continue; |
| 1290 | size = fw_table[i].size; |
| 1291 | addr = fw_table[i].dest; |
Elyes Haouas | 7d67a19 | 2022-10-14 09:58:29 +0200 | [diff] [blame] | 1292 | if (addr != ALIGN_UP(addr, ERASE_ALIGNMENT)) { |
Ritul Guru | a2cb340 | 2022-08-29 00:51:08 +0530 | [diff] [blame] | 1293 | fprintf(stderr, |
| 1294 | "Error: PSP NVRAM section not aligned with erase block size.\n\n"); |
| 1295 | exit(1); |
| 1296 | } |
| 1297 | } else { |
Elyes Haouas | 7d67a19 | 2022-10-14 09:58:29 +0200 | [diff] [blame] | 1298 | ctx->current = ALIGN_UP(ctx->current, ERASE_ALIGNMENT); |
Ritul Guru | a2cb340 | 2022-08-29 00:51:08 +0530 | [diff] [blame] | 1299 | bytes = copy_blob(BUFF_CURRENT(*ctx), |
| 1300 | fw_table[i].filename, BUFF_ROOM(*ctx)); |
| 1301 | if (bytes <= 0) { |
| 1302 | free(ctx->rom); |
| 1303 | exit(1); |
| 1304 | } |
| 1305 | |
Elyes Haouas | 7d67a19 | 2022-10-14 09:58:29 +0200 | [diff] [blame] | 1306 | size = ALIGN_UP(bytes, ERASE_ALIGNMENT); |
Ritul Guru | a2cb340 | 2022-08-29 00:51:08 +0530 | [diff] [blame] | 1307 | addr = RUN_CURRENT(*ctx); |
Elyes Haouas | 7d67a19 | 2022-10-14 09:58:29 +0200 | [diff] [blame] | 1308 | ctx->current = ALIGN_UP(ctx->current + bytes, |
Ritul Guru | a2cb340 | 2022-08-29 00:51:08 +0530 | [diff] [blame] | 1309 | BLOB_ERASE_ALIGNMENT); |
Marshall Dawson | 7c1e142 | 2019-04-11 09:44:43 -0600 | [diff] [blame] | 1310 | } |
| 1311 | |
| 1312 | pspdir->entries[count].type = fw_table[i].type; |
| 1313 | pspdir->entries[count].subprog = fw_table[i].subprog; |
| 1314 | pspdir->entries[count].rsvd = 0; |
Ritul Guru | a2cb340 | 2022-08-29 00:51:08 +0530 | [diff] [blame] | 1315 | pspdir->entries[count].size = size; |
| 1316 | pspdir->entries[count].addr = addr; |
| 1317 | |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 1318 | pspdir->entries[count].address_mode = |
Robert Zieba | 29bc79f | 2022-03-14 15:59:12 -0600 | [diff] [blame] | 1319 | SET_ADDR_MODE(pspdir, AMD_ADDR_REL_BIOS); |
Marshall Dawson | 7c1e142 | 2019-04-11 09:44:43 -0600 | [diff] [blame] | 1320 | |
Marshall Dawson | 7c1e142 | 2019-04-11 09:44:43 -0600 | [diff] [blame] | 1321 | count++; |
zbao | c3a08a9 | 2016-03-02 14:47:27 +0800 | [diff] [blame] | 1322 | } else if (fw_table[i].filename != NULL) { |
Kangheui Won | 3c164e1 | 2021-12-03 20:25:05 +1100 | [diff] [blame] | 1323 | if (fw_table[i].addr_signed) { |
| 1324 | pspdir->entries[count].addr = |
| 1325 | RUN_OFFSET(*ctx, fw_table[i].addr_signed); |
| 1326 | pspdir->entries[count].address_mode = |
| 1327 | SET_ADDR_MODE_BY_TABLE(pspdir); |
| 1328 | bytes = fw_table[i].file_size; |
| 1329 | } else { |
| 1330 | bytes = copy_blob(BUFF_CURRENT(*ctx), |
| 1331 | fw_table[i].filename, BUFF_ROOM(*ctx)); |
| 1332 | if (bytes < 0) { |
| 1333 | free(ctx->rom); |
| 1334 | exit(1); |
| 1335 | } |
| 1336 | pspdir->entries[count].addr = RUN_CURRENT(*ctx); |
| 1337 | pspdir->entries[count].address_mode = |
| 1338 | SET_ADDR_MODE_BY_TABLE(pspdir); |
Elyes Haouas | 7d67a19 | 2022-10-14 09:58:29 +0200 | [diff] [blame] | 1339 | ctx->current = ALIGN_UP(ctx->current + bytes, |
Kangheui Won | 3c164e1 | 2021-12-03 20:25:05 +1100 | [diff] [blame] | 1340 | BLOB_ALIGNMENT); |
Marshall Dawson | 8e0dca0 | 2019-02-27 18:40:49 -0700 | [diff] [blame] | 1341 | } |
| 1342 | |
Marshall Dawson | 239286c | 2019-02-23 16:42:46 -0700 | [diff] [blame] | 1343 | pspdir->entries[count].type = fw_table[i].type; |
Marshall Dawson | dbae632 | 2019-03-04 10:31:03 -0700 | [diff] [blame] | 1344 | pspdir->entries[count].subprog = fw_table[i].subprog; |
| 1345 | pspdir->entries[count].rsvd = 0; |
Marshall Dawson | 8e0dca0 | 2019-02-27 18:40:49 -0700 | [diff] [blame] | 1346 | pspdir->entries[count].size = (uint32_t)bytes; |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1347 | |
Marshall Dawson | c38c0c9 | 2019-02-23 16:41:35 -0700 | [diff] [blame] | 1348 | count++; |
zbao | c3a08a9 | 2016-03-02 14:47:27 +0800 | [diff] [blame] | 1349 | } else { |
| 1350 | /* This APU doesn't have this firmware. */ |
| 1351 | } |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1352 | } |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 1353 | |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 1354 | if (recovery_ab && (pspdir2 != NULL)) { |
Zheng Bao | fdd47ef | 2021-09-17 13:30:08 +0800 | [diff] [blame] | 1355 | if (cb_config->need_ish) { /* Need ISH */ |
| 1356 | ish_a_dir = new_ish_dir(ctx); |
| 1357 | if (pspdir2_b != NULL) |
| 1358 | ish_b_dir = new_ish_dir(ctx); |
| 1359 | } |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 1360 | pspdir->header.num_entries = count; |
Zheng Bao | fdd47ef | 2021-09-17 13:30:08 +0800 | [diff] [blame] | 1361 | integrate_psp_ab(ctx, pspdir, pspdir2, ish_a_dir, |
Zheng Bao | 4bf6f49 | 2023-01-25 22:37:29 +0800 | [diff] [blame] | 1362 | AMD_FW_RECOVERYAB_A, cb_config->soc_id); |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 1363 | if (pspdir2_b != NULL) |
Zheng Bao | fdd47ef | 2021-09-17 13:30:08 +0800 | [diff] [blame] | 1364 | integrate_psp_ab(ctx, pspdir, pspdir2_b, ish_b_dir, |
Zheng Bao | 4bf6f49 | 2023-01-25 22:37:29 +0800 | [diff] [blame] | 1365 | AMD_FW_RECOVERYAB_B, cb_config->soc_id); |
Karthikeyan Ramasubramanian | ad06bae | 2022-04-08 14:19:55 -0600 | [diff] [blame] | 1366 | else |
Karthikeyan Ramasubramanian | e5af14a | 2022-08-02 11:34:48 -0600 | [diff] [blame] | 1367 | integrate_psp_ab(ctx, pspdir, pspdir2, ish_a_dir, |
Zheng Bao | 4bf6f49 | 2023-01-25 22:37:29 +0800 | [diff] [blame] | 1368 | AMD_FW_RECOVERYAB_B, cb_config->soc_id); |
Karthikeyan Ramasubramanian | ad06bae | 2022-04-08 14:19:55 -0600 | [diff] [blame] | 1369 | |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 1370 | count = pspdir->header.num_entries; |
| 1371 | } else if (pspdir2 != NULL) { |
Zheng Bao | 5164e4b | 2021-10-30 12:09:07 +0800 | [diff] [blame] | 1372 | assert_fw_entry(count, MAX_PSP_ENTRIES, ctx); |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 1373 | pspdir->entries[count].type = AMD_FW_L2_PTR; |
| 1374 | pspdir->entries[count].subprog = 0; |
| 1375 | pspdir->entries[count].rsvd = 0; |
| 1376 | pspdir->entries[count].size = sizeof(pspdir2->header) |
| 1377 | + pspdir2->header.num_entries |
| 1378 | * sizeof(psp_directory_entry); |
| 1379 | |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 1380 | pspdir->entries[count].addr = |
Robert Zieba | 29bc79f | 2022-03-14 15:59:12 -0600 | [diff] [blame] | 1381 | BUFF_TO_RUN_MODE(*ctx, pspdir2, AMD_ADDR_REL_BIOS); |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 1382 | pspdir->entries[count].address_mode = |
Robert Zieba | 29bc79f | 2022-03-14 15:59:12 -0600 | [diff] [blame] | 1383 | SET_ADDR_MODE(pspdir, AMD_ADDR_REL_BIOS); |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 1384 | count++; |
| 1385 | } |
| 1386 | |
Zheng Bao | bf29a0d | 2020-12-03 23:00:48 +0800 | [diff] [blame] | 1387 | fill_dir_header(pspdir, count, cookie, ctx); |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 1388 | ctx->current_table = current_table_save; |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1389 | } |
| 1390 | |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 1391 | static void add_psp_firmware_entry(context *ctx, |
| 1392 | psp_directory_table *pspdir, |
| 1393 | void *table, amd_fw_type type, uint32_t size) |
| 1394 | { |
| 1395 | uint32_t count = pspdir->header.num_entries; |
| 1396 | uint32_t index; |
| 1397 | uint32_t current_table_save; |
| 1398 | |
| 1399 | current_table_save = ctx->current_table; |
| 1400 | ctx->current_table = (char *)pspdir - ctx->rom; |
| 1401 | |
| 1402 | /* If there is an entry of "type", replace it. */ |
| 1403 | for (index = 0; index < count; index++) { |
| 1404 | if (pspdir->entries[index].type == (uint8_t)type) |
| 1405 | break; |
| 1406 | } |
| 1407 | |
| 1408 | assert_fw_entry(count, MAX_PSP_ENTRIES, ctx); |
| 1409 | pspdir->entries[index].type = (uint8_t)type; |
| 1410 | pspdir->entries[index].subprog = 0; |
| 1411 | pspdir->entries[index].rsvd = 0; |
| 1412 | pspdir->entries[index].addr = BUFF_TO_RUN(*ctx, table); |
| 1413 | pspdir->entries[index].address_mode = SET_ADDR_MODE_BY_TABLE(pspdir); |
| 1414 | pspdir->entries[index].size = size; |
| 1415 | if (index == count) |
| 1416 | count++; |
| 1417 | |
| 1418 | pspdir->header.num_entries = count; |
| 1419 | pspdir->header.checksum = fletcher32(&pspdir->header.num_entries, |
| 1420 | count * sizeof(psp_directory_entry) |
| 1421 | + sizeof(pspdir->header.num_entries) |
| 1422 | + sizeof(pspdir->header.additional_info)); |
| 1423 | |
| 1424 | ctx->current_table = current_table_save; |
| 1425 | } |
| 1426 | |
Zheng Bao | ba3af5e | 2021-11-04 18:56:47 +0800 | [diff] [blame] | 1427 | static void *new_bios_dir(context *ctx, bool multi) |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1428 | { |
| 1429 | void *ptr; |
| 1430 | |
| 1431 | /* |
| 1432 | * Force both onto boundary when multi. Primary table is after |
| 1433 | * updatable table, so alignment ensures primary can stay intact |
| 1434 | * if secondary is reprogrammed. |
| 1435 | */ |
| 1436 | if (multi) |
Elyes Haouas | 7d67a19 | 2022-10-14 09:58:29 +0200 | [diff] [blame] | 1437 | ctx->current = ALIGN_UP(ctx->current, TABLE_ERASE_ALIGNMENT); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1438 | else |
Elyes Haouas | 7d67a19 | 2022-10-14 09:58:29 +0200 | [diff] [blame] | 1439 | ctx->current = ALIGN_UP(ctx->current, TABLE_ALIGNMENT); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1440 | ptr = BUFF_CURRENT(*ctx); |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 1441 | ((bios_directory_hdr *) ptr)->additional_info = 0; |
| 1442 | ((bios_directory_hdr *) ptr)->additional_info_fields.address_mode = ctx->address_mode; |
| 1443 | ctx->current_table = ctx->current; |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1444 | ctx->current += sizeof(bios_directory_hdr) |
| 1445 | + MAX_BIOS_ENTRIES * sizeof(bios_directory_entry); |
| 1446 | return ptr; |
| 1447 | } |
| 1448 | |
| 1449 | static int locate_bdt2_bios(bios_directory_table *level2, |
| 1450 | uint64_t *source, uint32_t *size) |
| 1451 | { |
Zheng Bao | 6d402ac | 2020-10-01 16:16:30 +0800 | [diff] [blame] | 1452 | uint32_t i; |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1453 | |
| 1454 | *source = 0; |
| 1455 | *size = 0; |
| 1456 | if (!level2) |
| 1457 | return 0; |
| 1458 | |
| 1459 | for (i = 0 ; i < level2->header.num_entries ; i++) { |
| 1460 | if (level2->entries[i].type == AMD_BIOS_BIN) { |
| 1461 | *source = level2->entries[i].source; |
| 1462 | *size = level2->entries[i].size; |
| 1463 | return 1; |
| 1464 | } |
| 1465 | } |
| 1466 | return 0; |
| 1467 | } |
| 1468 | |
| 1469 | static int have_bios_tables(amd_bios_entry *table) |
| 1470 | { |
| 1471 | int i; |
| 1472 | |
| 1473 | for (i = 0 ; table[i].type != AMD_BIOS_INVALID; i++) { |
| 1474 | if (table[i].level & BDT_LVL1 && table[i].filename) |
| 1475 | return 1; |
| 1476 | } |
| 1477 | return 0; |
| 1478 | } |
| 1479 | |
Marshall Dawson | c4a8c48 | 2020-01-21 17:17:59 -0700 | [diff] [blame] | 1480 | static int find_bios_entry(amd_bios_type type) |
| 1481 | { |
| 1482 | int i; |
| 1483 | |
| 1484 | for (i = 0; amd_bios_table[i].type != AMD_BIOS_INVALID; i++) { |
| 1485 | if (amd_bios_table[i].type == type) |
| 1486 | return i; |
| 1487 | } |
| 1488 | return -1; |
| 1489 | } |
| 1490 | |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1491 | static void integrate_bios_firmwares(context *ctx, |
| 1492 | bios_directory_table *biosdir, |
| 1493 | bios_directory_table *biosdir2, |
| 1494 | amd_bios_entry *fw_table, |
Zheng Bao | 2079589 | 2021-08-20 14:58:22 +0800 | [diff] [blame] | 1495 | uint32_t cookie, |
| 1496 | amd_cb_config *cb_config) |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1497 | { |
| 1498 | ssize_t bytes; |
Martin Roth | ec93313 | 2019-07-13 20:03:34 -0600 | [diff] [blame] | 1499 | unsigned int i, count; |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1500 | int level; |
Marshall Dawson | c4a8c48 | 2020-01-21 17:17:59 -0700 | [diff] [blame] | 1501 | int apob_idx; |
Martin Roth | eca423b | 2020-09-01 10:54:11 -0600 | [diff] [blame] | 1502 | uint32_t size; |
| 1503 | uint64_t source; |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1504 | |
| 1505 | /* This function can create a primary table, a secondary table, or a |
| 1506 | * flattened table which contains all applicable types. These if-else |
| 1507 | * statements infer what the caller intended. If a 2nd-level cookie |
| 1508 | * is passed, clearly a 2nd-level table is intended. However, a |
| 1509 | * 1st-level cookie may indicate level 1 or flattened. If the caller |
| 1510 | * passes a pointer to a 2nd-level table, then assume not flat. |
| 1511 | */ |
Zheng Bao | ba3af5e | 2021-11-04 18:56:47 +0800 | [diff] [blame] | 1512 | if (!cb_config->multi_level) |
Zheng Bao | 2079589 | 2021-08-20 14:58:22 +0800 | [diff] [blame] | 1513 | level = BDT_BOTH; |
Zheng Bao | 96a3371 | 2021-06-11 15:54:40 +0800 | [diff] [blame] | 1514 | else if (cookie == BHDL2_COOKIE) |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1515 | level = BDT_LVL2; |
| 1516 | else if (biosdir2) |
| 1517 | level = BDT_LVL1; |
| 1518 | else |
| 1519 | level = BDT_BOTH; |
| 1520 | |
Elyes Haouas | 7d67a19 | 2022-10-14 09:58:29 +0200 | [diff] [blame] | 1521 | ctx->current = ALIGN_UP(ctx->current, TABLE_ALIGNMENT); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1522 | |
| 1523 | for (i = 0, count = 0; fw_table[i].type != AMD_BIOS_INVALID; i++) { |
| 1524 | if (!(fw_table[i].level & level)) |
| 1525 | continue; |
| 1526 | if (fw_table[i].filename == NULL && ( |
Ritul Guru | 9a321f3 | 2022-07-29 11:06:40 +0530 | [diff] [blame] | 1527 | fw_table[i].type != AMD_BIOS_SIG && |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1528 | fw_table[i].type != AMD_BIOS_APOB && |
| 1529 | fw_table[i].type != AMD_BIOS_APOB_NV && |
| 1530 | fw_table[i].type != AMD_BIOS_L2_PTR && |
Martin Roth | 9455474 | 2020-04-14 14:59:36 -0600 | [diff] [blame] | 1531 | fw_table[i].type != AMD_BIOS_BIN && |
| 1532 | fw_table[i].type != AMD_BIOS_PSP_SHARED_MEM)) |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1533 | continue; |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1534 | |
| 1535 | /* BIOS Directory items may have additional requirements */ |
| 1536 | |
Ritul Guru | 9a321f3 | 2022-07-29 11:06:40 +0530 | [diff] [blame] | 1537 | /* SIG needs a size, else no choice but to skip */ |
| 1538 | if (fw_table[i].type == AMD_BIOS_SIG && !fw_table[i].size) |
| 1539 | continue; |
| 1540 | |
Martin Roth | 48dd9fe | 2020-07-29 16:32:25 -0600 | [diff] [blame] | 1541 | /* Check APOB_NV requirements */ |
| 1542 | if (fw_table[i].type == AMD_BIOS_APOB_NV) { |
| 1543 | if (!fw_table[i].size && !fw_table[i].src) |
| 1544 | continue; /* APOB_NV not used */ |
| 1545 | if (fw_table[i].src && !fw_table[i].size) { |
Zheng Bao | 77a2c67 | 2020-10-01 17:05:43 +0800 | [diff] [blame] | 1546 | fprintf(stderr, "Error: APOB NV address provided, but no size\n"); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1547 | free(ctx->rom); |
| 1548 | exit(1); |
| 1549 | } |
Martin Roth | 48dd9fe | 2020-07-29 16:32:25 -0600 | [diff] [blame] | 1550 | /* If the APOB isn't used, APOB_NV isn't used either */ |
Marshall Dawson | c4a8c48 | 2020-01-21 17:17:59 -0700 | [diff] [blame] | 1551 | apob_idx = find_bios_entry(AMD_BIOS_APOB); |
Martin Roth | 48dd9fe | 2020-07-29 16:32:25 -0600 | [diff] [blame] | 1552 | if (apob_idx < 0 || !fw_table[apob_idx].dest) |
| 1553 | continue; /* APOV NV not supported */ |
Marshall Dawson | c4a8c48 | 2020-01-21 17:17:59 -0700 | [diff] [blame] | 1554 | } |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1555 | |
| 1556 | /* APOB_DATA needs destination */ |
| 1557 | if (fw_table[i].type == AMD_BIOS_APOB && !fw_table[i].dest) { |
Zheng Bao | 77a2c67 | 2020-10-01 17:05:43 +0800 | [diff] [blame] | 1558 | fprintf(stderr, "Error: APOB destination not provided\n"); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1559 | free(ctx->rom); |
| 1560 | exit(1); |
| 1561 | } |
| 1562 | |
| 1563 | /* BIOS binary must have destination and uncompressed size. If |
| 1564 | * no filename given, then user must provide a source address. |
| 1565 | */ |
| 1566 | if (fw_table[i].type == AMD_BIOS_BIN) { |
| 1567 | if (!fw_table[i].dest || !fw_table[i].size) { |
Zheng Bao | 77a2c67 | 2020-10-01 17:05:43 +0800 | [diff] [blame] | 1568 | fprintf(stderr, "Error: BIOS binary destination and uncompressed size are required\n"); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1569 | free(ctx->rom); |
| 1570 | exit(1); |
| 1571 | } |
| 1572 | if (!fw_table[i].filename && !fw_table[i].src) { |
Zheng Bao | 77a2c67 | 2020-10-01 17:05:43 +0800 | [diff] [blame] | 1573 | fprintf(stderr, "Error: BIOS binary assumed outside amdfw.rom but no source address given\n"); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1574 | free(ctx->rom); |
| 1575 | exit(1); |
| 1576 | } |
| 1577 | } |
| 1578 | |
Martin Roth | 9455474 | 2020-04-14 14:59:36 -0600 | [diff] [blame] | 1579 | /* PSP_SHARED_MEM needs a destination and size */ |
| 1580 | if (fw_table[i].type == AMD_BIOS_PSP_SHARED_MEM && |
| 1581 | (!fw_table[i].dest || !fw_table[i].size)) |
| 1582 | continue; |
Zheng Bao | 5164e4b | 2021-10-30 12:09:07 +0800 | [diff] [blame] | 1583 | assert_fw_entry(count, MAX_BIOS_ENTRIES, ctx); |
Martin Roth | 9455474 | 2020-04-14 14:59:36 -0600 | [diff] [blame] | 1584 | |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1585 | biosdir->entries[count].type = fw_table[i].type; |
| 1586 | biosdir->entries[count].region_type = fw_table[i].region_type; |
| 1587 | biosdir->entries[count].dest = fw_table[i].dest ? |
| 1588 | fw_table[i].dest : (uint64_t)-1; |
| 1589 | biosdir->entries[count].reset = fw_table[i].reset; |
| 1590 | biosdir->entries[count].copy = fw_table[i].copy; |
| 1591 | biosdir->entries[count].ro = fw_table[i].ro; |
| 1592 | biosdir->entries[count].compressed = fw_table[i].zlib; |
| 1593 | biosdir->entries[count].inst = fw_table[i].inst; |
| 1594 | biosdir->entries[count].subprog = fw_table[i].subpr; |
| 1595 | |
| 1596 | switch (fw_table[i].type) { |
Ritul Guru | 9a321f3 | 2022-07-29 11:06:40 +0530 | [diff] [blame] | 1597 | case AMD_BIOS_SIG: |
| 1598 | /* Reserve size bytes within amdfw.rom */ |
| 1599 | biosdir->entries[count].size = fw_table[i].size; |
| 1600 | biosdir->entries[count].source = RUN_CURRENT(*ctx); |
| 1601 | biosdir->entries[count].address_mode = |
| 1602 | SET_ADDR_MODE_BY_TABLE(biosdir); |
| 1603 | memset(BUFF_CURRENT(*ctx), 0xff, |
| 1604 | biosdir->entries[count].size); |
Elyes Haouas | 7d67a19 | 2022-10-14 09:58:29 +0200 | [diff] [blame] | 1605 | ctx->current = ALIGN_UP(ctx->current |
Ritul Guru | 9a321f3 | 2022-07-29 11:06:40 +0530 | [diff] [blame] | 1606 | + biosdir->entries[count].size, 0x100U); |
| 1607 | break; |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1608 | case AMD_BIOS_APOB: |
| 1609 | biosdir->entries[count].size = fw_table[i].size; |
| 1610 | biosdir->entries[count].source = fw_table[i].src; |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 1611 | biosdir->entries[count].address_mode = SET_ADDR_MODE_BY_TABLE(biosdir); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1612 | break; |
| 1613 | case AMD_BIOS_APOB_NV: |
| 1614 | if (fw_table[i].src) { |
| 1615 | /* If source is given, use that and its size */ |
| 1616 | biosdir->entries[count].source = fw_table[i].src; |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 1617 | biosdir->entries[count].address_mode = |
Robert Zieba | 29bc79f | 2022-03-14 15:59:12 -0600 | [diff] [blame] | 1618 | SET_ADDR_MODE(biosdir, AMD_ADDR_REL_BIOS); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1619 | biosdir->entries[count].size = fw_table[i].size; |
| 1620 | } else { |
| 1621 | /* Else reserve size bytes within amdfw.rom */ |
Elyes Haouas | 7d67a19 | 2022-10-14 09:58:29 +0200 | [diff] [blame] | 1622 | ctx->current = ALIGN_UP(ctx->current, ERASE_ALIGNMENT); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1623 | biosdir->entries[count].source = RUN_CURRENT(*ctx); |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 1624 | biosdir->entries[count].address_mode = |
Robert Zieba | 29bc79f | 2022-03-14 15:59:12 -0600 | [diff] [blame] | 1625 | SET_ADDR_MODE(biosdir, AMD_ADDR_REL_BIOS); |
Elyes Haouas | 7d67a19 | 2022-10-14 09:58:29 +0200 | [diff] [blame] | 1626 | biosdir->entries[count].size = ALIGN_UP( |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1627 | fw_table[i].size, ERASE_ALIGNMENT); |
| 1628 | memset(BUFF_CURRENT(*ctx), 0xff, |
| 1629 | biosdir->entries[count].size); |
| 1630 | ctx->current = ctx->current |
| 1631 | + biosdir->entries[count].size; |
| 1632 | } |
| 1633 | break; |
| 1634 | case AMD_BIOS_BIN: |
| 1635 | /* Don't make a 2nd copy, point to the same one */ |
Martin Roth | eca423b | 2020-09-01 10:54:11 -0600 | [diff] [blame] | 1636 | if (level == BDT_LVL1 && locate_bdt2_bios(biosdir2, &source, &size)) { |
| 1637 | biosdir->entries[count].source = source; |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 1638 | biosdir->entries[count].address_mode = |
Robert Zieba | 29bc79f | 2022-03-14 15:59:12 -0600 | [diff] [blame] | 1639 | SET_ADDR_MODE(biosdir, AMD_ADDR_REL_BIOS); |
Martin Roth | eca423b | 2020-09-01 10:54:11 -0600 | [diff] [blame] | 1640 | biosdir->entries[count].size = size; |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1641 | break; |
Martin Roth | eca423b | 2020-09-01 10:54:11 -0600 | [diff] [blame] | 1642 | } |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1643 | |
| 1644 | /* level 2, or level 1 and no copy found in level 2 */ |
| 1645 | biosdir->entries[count].source = fw_table[i].src; |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 1646 | biosdir->entries[count].address_mode = |
Robert Zieba | 29bc79f | 2022-03-14 15:59:12 -0600 | [diff] [blame] | 1647 | SET_ADDR_MODE(biosdir, AMD_ADDR_REL_BIOS); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1648 | biosdir->entries[count].dest = fw_table[i].dest; |
| 1649 | biosdir->entries[count].size = fw_table[i].size; |
| 1650 | |
| 1651 | if (!fw_table[i].filename) |
| 1652 | break; |
| 1653 | |
| 1654 | bytes = copy_blob(BUFF_CURRENT(*ctx), |
| 1655 | fw_table[i].filename, BUFF_ROOM(*ctx)); |
| 1656 | if (bytes <= 0) { |
| 1657 | free(ctx->rom); |
| 1658 | exit(1); |
| 1659 | } |
| 1660 | |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 1661 | biosdir->entries[count].source = |
Robert Zieba | 29bc79f | 2022-03-14 15:59:12 -0600 | [diff] [blame] | 1662 | RUN_CURRENT_MODE(*ctx, AMD_ADDR_REL_BIOS); |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 1663 | biosdir->entries[count].address_mode = |
Robert Zieba | 29bc79f | 2022-03-14 15:59:12 -0600 | [diff] [blame] | 1664 | SET_ADDR_MODE(biosdir, AMD_ADDR_REL_BIOS); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1665 | |
Elyes Haouas | 7d67a19 | 2022-10-14 09:58:29 +0200 | [diff] [blame] | 1666 | ctx->current = ALIGN_UP(ctx->current + bytes, 0x100U); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1667 | break; |
Martin Roth | 9455474 | 2020-04-14 14:59:36 -0600 | [diff] [blame] | 1668 | case AMD_BIOS_PSP_SHARED_MEM: |
| 1669 | biosdir->entries[count].dest = fw_table[i].dest; |
| 1670 | biosdir->entries[count].size = fw_table[i].size; |
| 1671 | break; |
| 1672 | |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1673 | default: /* everything else is copied from input */ |
| 1674 | if (fw_table[i].type == AMD_BIOS_APCB || |
| 1675 | fw_table[i].type == AMD_BIOS_APCB_BK) |
Elyes Haouas | 7d67a19 | 2022-10-14 09:58:29 +0200 | [diff] [blame] | 1676 | ctx->current = ALIGN_UP( |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1677 | ctx->current, ERASE_ALIGNMENT); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1678 | bytes = copy_blob(BUFF_CURRENT(*ctx), |
| 1679 | fw_table[i].filename, BUFF_ROOM(*ctx)); |
| 1680 | if (bytes <= 0) { |
| 1681 | free(ctx->rom); |
| 1682 | exit(1); |
| 1683 | } |
| 1684 | |
| 1685 | biosdir->entries[count].size = (uint32_t)bytes; |
| 1686 | biosdir->entries[count].source = RUN_CURRENT(*ctx); |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 1687 | biosdir->entries[count].address_mode = SET_ADDR_MODE_BY_TABLE(biosdir); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1688 | |
Elyes Haouas | 7d67a19 | 2022-10-14 09:58:29 +0200 | [diff] [blame] | 1689 | ctx->current = ALIGN_UP(ctx->current + bytes, 0x100U); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1690 | break; |
| 1691 | } |
| 1692 | |
| 1693 | count++; |
| 1694 | } |
| 1695 | |
| 1696 | if (biosdir2) { |
Zheng Bao | 5164e4b | 2021-10-30 12:09:07 +0800 | [diff] [blame] | 1697 | assert_fw_entry(count, MAX_BIOS_ENTRIES, ctx); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1698 | biosdir->entries[count].type = AMD_BIOS_L2_PTR; |
Zheng Bao | e8e6043 | 2021-05-24 16:11:12 +0800 | [diff] [blame] | 1699 | biosdir->entries[count].region_type = 0; |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1700 | biosdir->entries[count].size = |
| 1701 | + MAX_BIOS_ENTRIES |
| 1702 | * sizeof(bios_directory_entry); |
| 1703 | biosdir->entries[count].source = |
| 1704 | BUFF_TO_RUN(*ctx, biosdir2); |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 1705 | biosdir->entries[count].address_mode = |
Robert Zieba | 29bc79f | 2022-03-14 15:59:12 -0600 | [diff] [blame] | 1706 | SET_ADDR_MODE(biosdir, AMD_ADDR_REL_BIOS); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1707 | biosdir->entries[count].subprog = 0; |
| 1708 | biosdir->entries[count].inst = 0; |
| 1709 | biosdir->entries[count].copy = 0; |
| 1710 | biosdir->entries[count].compressed = 0; |
| 1711 | biosdir->entries[count].dest = -1; |
| 1712 | biosdir->entries[count].reset = 0; |
| 1713 | biosdir->entries[count].ro = 0; |
| 1714 | count++; |
| 1715 | } |
| 1716 | |
Zheng Bao | bf29a0d | 2020-12-03 23:00:48 +0800 | [diff] [blame] | 1717 | fill_dir_header(biosdir, count, cookie, ctx); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1718 | } |
Matt Papageorge | be4376c | 2020-06-15 11:18:15 -0500 | [diff] [blame] | 1719 | |
| 1720 | enum { |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1721 | AMDFW_OPT_CONFIG = 'c', |
| 1722 | AMDFW_OPT_DEBUG = 'd', |
| 1723 | AMDFW_OPT_HELP = 'h', |
| 1724 | AMDFW_OPT_LIST_DEPEND = 'l', |
| 1725 | |
| 1726 | AMDFW_OPT_XHCI = 128, |
| 1727 | AMDFW_OPT_IMC, |
| 1728 | AMDFW_OPT_GEC, |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 1729 | AMDFW_OPT_RECOVERY_AB, |
Karthikeyan Ramasubramanian | ad06bae | 2022-04-08 14:19:55 -0600 | [diff] [blame] | 1730 | AMDFW_OPT_RECOVERY_AB_SINGLE_COPY, |
Zheng Bao | 993b43f | 2021-11-10 12:21:46 +0800 | [diff] [blame] | 1731 | AMDFW_OPT_USE_COMBO, |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1732 | AMDFW_OPT_MULTILEVEL, |
| 1733 | AMDFW_OPT_NVRAM, |
| 1734 | |
| 1735 | AMDFW_OPT_FUSE, |
| 1736 | AMDFW_OPT_UNLOCK, |
| 1737 | AMDFW_OPT_WHITELIST, |
| 1738 | AMDFW_OPT_USE_PSPSECUREOS, |
| 1739 | AMDFW_OPT_LOAD_MP2FW, |
| 1740 | AMDFW_OPT_LOAD_S0I3, |
Zheng Bao | 6c5ec8e | 2022-02-11 11:51:26 +0800 | [diff] [blame] | 1741 | AMDFW_OPT_SPL_TABLE, |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1742 | AMDFW_OPT_VERSTAGE, |
| 1743 | AMDFW_OPT_VERSTAGE_SIG, |
| 1744 | |
| 1745 | AMDFW_OPT_INSTANCE, |
| 1746 | AMDFW_OPT_APCB, |
| 1747 | AMDFW_OPT_APOBBASE, |
| 1748 | AMDFW_OPT_BIOSBIN, |
| 1749 | AMDFW_OPT_BIOSBIN_SOURCE, |
| 1750 | AMDFW_OPT_BIOSBIN_DEST, |
| 1751 | AMDFW_OPT_BIOS_UNCOMP_SIZE, |
| 1752 | AMDFW_OPT_UCODE, |
| 1753 | AMDFW_OPT_APOB_NVBASE, |
| 1754 | AMDFW_OPT_APOB_NVSIZE, |
| 1755 | |
| 1756 | AMDFW_OPT_OUTPUT, |
| 1757 | AMDFW_OPT_FLASHSIZE, |
| 1758 | AMDFW_OPT_LOCATION, |
| 1759 | AMDFW_OPT_ANYWHERE, |
| 1760 | AMDFW_OPT_SHAREDMEM, |
| 1761 | AMDFW_OPT_SHAREDMEM_SIZE, |
Kangheui Won | 3c164e1 | 2021-12-03 20:25:05 +1100 | [diff] [blame] | 1762 | AMDFW_OPT_SIGNED_OUTPUT, |
| 1763 | AMDFW_OPT_SIGNED_ADDR, |
Karthikeyan Ramasubramanian | ecb4e31 | 2022-11-02 16:53:54 -0600 | [diff] [blame] | 1764 | AMDFW_OPT_BODY_LOCATION, |
Matt Papageorge | be4376c | 2020-06-15 11:18:15 -0500 | [diff] [blame] | 1765 | /* begin after ASCII characters */ |
| 1766 | LONGOPT_SPI_READ_MODE = 256, |
| 1767 | LONGOPT_SPI_SPEED = 257, |
| 1768 | LONGOPT_SPI_MICRON_FLAG = 258, |
Ritul Guru | 9a321f3 | 2022-07-29 11:06:40 +0530 | [diff] [blame] | 1769 | LONGOPT_BIOS_SIG = 259, |
Ritul Guru | a2cb340 | 2022-08-29 00:51:08 +0530 | [diff] [blame] | 1770 | LONGOPT_NVRAM_BASE = 260, |
| 1771 | LONGOPT_NVRAM_SIZE = 261, |
Matt Papageorge | be4376c | 2020-06-15 11:18:15 -0500 | [diff] [blame] | 1772 | }; |
| 1773 | |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1774 | static char const optstring[] = {AMDFW_OPT_CONFIG, ':', |
| 1775 | AMDFW_OPT_DEBUG, AMDFW_OPT_HELP, AMDFW_OPT_LIST_DEPEND |
| 1776 | }; |
Marc Jones | 90099b6 | 2016-09-20 21:05:45 -0600 | [diff] [blame] | 1777 | |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1778 | static struct option long_options[] = { |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1779 | {"xhci", required_argument, 0, AMDFW_OPT_XHCI }, |
| 1780 | {"imc", required_argument, 0, AMDFW_OPT_IMC }, |
| 1781 | {"gec", required_argument, 0, AMDFW_OPT_GEC }, |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1782 | /* PSP Directory Table items */ |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 1783 | {"recovery-ab", no_argument, 0, AMDFW_OPT_RECOVERY_AB }, |
Karthikeyan Ramasubramanian | ad06bae | 2022-04-08 14:19:55 -0600 | [diff] [blame] | 1784 | {"recovery-ab-single-copy", no_argument, 0, AMDFW_OPT_RECOVERY_AB_SINGLE_COPY }, |
Zheng Bao | 993b43f | 2021-11-10 12:21:46 +0800 | [diff] [blame] | 1785 | {"use-combo", no_argument, 0, AMDFW_OPT_USE_COMBO }, |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1786 | {"multilevel", no_argument, 0, AMDFW_OPT_MULTILEVEL }, |
| 1787 | {"nvram", required_argument, 0, AMDFW_OPT_NVRAM }, |
Ritul Guru | a2cb340 | 2022-08-29 00:51:08 +0530 | [diff] [blame] | 1788 | {"nvram-base", required_argument, 0, LONGOPT_NVRAM_BASE }, |
| 1789 | {"nvram-size", required_argument, 0, LONGOPT_NVRAM_SIZE }, |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1790 | {"soft-fuse", required_argument, 0, AMDFW_OPT_FUSE }, |
| 1791 | {"token-unlock", no_argument, 0, AMDFW_OPT_UNLOCK }, |
| 1792 | {"whitelist", required_argument, 0, AMDFW_OPT_WHITELIST }, |
| 1793 | {"use-pspsecureos", no_argument, 0, AMDFW_OPT_USE_PSPSECUREOS }, |
| 1794 | {"load-mp2-fw", no_argument, 0, AMDFW_OPT_LOAD_MP2FW }, |
| 1795 | {"load-s0i3", no_argument, 0, AMDFW_OPT_LOAD_S0I3 }, |
Zheng Bao | 6c5ec8e | 2022-02-11 11:51:26 +0800 | [diff] [blame] | 1796 | {"spl-table", required_argument, 0, AMDFW_OPT_SPL_TABLE }, |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1797 | {"verstage", required_argument, 0, AMDFW_OPT_VERSTAGE }, |
| 1798 | {"verstage_sig", required_argument, 0, AMDFW_OPT_VERSTAGE_SIG }, |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1799 | /* BIOS Directory Table items */ |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1800 | {"instance", required_argument, 0, AMDFW_OPT_INSTANCE }, |
| 1801 | {"apcb", required_argument, 0, AMDFW_OPT_APCB }, |
| 1802 | {"apob-base", required_argument, 0, AMDFW_OPT_APOBBASE }, |
| 1803 | {"bios-bin", required_argument, 0, AMDFW_OPT_BIOSBIN }, |
| 1804 | {"bios-bin-src", required_argument, 0, AMDFW_OPT_BIOSBIN_SOURCE }, |
| 1805 | {"bios-bin-dest", required_argument, 0, AMDFW_OPT_BIOSBIN_DEST }, |
| 1806 | {"bios-uncomp-size", required_argument, 0, AMDFW_OPT_BIOS_UNCOMP_SIZE }, |
Ritul Guru | 9a321f3 | 2022-07-29 11:06:40 +0530 | [diff] [blame] | 1807 | {"bios-sig-size", required_argument, 0, LONGOPT_BIOS_SIG }, |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1808 | {"ucode", required_argument, 0, AMDFW_OPT_UCODE }, |
| 1809 | {"apob-nv-base", required_argument, 0, AMDFW_OPT_APOB_NVBASE }, |
| 1810 | {"apob-nv-size", required_argument, 0, AMDFW_OPT_APOB_NVSIZE }, |
Matt Papageorge | be4376c | 2020-06-15 11:18:15 -0500 | [diff] [blame] | 1811 | /* Embedded Firmware Structure items*/ |
| 1812 | {"spi-read-mode", required_argument, 0, LONGOPT_SPI_READ_MODE }, |
| 1813 | {"spi-speed", required_argument, 0, LONGOPT_SPI_SPEED }, |
| 1814 | {"spi-micron-flag", required_argument, 0, LONGOPT_SPI_MICRON_FLAG }, |
Karthikeyan Ramasubramanian | ecb4e31 | 2022-11-02 16:53:54 -0600 | [diff] [blame] | 1815 | {"body-location", required_argument, 0, AMDFW_OPT_BODY_LOCATION }, |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1816 | /* other */ |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1817 | {"output", required_argument, 0, AMDFW_OPT_OUTPUT }, |
| 1818 | {"flashsize", required_argument, 0, AMDFW_OPT_FLASHSIZE }, |
| 1819 | {"location", required_argument, 0, AMDFW_OPT_LOCATION }, |
| 1820 | {"anywhere", no_argument, 0, AMDFW_OPT_ANYWHERE }, |
| 1821 | {"sharedmem", required_argument, 0, AMDFW_OPT_SHAREDMEM }, |
| 1822 | {"sharedmem-size", required_argument, 0, AMDFW_OPT_SHAREDMEM_SIZE }, |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 1823 | |
Kangheui Won | 3c164e1 | 2021-12-03 20:25:05 +1100 | [diff] [blame] | 1824 | {"signed-output", required_argument, 0, AMDFW_OPT_SIGNED_OUTPUT }, |
| 1825 | {"signed-addr", required_argument, 0, AMDFW_OPT_SIGNED_ADDR }, |
| 1826 | |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1827 | {"config", required_argument, 0, AMDFW_OPT_CONFIG }, |
| 1828 | {"debug", no_argument, 0, AMDFW_OPT_DEBUG }, |
| 1829 | {"help", no_argument, 0, AMDFW_OPT_HELP }, |
| 1830 | {"list", no_argument, 0, AMDFW_OPT_LIST_DEPEND }, |
Marshall Dawson | f4b9b41 | 2017-03-17 16:30:51 -0600 | [diff] [blame] | 1831 | {NULL, 0, 0, 0 } |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1832 | }; |
| 1833 | |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 1834 | void register_fw_fuse(char *str) |
Marshall Dawson | ef79fcc | 2019-04-01 10:16:41 -0600 | [diff] [blame] | 1835 | { |
Zheng Bao | 6d402ac | 2020-10-01 16:16:30 +0800 | [diff] [blame] | 1836 | uint32_t i; |
Marshall Dawson | ef79fcc | 2019-04-01 10:16:41 -0600 | [diff] [blame] | 1837 | |
| 1838 | for (i = 0; i < sizeof(amd_psp_fw_table) / sizeof(amd_fw_entry); i++) { |
| 1839 | if (amd_psp_fw_table[i].type != AMD_PSP_FUSE_CHAIN) |
| 1840 | continue; |
| 1841 | |
| 1842 | amd_psp_fw_table[i].other = strtoull(str, NULL, 16); |
| 1843 | return; |
| 1844 | } |
| 1845 | } |
| 1846 | |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1847 | static void register_fw_token_unlock(void) |
| 1848 | { |
Zheng Bao | 6d402ac | 2020-10-01 16:16:30 +0800 | [diff] [blame] | 1849 | uint32_t i; |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1850 | |
| 1851 | for (i = 0; i < sizeof(amd_psp_fw_table) / sizeof(amd_fw_entry); i++) { |
| 1852 | if (amd_psp_fw_table[i].type != AMD_TOKEN_UNLOCK) |
| 1853 | continue; |
| 1854 | |
| 1855 | amd_psp_fw_table[i].other = 1; |
| 1856 | return; |
| 1857 | } |
| 1858 | } |
| 1859 | |
Marshall Dawson | dbae632 | 2019-03-04 10:31:03 -0700 | [diff] [blame] | 1860 | static void register_fw_filename(amd_fw_type type, uint8_t sub, char filename[]) |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1861 | { |
Martin Roth | 8806f7f | 2016-11-08 10:44:18 -0700 | [diff] [blame] | 1862 | unsigned int i; |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1863 | |
Martin Roth | cd15bc8 | 2016-11-08 11:34:02 -0700 | [diff] [blame] | 1864 | for (i = 0; i < sizeof(amd_fw_table) / sizeof(amd_fw_entry); i++) { |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1865 | if (amd_fw_table[i].type == type) { |
| 1866 | amd_fw_table[i].filename = filename; |
| 1867 | return; |
| 1868 | } |
| 1869 | } |
| 1870 | |
Marshall Dawson | 0e02ce8 | 2019-03-04 16:50:37 -0700 | [diff] [blame] | 1871 | for (i = 0; i < sizeof(amd_psp_fw_table) / sizeof(amd_fw_entry); i++) { |
Marshall Dawson | dbae632 | 2019-03-04 10:31:03 -0700 | [diff] [blame] | 1872 | if (amd_psp_fw_table[i].type != type) |
| 1873 | continue; |
| 1874 | |
| 1875 | if (amd_psp_fw_table[i].subprog == sub) { |
Marshall Dawson | 0e02ce8 | 2019-03-04 16:50:37 -0700 | [diff] [blame] | 1876 | amd_psp_fw_table[i].filename = filename; |
| 1877 | return; |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1878 | } |
| 1879 | } |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1880 | } |
| 1881 | |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1882 | static void register_bdt_data(amd_bios_type type, int sub, int ins, char name[]) |
| 1883 | { |
Zheng Bao | 6d402ac | 2020-10-01 16:16:30 +0800 | [diff] [blame] | 1884 | uint32_t i; |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1885 | |
| 1886 | for (i = 0; i < sizeof(amd_bios_table) / sizeof(amd_bios_entry); i++) { |
| 1887 | if (amd_bios_table[i].type == type |
| 1888 | && amd_bios_table[i].inst == ins |
| 1889 | && amd_bios_table[i].subpr == sub) { |
| 1890 | amd_bios_table[i].filename = name; |
| 1891 | return; |
| 1892 | } |
| 1893 | } |
| 1894 | } |
| 1895 | |
Ritul Guru | a2cb340 | 2022-08-29 00:51:08 +0530 | [diff] [blame] | 1896 | static void register_amd_psp_fw_addr(amd_fw_type type, int sub, |
| 1897 | char *dst_str, char *size_str) |
| 1898 | { |
| 1899 | unsigned int i; |
| 1900 | |
| 1901 | for (i = 0; i < sizeof(amd_psp_fw_table) / sizeof(amd_fw_entry); i++) { |
| 1902 | if (amd_psp_fw_table[i].type != type) |
| 1903 | continue; |
| 1904 | |
| 1905 | if (amd_psp_fw_table[i].subprog == sub) { |
| 1906 | if (dst_str) |
| 1907 | amd_psp_fw_table[i].dest = strtoull(dst_str, NULL, 16); |
| 1908 | if (size_str) |
| 1909 | amd_psp_fw_table[i].size = strtoul(size_str, NULL, 16); |
| 1910 | return; |
| 1911 | } |
| 1912 | } |
| 1913 | } |
| 1914 | |
| 1915 | static void register_bios_fw_addr(amd_bios_type type, char *src_str, |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1916 | char *dst_str, char *size_str) |
| 1917 | { |
Zheng Bao | 6d402ac | 2020-10-01 16:16:30 +0800 | [diff] [blame] | 1918 | uint32_t i; |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1919 | for (i = 0; i < sizeof(amd_bios_table) / sizeof(amd_bios_entry); i++) { |
| 1920 | if (amd_bios_table[i].type != type) |
| 1921 | continue; |
| 1922 | |
| 1923 | if (src_str) |
| 1924 | amd_bios_table[i].src = strtoull(src_str, NULL, 16); |
| 1925 | if (dst_str) |
| 1926 | amd_bios_table[i].dest = strtoull(dst_str, NULL, 16); |
| 1927 | if (size_str) |
| 1928 | amd_bios_table[i].size = strtoul(size_str, NULL, 16); |
| 1929 | |
| 1930 | return; |
| 1931 | } |
| 1932 | } |
| 1933 | |
Zheng Bao | c3007f3 | 2022-04-03 12:53:51 +0800 | [diff] [blame] | 1934 | static int set_efs_table(uint8_t soc_id, amd_cb_config *cb_config, |
| 1935 | embedded_firmware *amd_romsig, uint8_t efs_spi_readmode, |
| 1936 | uint8_t efs_spi_speed, uint8_t efs_spi_micron_flag) |
Matt Papageorge | be4376c | 2020-06-15 11:18:15 -0500 | [diff] [blame] | 1937 | { |
| 1938 | if ((efs_spi_readmode == 0xFF) || (efs_spi_speed == 0xFF)) { |
Zheng Bao | 77a2c67 | 2020-10-01 17:05:43 +0800 | [diff] [blame] | 1939 | fprintf(stderr, "Error: EFS read mode and SPI speed must be set\n"); |
Matt Papageorge | be4376c | 2020-06-15 11:18:15 -0500 | [diff] [blame] | 1940 | return 1; |
| 1941 | } |
Zheng Bao | c3007f3 | 2022-04-03 12:53:51 +0800 | [diff] [blame] | 1942 | |
| 1943 | /* amd_romsig->efs_gen introduced after RAVEN/PICASSO. |
| 1944 | * Leave as 0xffffffff for first gen */ |
| 1945 | if (cb_config->second_gen) { |
| 1946 | amd_romsig->efs_gen.gen = EFS_SECOND_GEN; |
| 1947 | amd_romsig->efs_gen.reserved = 0; |
| 1948 | } else { |
Zheng Bao | 487d045 | 2022-04-03 12:50:07 +0800 | [diff] [blame] | 1949 | amd_romsig->efs_gen.gen = EFS_BEFORE_SECOND_GEN; |
| 1950 | amd_romsig->efs_gen.reserved = ~0; |
Zheng Bao | c3007f3 | 2022-04-03 12:53:51 +0800 | [diff] [blame] | 1951 | } |
| 1952 | |
| 1953 | switch (soc_id) { |
Zheng Bao | 3d7623f | 2022-08-17 11:52:30 +0800 | [diff] [blame] | 1954 | case PLATFORM_CARRIZO: |
Zheng Bao | c3007f3 | 2022-04-03 12:53:51 +0800 | [diff] [blame] | 1955 | case PLATFORM_STONEYRIDGE: |
Matt Papageorge | be4376c | 2020-06-15 11:18:15 -0500 | [diff] [blame] | 1956 | amd_romsig->spi_readmode_f15_mod_60_6f = efs_spi_readmode; |
| 1957 | amd_romsig->fast_speed_new_f15_mod_60_6f = efs_spi_speed; |
| 1958 | break; |
| 1959 | case PLATFORM_RAVEN: |
| 1960 | case PLATFORM_PICASSO: |
Matt Papageorge | be4376c | 2020-06-15 11:18:15 -0500 | [diff] [blame] | 1961 | amd_romsig->spi_readmode_f17_mod_00_2f = efs_spi_readmode; |
| 1962 | amd_romsig->spi_fastspeed_f17_mod_00_2f = efs_spi_speed; |
| 1963 | switch (efs_spi_micron_flag) { |
| 1964 | case 0: |
| 1965 | amd_romsig->qpr_dummy_cycle_f17_mod_00_2f = 0xff; |
| 1966 | break; |
| 1967 | case 1: |
| 1968 | amd_romsig->qpr_dummy_cycle_f17_mod_00_2f = 0xa; |
| 1969 | break; |
| 1970 | default: |
Zheng Bao | 77a2c67 | 2020-10-01 17:05:43 +0800 | [diff] [blame] | 1971 | fprintf(stderr, "Error: EFS Micron flag must be correctly set.\n\n"); |
Matt Papageorge | be4376c | 2020-06-15 11:18:15 -0500 | [diff] [blame] | 1972 | return 1; |
| 1973 | } |
| 1974 | break; |
| 1975 | case PLATFORM_RENOIR: |
| 1976 | case PLATFORM_LUCIENNE: |
Zheng Bao | bf29a0d | 2020-12-03 23:00:48 +0800 | [diff] [blame] | 1977 | case PLATFORM_CEZANNE: |
Zheng Bao | 535ec53 | 2021-08-12 16:30:19 +0800 | [diff] [blame] | 1978 | case PLATFORM_MENDOCINO: |
Zheng Bao | de6f198 | 2022-10-16 20:32:43 +0800 | [diff] [blame] | 1979 | case PLATFORM_PHOENIX: |
| 1980 | case PLATFORM_GLINDA: |
Matt Papageorge | be4376c | 2020-06-15 11:18:15 -0500 | [diff] [blame] | 1981 | amd_romsig->spi_readmode_f17_mod_30_3f = efs_spi_readmode; |
| 1982 | amd_romsig->spi_fastspeed_f17_mod_30_3f = efs_spi_speed; |
| 1983 | switch (efs_spi_micron_flag) { |
| 1984 | case 0: |
| 1985 | amd_romsig->micron_detect_f17_mod_30_3f = 0xff; |
| 1986 | break; |
| 1987 | case 1: |
| 1988 | amd_romsig->micron_detect_f17_mod_30_3f = 0xaa; |
| 1989 | break; |
| 1990 | case 2: |
| 1991 | amd_romsig->micron_detect_f17_mod_30_3f = 0x55; |
| 1992 | break; |
| 1993 | default: |
Zheng Bao | 77a2c67 | 2020-10-01 17:05:43 +0800 | [diff] [blame] | 1994 | fprintf(stderr, "Error: EFS Micron flag must be correctly set.\n\n"); |
Matt Papageorge | be4376c | 2020-06-15 11:18:15 -0500 | [diff] [blame] | 1995 | return 1; |
| 1996 | } |
| 1997 | break; |
| 1998 | case PLATFORM_UNKNOWN: |
| 1999 | default: |
Zheng Bao | 77a2c67 | 2020-10-01 17:05:43 +0800 | [diff] [blame] | 2000 | fprintf(stderr, "Error: Invalid SOC name.\n\n"); |
Matt Papageorge | be4376c | 2020-06-15 11:18:15 -0500 | [diff] [blame] | 2001 | return 1; |
| 2002 | } |
| 2003 | return 0; |
| 2004 | } |
| 2005 | |
Karthikeyan Ramasubramanian | ecb4e31 | 2022-11-02 16:53:54 -0600 | [diff] [blame] | 2006 | static ssize_t write_efs(char *output, embedded_firmware *amd_romsig) |
| 2007 | { |
| 2008 | char efs_name[PATH_MAX], efs_tmp_name[PATH_MAX]; |
| 2009 | int ret; |
| 2010 | int fd; |
| 2011 | ssize_t bytes = -1; |
| 2012 | |
| 2013 | /* Create a tmp file and rename it at the end so that make does not get confused |
| 2014 | if amdfwtool is killed for some unexpected reasons. */ |
| 2015 | ret = snprintf(efs_tmp_name, sizeof(efs_tmp_name), "%s%s%s", |
| 2016 | output, EFS_FILE_SUFFIX, TMP_FILE_SUFFIX); |
| 2017 | if (ret < 0) { |
| 2018 | fprintf(stderr, "Error %s forming EFS tmp file name: %d\n", |
| 2019 | strerror(errno), ret); |
| 2020 | exit(1); |
| 2021 | } else if ((unsigned int)ret >= sizeof(efs_tmp_name)) { |
| 2022 | fprintf(stderr, "EFS File name %d > %zu\n", ret, sizeof(efs_tmp_name)); |
| 2023 | exit(1); |
| 2024 | } |
| 2025 | |
| 2026 | fd = open(efs_tmp_name, O_RDWR | O_CREAT | O_TRUNC, 0666); |
| 2027 | if (fd < 0) { |
| 2028 | fprintf(stderr, "Error: Opening %s file: %s\n", efs_tmp_name, strerror(errno)); |
| 2029 | exit(1); |
| 2030 | } |
| 2031 | |
| 2032 | bytes = write_from_buf_to_file(fd, amd_romsig, sizeof(*amd_romsig)); |
| 2033 | if (bytes != sizeof(*amd_romsig)) { |
| 2034 | fprintf(stderr, "Error: Writing to file %s failed\n", efs_tmp_name); |
| 2035 | exit(1); |
| 2036 | } |
| 2037 | close(fd); |
| 2038 | |
| 2039 | /* Rename the tmp file */ |
| 2040 | ret = snprintf(efs_name, sizeof(efs_name), "%s%s", output, EFS_FILE_SUFFIX); |
| 2041 | if (ret < 0) { |
| 2042 | fprintf(stderr, "Error %s forming EFS file name: %d\n", strerror(errno), ret); |
| 2043 | exit(1); |
| 2044 | } |
| 2045 | |
| 2046 | if (rename(efs_tmp_name, efs_name)) { |
| 2047 | fprintf(stderr, "Error: renaming file %s to %s\n", efs_tmp_name, efs_name); |
| 2048 | exit(1); |
| 2049 | } |
| 2050 | |
| 2051 | return bytes; |
| 2052 | } |
| 2053 | |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 2054 | int main(int argc, char **argv) |
| 2055 | { |
Marshall Dawson | 0e02ce8 | 2019-03-04 16:50:37 -0700 | [diff] [blame] | 2056 | int c; |
Martin Roth | 31d95a2 | 2016-11-08 11:22:12 -0700 | [diff] [blame] | 2057 | int retval = 0; |
Martin Roth | 60f1551 | 2016-11-08 09:55:01 -0700 | [diff] [blame] | 2058 | char *tmp; |
Martin Roth | 8806f7f | 2016-11-08 10:44:18 -0700 | [diff] [blame] | 2059 | char *rom = NULL; |
Marshall Dawson | 239286c | 2019-02-23 16:42:46 -0700 | [diff] [blame] | 2060 | embedded_firmware *amd_romsig; |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 2061 | psp_directory_table *pspdir = NULL; |
| 2062 | psp_directory_table *pspdir2 = NULL; |
| 2063 | psp_directory_table *pspdir2_b = NULL; |
Marshall Dawson | ef79fcc | 2019-04-01 10:16:41 -0600 | [diff] [blame] | 2064 | int fuse_defined = 0; |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 2065 | int targetfd; |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 2066 | char *output = NULL, *config = NULL; |
| 2067 | FILE *config_handle; |
Zheng Bao | 9c8ce3e | 2020-09-28 10:36:29 +0800 | [diff] [blame] | 2068 | context ctx = { 0 }; |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 2069 | /* Values cleared after each firmware or parameter, regardless if N/A */ |
| 2070 | uint8_t sub = 0, instance = 0; |
Zheng Bao | 99945dc | 2023-01-02 10:55:56 +0800 | [diff] [blame] | 2071 | uint32_t body_location = 0; |
Karthikeyan Ramasubramanian | ecb4e31 | 2022-11-02 16:53:54 -0600 | [diff] [blame] | 2072 | uint32_t efs_location = 0; |
Martin Roth | 37305e7 | 2020-04-07 14:16:39 -0600 | [diff] [blame] | 2073 | bool any_location = 0; |
Martin Roth | 0d3b118 | 2017-10-03 14:16:04 -0600 | [diff] [blame] | 2074 | uint32_t romsig_offset; |
Martin Roth | 60f1551 | 2016-11-08 09:55:01 -0700 | [diff] [blame] | 2075 | uint32_t rom_base_address; |
Matt Papageorge | be4376c | 2020-06-15 11:18:15 -0500 | [diff] [blame] | 2076 | uint8_t efs_spi_readmode = 0xff; |
| 2077 | uint8_t efs_spi_speed = 0xff; |
| 2078 | uint8_t efs_spi_micron_flag = 0xff; |
Kangheui Won | 3c164e1 | 2021-12-03 20:25:05 +1100 | [diff] [blame] | 2079 | const char *signed_output_file = NULL; |
| 2080 | uint64_t signed_start_addr = 0x0; |
Matt Papageorge | be4376c | 2020-06-15 11:18:15 -0500 | [diff] [blame] | 2081 | |
Fred Reitberger | f36b013 | 2022-06-29 13:54:57 -0400 | [diff] [blame] | 2082 | amd_cb_config cb_config = { 0 }; |
Zheng Bao | 9e90807 | 2020-10-28 11:39:13 +0800 | [diff] [blame] | 2083 | int debug = 0; |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 2084 | int list_deps = 0; |
| 2085 | |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 2086 | while (1) { |
| 2087 | int optindex = 0; |
| 2088 | |
| 2089 | c = getopt_long(argc, argv, optstring, long_options, &optindex); |
| 2090 | |
| 2091 | if (c == -1) |
| 2092 | break; |
| 2093 | |
| 2094 | switch (c) { |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 2095 | case AMDFW_OPT_XHCI: |
Marshall Dawson | dbae632 | 2019-03-04 10:31:03 -0700 | [diff] [blame] | 2096 | register_fw_filename(AMD_FW_XHCI, sub, optarg); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 2097 | sub = instance = 0; |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 2098 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 2099 | case AMDFW_OPT_IMC: |
Marshall Dawson | dbae632 | 2019-03-04 10:31:03 -0700 | [diff] [blame] | 2100 | register_fw_filename(AMD_FW_IMC, sub, optarg); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 2101 | sub = instance = 0; |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 2102 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 2103 | case AMDFW_OPT_GEC: |
Marshall Dawson | dbae632 | 2019-03-04 10:31:03 -0700 | [diff] [blame] | 2104 | register_fw_filename(AMD_FW_GEC, sub, optarg); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 2105 | sub = instance = 0; |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 2106 | break; |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 2107 | case AMDFW_OPT_RECOVERY_AB: |
| 2108 | cb_config.recovery_ab = true; |
| 2109 | break; |
Karthikeyan Ramasubramanian | ad06bae | 2022-04-08 14:19:55 -0600 | [diff] [blame] | 2110 | case AMDFW_OPT_RECOVERY_AB_SINGLE_COPY: |
| 2111 | cb_config.recovery_ab = true; |
| 2112 | cb_config.recovery_ab_single_copy = true; |
| 2113 | break; |
Zheng Bao | 993b43f | 2021-11-10 12:21:46 +0800 | [diff] [blame] | 2114 | case AMDFW_OPT_USE_COMBO: |
| 2115 | cb_config.use_combo = true; |
| 2116 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 2117 | case AMDFW_OPT_MULTILEVEL: |
Zheng Bao | ba3af5e | 2021-11-04 18:56:47 +0800 | [diff] [blame] | 2118 | cb_config.multi_level = true; |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 2119 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 2120 | case AMDFW_OPT_UNLOCK: |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 2121 | register_fw_token_unlock(); |
Zheng Bao | ba3af5e | 2021-11-04 18:56:47 +0800 | [diff] [blame] | 2122 | cb_config.unlock_secure = true; |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 2123 | sub = instance = 0; |
| 2124 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 2125 | case AMDFW_OPT_USE_PSPSECUREOS: |
Zheng Bao | ba3af5e | 2021-11-04 18:56:47 +0800 | [diff] [blame] | 2126 | cb_config.use_secureos = true; |
Marshall Dawson | dbae632 | 2019-03-04 10:31:03 -0700 | [diff] [blame] | 2127 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 2128 | case AMDFW_OPT_INSTANCE: |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 2129 | instance = strtoul(optarg, &tmp, 16); |
| 2130 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 2131 | case AMDFW_OPT_LOAD_MP2FW: |
Zheng Bao | ba3af5e | 2021-11-04 18:56:47 +0800 | [diff] [blame] | 2132 | cb_config.load_mp2_fw = true; |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 2133 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 2134 | case AMDFW_OPT_NVRAM: |
Marshall Dawson | dbae632 | 2019-03-04 10:31:03 -0700 | [diff] [blame] | 2135 | register_fw_filename(AMD_FW_PSP_NVRAM, sub, optarg); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 2136 | sub = instance = 0; |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 2137 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 2138 | case AMDFW_OPT_FUSE: |
Marshall Dawson | ef79fcc | 2019-04-01 10:16:41 -0600 | [diff] [blame] | 2139 | register_fw_fuse(optarg); |
| 2140 | fuse_defined = 1; |
| 2141 | sub = 0; |
| 2142 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 2143 | case AMDFW_OPT_APCB: |
Zheng Bao | 5caca94 | 2020-12-04 16:39:38 +0800 | [diff] [blame] | 2144 | if ((instance & 0xF0) == 0) |
| 2145 | register_bdt_data(AMD_BIOS_APCB, sub, instance & 0xF, optarg); |
| 2146 | else |
| 2147 | register_bdt_data(AMD_BIOS_APCB_BK, sub, |
| 2148 | instance & 0xF, optarg); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 2149 | sub = instance = 0; |
| 2150 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 2151 | case AMDFW_OPT_APOBBASE: |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 2152 | /* APOB destination */ |
Ritul Guru | a2cb340 | 2022-08-29 00:51:08 +0530 | [diff] [blame] | 2153 | register_bios_fw_addr(AMD_BIOS_APOB, 0, optarg, 0); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 2154 | sub = instance = 0; |
| 2155 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 2156 | case AMDFW_OPT_APOB_NVBASE: |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 2157 | /* APOB NV source */ |
Ritul Guru | a2cb340 | 2022-08-29 00:51:08 +0530 | [diff] [blame] | 2158 | register_bios_fw_addr(AMD_BIOS_APOB_NV, optarg, 0, 0); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 2159 | sub = instance = 0; |
| 2160 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 2161 | case AMDFW_OPT_APOB_NVSIZE: |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 2162 | /* APOB NV size */ |
Ritul Guru | a2cb340 | 2022-08-29 00:51:08 +0530 | [diff] [blame] | 2163 | register_bios_fw_addr(AMD_BIOS_APOB_NV, 0, 0, optarg); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 2164 | sub = instance = 0; |
| 2165 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 2166 | case AMDFW_OPT_BIOSBIN: |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 2167 | register_bdt_data(AMD_BIOS_BIN, sub, instance, optarg); |
| 2168 | sub = instance = 0; |
| 2169 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 2170 | case AMDFW_OPT_BIOSBIN_SOURCE: |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 2171 | /* BIOS source */ |
Ritul Guru | a2cb340 | 2022-08-29 00:51:08 +0530 | [diff] [blame] | 2172 | register_bios_fw_addr(AMD_BIOS_BIN, optarg, 0, 0); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 2173 | sub = instance = 0; |
| 2174 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 2175 | case AMDFW_OPT_BIOSBIN_DEST: |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 2176 | /* BIOS destination */ |
Ritul Guru | a2cb340 | 2022-08-29 00:51:08 +0530 | [diff] [blame] | 2177 | register_bios_fw_addr(AMD_BIOS_BIN, 0, optarg, 0); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 2178 | sub = instance = 0; |
| 2179 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 2180 | case AMDFW_OPT_BIOS_UNCOMP_SIZE: |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 2181 | /* BIOS destination size */ |
Ritul Guru | a2cb340 | 2022-08-29 00:51:08 +0530 | [diff] [blame] | 2182 | register_bios_fw_addr(AMD_BIOS_BIN, 0, 0, optarg); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 2183 | sub = instance = 0; |
| 2184 | break; |
Ritul Guru | 9a321f3 | 2022-07-29 11:06:40 +0530 | [diff] [blame] | 2185 | case LONGOPT_BIOS_SIG: |
| 2186 | /* BIOS signature size */ |
Ritul Guru | a2cb340 | 2022-08-29 00:51:08 +0530 | [diff] [blame] | 2187 | register_bios_fw_addr(AMD_BIOS_SIG, 0, 0, optarg); |
Ritul Guru | 9a321f3 | 2022-07-29 11:06:40 +0530 | [diff] [blame] | 2188 | sub = instance = 0; |
| 2189 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 2190 | case AMDFW_OPT_UCODE: |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 2191 | register_bdt_data(AMD_BIOS_UCODE, sub, |
| 2192 | instance, optarg); |
| 2193 | sub = instance = 0; |
| 2194 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 2195 | case AMDFW_OPT_LOAD_S0I3: |
Zheng Bao | ba3af5e | 2021-11-04 18:56:47 +0800 | [diff] [blame] | 2196 | cb_config.s0i3 = true; |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 2197 | break; |
Zheng Bao | 6c5ec8e | 2022-02-11 11:51:26 +0800 | [diff] [blame] | 2198 | case AMDFW_OPT_SPL_TABLE: |
| 2199 | register_fw_filename(AMD_FW_SPL, sub, optarg); |
| 2200 | sub = instance = 0; |
| 2201 | cb_config.have_mb_spl = true; |
| 2202 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 2203 | case AMDFW_OPT_WHITELIST: |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 2204 | register_fw_filename(AMD_FW_PSP_WHITELIST, sub, optarg); |
| 2205 | sub = instance = 0; |
Zheng Bao | ba3af5e | 2021-11-04 18:56:47 +0800 | [diff] [blame] | 2206 | cb_config.have_whitelist = true; |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 2207 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 2208 | case AMDFW_OPT_VERSTAGE: |
Martin Roth | d3ce8c8 | 2019-07-13 20:13:07 -0600 | [diff] [blame] | 2209 | register_fw_filename(AMD_FW_PSP_VERSTAGE, sub, optarg); |
| 2210 | sub = instance = 0; |
| 2211 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 2212 | case AMDFW_OPT_VERSTAGE_SIG: |
Martin Roth | b1f648f | 2020-09-01 09:36:59 -0600 | [diff] [blame] | 2213 | register_fw_filename(AMD_FW_VERSTAGE_SIG, sub, optarg); |
| 2214 | sub = instance = 0; |
| 2215 | break; |
Kangheui Won | 3c164e1 | 2021-12-03 20:25:05 +1100 | [diff] [blame] | 2216 | case AMDFW_OPT_SIGNED_OUTPUT: |
| 2217 | signed_output_file = optarg; |
| 2218 | sub = instance = 0; |
| 2219 | break; |
| 2220 | case AMDFW_OPT_SIGNED_ADDR: |
| 2221 | signed_start_addr = strtoull(optarg, NULL, 10); |
| 2222 | sub = instance = 0; |
| 2223 | break; |
Matt Papageorge | be4376c | 2020-06-15 11:18:15 -0500 | [diff] [blame] | 2224 | case LONGOPT_SPI_READ_MODE: |
| 2225 | efs_spi_readmode = strtoull(optarg, NULL, 16); |
| 2226 | sub = instance = 0; |
| 2227 | break; |
| 2228 | case LONGOPT_SPI_SPEED: |
| 2229 | efs_spi_speed = strtoull(optarg, NULL, 16); |
| 2230 | sub = instance = 0; |
| 2231 | break; |
| 2232 | case LONGOPT_SPI_MICRON_FLAG: |
| 2233 | efs_spi_micron_flag = strtoull(optarg, NULL, 16); |
| 2234 | sub = instance = 0; |
| 2235 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 2236 | case AMDFW_OPT_OUTPUT: |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 2237 | output = optarg; |
| 2238 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 2239 | case AMDFW_OPT_FLASHSIZE: |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 2240 | ctx.rom_size = (uint32_t)strtoul(optarg, &tmp, 16); |
Martin Roth | 60f1551 | 2016-11-08 09:55:01 -0700 | [diff] [blame] | 2241 | if (*tmp != '\0') { |
Zheng Bao | 77a2c67 | 2020-10-01 17:05:43 +0800 | [diff] [blame] | 2242 | fprintf(stderr, "Error: ROM size specified" |
Martin Roth | 60f1551 | 2016-11-08 09:55:01 -0700 | [diff] [blame] | 2243 | " incorrectly (%s)\n\n", optarg); |
Martin Roth | 31d95a2 | 2016-11-08 11:22:12 -0700 | [diff] [blame] | 2244 | retval = 1; |
Martin Roth | 60f1551 | 2016-11-08 09:55:01 -0700 | [diff] [blame] | 2245 | } |
| 2246 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 2247 | case AMDFW_OPT_LOCATION: |
Karthikeyan Ramasubramanian | ecb4e31 | 2022-11-02 16:53:54 -0600 | [diff] [blame] | 2248 | efs_location = (uint32_t)strtoul(optarg, &tmp, 16); |
Martin Roth | 0d3b118 | 2017-10-03 14:16:04 -0600 | [diff] [blame] | 2249 | if (*tmp != '\0') { |
Zheng Bao | 77a2c67 | 2020-10-01 17:05:43 +0800 | [diff] [blame] | 2250 | fprintf(stderr, "Error: Directory Location specified" |
Martin Roth | 0d3b118 | 2017-10-03 14:16:04 -0600 | [diff] [blame] | 2251 | " incorrectly (%s)\n\n", optarg); |
| 2252 | retval = 1; |
| 2253 | } |
Zheng Bao | 99945dc | 2023-01-02 10:55:56 +0800 | [diff] [blame] | 2254 | if (body_location == 0) |
| 2255 | body_location = efs_location; |
Martin Roth | 0d3b118 | 2017-10-03 14:16:04 -0600 | [diff] [blame] | 2256 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 2257 | case AMDFW_OPT_ANYWHERE: |
Martin Roth | 37305e7 | 2020-04-07 14:16:39 -0600 | [diff] [blame] | 2258 | any_location = 1; |
| 2259 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 2260 | case AMDFW_OPT_SHAREDMEM: |
Martin Roth | 9455474 | 2020-04-14 14:59:36 -0600 | [diff] [blame] | 2261 | /* shared memory destination */ |
Ritul Guru | a2cb340 | 2022-08-29 00:51:08 +0530 | [diff] [blame] | 2262 | register_bios_fw_addr(AMD_BIOS_PSP_SHARED_MEM, 0, optarg, 0); |
Martin Roth | 9455474 | 2020-04-14 14:59:36 -0600 | [diff] [blame] | 2263 | sub = instance = 0; |
| 2264 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 2265 | case AMDFW_OPT_SHAREDMEM_SIZE: |
Martin Roth | 9455474 | 2020-04-14 14:59:36 -0600 | [diff] [blame] | 2266 | /* shared memory size */ |
Ritul Guru | a2cb340 | 2022-08-29 00:51:08 +0530 | [diff] [blame] | 2267 | register_bios_fw_addr(AMD_BIOS_PSP_SHARED_MEM, NULL, NULL, optarg); |
Martin Roth | 9455474 | 2020-04-14 14:59:36 -0600 | [diff] [blame] | 2268 | sub = instance = 0; |
| 2269 | break; |
Ritul Guru | a2cb340 | 2022-08-29 00:51:08 +0530 | [diff] [blame] | 2270 | case LONGOPT_NVRAM_BASE: |
| 2271 | /* PSP NV base */ |
| 2272 | register_amd_psp_fw_addr(AMD_FW_PSP_NVRAM, sub, optarg, 0); |
| 2273 | sub = instance = 0; |
| 2274 | break; |
| 2275 | case LONGOPT_NVRAM_SIZE: |
| 2276 | /* PSP NV size */ |
| 2277 | register_amd_psp_fw_addr(AMD_FW_PSP_NVRAM, sub, 0, optarg); |
| 2278 | sub = instance = 0; |
| 2279 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 2280 | case AMDFW_OPT_CONFIG: |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 2281 | config = optarg; |
| 2282 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 2283 | case AMDFW_OPT_DEBUG: |
Zheng Bao | 9e90807 | 2020-10-28 11:39:13 +0800 | [diff] [blame] | 2284 | debug = 1; |
| 2285 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 2286 | case AMDFW_OPT_HELP: |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 2287 | usage(); |
Martin Roth | 31d95a2 | 2016-11-08 11:22:12 -0700 | [diff] [blame] | 2288 | return 0; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 2289 | case AMDFW_OPT_LIST_DEPEND: |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 2290 | list_deps = 1; |
| 2291 | break; |
Karthikeyan Ramasubramanian | ecb4e31 | 2022-11-02 16:53:54 -0600 | [diff] [blame] | 2292 | case AMDFW_OPT_BODY_LOCATION: |
Zheng Bao | 99945dc | 2023-01-02 10:55:56 +0800 | [diff] [blame] | 2293 | body_location = (uint32_t)strtoul(optarg, &tmp, 16); |
Karthikeyan Ramasubramanian | ecb4e31 | 2022-11-02 16:53:54 -0600 | [diff] [blame] | 2294 | if (*tmp != '\0') { |
| 2295 | fprintf(stderr, "Error: Body Location specified" |
| 2296 | " incorrectly (%s)\n\n", optarg); |
| 2297 | retval = 1; |
| 2298 | } |
| 2299 | break; |
| 2300 | |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 2301 | default: |
| 2302 | break; |
| 2303 | } |
| 2304 | } |
| 2305 | |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 2306 | if (config) { |
| 2307 | config_handle = fopen(config, "r"); |
| 2308 | if (config_handle == NULL) { |
| 2309 | fprintf(stderr, "Can not open file %s for reading: %s\n", |
| 2310 | config, strerror(errno)); |
| 2311 | exit(1); |
| 2312 | } |
| 2313 | if (process_config(config_handle, &cb_config, list_deps) == 0) { |
| 2314 | fprintf(stderr, "Configuration file %s parsing error\n", config); |
| 2315 | fclose(config_handle); |
| 2316 | exit(1); |
| 2317 | } |
| 2318 | fclose(config_handle); |
| 2319 | } |
Zheng Bao | 9e90807 | 2020-10-28 11:39:13 +0800 | [diff] [blame] | 2320 | /* For debug. */ |
| 2321 | if (debug) { |
| 2322 | dump_psp_firmwares(amd_psp_fw_table); |
| 2323 | dump_bdt_firmwares(amd_bios_table); |
| 2324 | } |
| 2325 | |
Marshall Dawson | ef79fcc | 2019-04-01 10:16:41 -0600 | [diff] [blame] | 2326 | if (!fuse_defined) |
| 2327 | register_fw_fuse(DEFAULT_SOFT_FUSE_CHAIN); |
| 2328 | |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 2329 | if (!output && !list_deps) { |
| 2330 | fprintf(stderr, "Error: Output value is not specified.\n\n"); |
Martin Roth | 31d95a2 | 2016-11-08 11:22:12 -0700 | [diff] [blame] | 2331 | retval = 1; |
| 2332 | } |
| 2333 | |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 2334 | if ((ctx.rom_size % 1024 != 0) && !list_deps) { |
| 2335 | fprintf(stderr, "Error: ROM Size (%d bytes) should be a multiple of" |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 2336 | " 1024 bytes.\n\n", ctx.rom_size); |
Martin Roth | 31d95a2 | 2016-11-08 11:22:12 -0700 | [diff] [blame] | 2337 | retval = 1; |
Martin Roth | 60f1551 | 2016-11-08 09:55:01 -0700 | [diff] [blame] | 2338 | } |
| 2339 | |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 2340 | if ((ctx.rom_size < MIN_ROM_KB * 1024) && !list_deps) { |
| 2341 | fprintf(stderr, "Error: ROM Size (%dKB) must be at least %dKB.\n\n", |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 2342 | ctx.rom_size / 1024, MIN_ROM_KB); |
Martin Roth | 31d95a2 | 2016-11-08 11:22:12 -0700 | [diff] [blame] | 2343 | retval = 1; |
| 2344 | } |
| 2345 | |
| 2346 | if (retval) { |
| 2347 | usage(); |
| 2348 | return retval; |
Martin Roth | 60f1551 | 2016-11-08 09:55:01 -0700 | [diff] [blame] | 2349 | } |
| 2350 | |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 2351 | if (list_deps) { |
| 2352 | return retval; |
| 2353 | } |
| 2354 | |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 2355 | printf(" AMDFWTOOL Using ROM size of %dKB\n", ctx.rom_size / 1024); |
Martin Roth | 60f1551 | 2016-11-08 09:55:01 -0700 | [diff] [blame] | 2356 | |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 2357 | rom_base_address = 0xFFFFFFFF - ctx.rom_size + 1; |
Karthikeyan Ramasubramanian | ecb4e31 | 2022-11-02 16:53:54 -0600 | [diff] [blame] | 2358 | if (efs_location && (efs_location < rom_base_address)) { |
| 2359 | fprintf(stderr, "Error: EFS/Directory location outside of ROM.\n\n"); |
| 2360 | return 1; |
| 2361 | } |
| 2362 | |
Zheng Bao | 99945dc | 2023-01-02 10:55:56 +0800 | [diff] [blame] | 2363 | if (!efs_location && body_location) { |
Karthikeyan Ramasubramanian | ecb4e31 | 2022-11-02 16:53:54 -0600 | [diff] [blame] | 2364 | fprintf(stderr, "Error AMDFW body location specified without EFS location.\n"); |
| 2365 | return 1; |
| 2366 | } |
| 2367 | |
| 2368 | /* |
| 2369 | * On boards using vboot, there can be more than one instance of EFS + AMDFW Body. |
| 2370 | * For the instance in the RO section, there is no need to split EFS + AMDFW body |
| 2371 | * currently. This condition is to ensure that it is not accidentally split. Revisit |
| 2372 | * this condition if such a need arises in the future. |
| 2373 | */ |
Zheng Bao | 99945dc | 2023-01-02 10:55:56 +0800 | [diff] [blame] | 2374 | if (!any_location && body_location != efs_location) { |
Karthikeyan Ramasubramanian | ecb4e31 | 2022-11-02 16:53:54 -0600 | [diff] [blame] | 2375 | fprintf(stderr, "Error: EFS cannot be separate from AMDFW Body.\n"); |
| 2376 | return 1; |
| 2377 | } |
| 2378 | |
Zheng Bao | 99945dc | 2023-01-02 10:55:56 +0800 | [diff] [blame] | 2379 | if (body_location != efs_location && |
| 2380 | body_location < ALIGN(efs_location + sizeof(embedded_firmware), BLOB_ALIGNMENT)) { |
Karthikeyan Ramasubramanian | ecb4e31 | 2022-11-02 16:53:54 -0600 | [diff] [blame] | 2381 | fprintf(stderr, "Error: Insufficient space between EFS and Blobs.\n"); |
| 2382 | fprintf(stderr, " Require safe spacing of 256 bytes\n"); |
Martin Roth | 0d3b118 | 2017-10-03 14:16:04 -0600 | [diff] [blame] | 2383 | return 1; |
| 2384 | } |
Zheng Bao | 4e8fb35 | 2022-11-21 21:34:45 +0800 | [diff] [blame] | 2385 | if (efs_location & 0xFF000000) |
| 2386 | efs_location = efs_location - rom_base_address; |
| 2387 | if (body_location & 0xFF000000) |
| 2388 | body_location = body_location - rom_base_address; |
Martin Roth | 0d3b118 | 2017-10-03 14:16:04 -0600 | [diff] [blame] | 2389 | |
Martin Roth | 37305e7 | 2020-04-07 14:16:39 -0600 | [diff] [blame] | 2390 | if (any_location) { |
Zheng Bao | 99945dc | 2023-01-02 10:55:56 +0800 | [diff] [blame] | 2391 | if ((body_location & 0x3f) || (efs_location & 0x3f)) { |
Karthikeyan Ramasubramanian | ecb4e31 | 2022-11-02 16:53:54 -0600 | [diff] [blame] | 2392 | fprintf(stderr, "Error: Invalid Directory/EFS location.\n"); |
Zheng Bao | 77a2c67 | 2020-10-01 17:05:43 +0800 | [diff] [blame] | 2393 | fprintf(stderr, " Valid locations are 64-byte aligned\n"); |
Martin Roth | 37305e7 | 2020-04-07 14:16:39 -0600 | [diff] [blame] | 2394 | return 1; |
| 2395 | } |
| 2396 | } else { |
Zheng Bao | 4e8fb35 | 2022-11-21 21:34:45 +0800 | [diff] [blame] | 2397 | /* efs_location is relative address now. */ |
Karthikeyan Ramasubramanian | ecb4e31 | 2022-11-02 16:53:54 -0600 | [diff] [blame] | 2398 | switch (efs_location) { |
Zheng Bao | 92c920b | 2022-12-08 13:56:13 +0800 | [diff] [blame] | 2399 | case 0: |
Zheng Bao | 4e8fb35 | 2022-11-21 21:34:45 +0800 | [diff] [blame] | 2400 | case 0xFA0000: |
| 2401 | case 0xF20000: |
| 2402 | case 0xE20000: |
| 2403 | case 0xC20000: |
| 2404 | case 0x820000: |
| 2405 | case 0x020000: |
| 2406 | break; |
| 2407 | case 0x7A0000: |
| 2408 | case 0x720000: |
| 2409 | case 0x620000: |
| 2410 | case 0x420000: |
| 2411 | /* Special cases for 8M. */ |
| 2412 | if (ctx.rom_size != 0x800000) { |
| 2413 | fprintf(stderr, "Error: Invalid Directory location.\n"); |
| 2414 | fprintf(stderr, "%x is only for 8M image size.", efs_location); |
| 2415 | return 1; |
| 2416 | } |
| 2417 | break; |
| 2418 | case 0x3A0000: |
| 2419 | case 0x320000: |
| 2420 | case 0x220000: |
| 2421 | /* Special cases for 4M. */ |
| 2422 | if (ctx.rom_size != 0x400000) { |
| 2423 | fprintf(stderr, "Error: Invalid Directory location.\n"); |
| 2424 | fprintf(stderr, "%x is only for 4M image size.", efs_location); |
| 2425 | return 1; |
| 2426 | } |
Martin Roth | 37305e7 | 2020-04-07 14:16:39 -0600 | [diff] [blame] | 2427 | break; |
| 2428 | default: |
Zheng Bao | 77a2c67 | 2020-10-01 17:05:43 +0800 | [diff] [blame] | 2429 | fprintf(stderr, "Error: Invalid Directory location.\n"); |
| 2430 | fprintf(stderr, " Valid locations are 0xFFFA0000, 0xFFF20000,\n"); |
| 2431 | fprintf(stderr, " 0xFFE20000, 0xFFC20000, 0xFF820000, 0xFF020000\n"); |
Zheng Bao | 4e8fb35 | 2022-11-21 21:34:45 +0800 | [diff] [blame] | 2432 | fprintf(stderr, " 0xFA0000, 0xF20000, 0xE20000, 0xC20000,\n"); |
| 2433 | fprintf(stderr, " 0x820000, 0x020000\n"); |
Martin Roth | 37305e7 | 2020-04-07 14:16:39 -0600 | [diff] [blame] | 2434 | return 1; |
| 2435 | } |
Martin Roth | 0d3b118 | 2017-10-03 14:16:04 -0600 | [diff] [blame] | 2436 | } |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 2437 | ctx.rom = malloc(ctx.rom_size); |
| 2438 | if (!ctx.rom) { |
Zheng Bao | 77a2c67 | 2020-10-01 17:05:43 +0800 | [diff] [blame] | 2439 | fprintf(stderr, "Error: Failed to allocate memory\n"); |
Martin Roth | 31d95a2 | 2016-11-08 11:22:12 -0700 | [diff] [blame] | 2440 | return 1; |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 2441 | } |
| 2442 | memset(ctx.rom, 0xFF, ctx.rom_size); |
Martin Roth | 60f1551 | 2016-11-08 09:55:01 -0700 | [diff] [blame] | 2443 | |
Karthikeyan Ramasubramanian | ecb4e31 | 2022-11-02 16:53:54 -0600 | [diff] [blame] | 2444 | if (efs_location) { |
Zheng Bao | 99945dc | 2023-01-02 10:55:56 +0800 | [diff] [blame] | 2445 | if (efs_location != body_location) { |
Zheng Bao | 4e8fb35 | 2022-11-21 21:34:45 +0800 | [diff] [blame] | 2446 | romsig_offset = efs_location; |
| 2447 | ctx.current = body_location; |
Karthikeyan Ramasubramanian | ecb4e31 | 2022-11-02 16:53:54 -0600 | [diff] [blame] | 2448 | } else { |
Zheng Bao | 4e8fb35 | 2022-11-21 21:34:45 +0800 | [diff] [blame] | 2449 | romsig_offset = efs_location; |
Karthikeyan Ramasubramanian | ecb4e31 | 2022-11-02 16:53:54 -0600 | [diff] [blame] | 2450 | ctx.current = romsig_offset + sizeof(embedded_firmware); |
| 2451 | } |
| 2452 | } else { |
| 2453 | romsig_offset = AMD_ROMSIG_OFFSET; |
| 2454 | ctx.current = romsig_offset + sizeof(embedded_firmware); |
| 2455 | } |
Martin Roth | 0d3b118 | 2017-10-03 14:16:04 -0600 | [diff] [blame] | 2456 | |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 2457 | amd_romsig = BUFF_OFFSET(ctx, romsig_offset); |
Marshall Dawson | 239286c | 2019-02-23 16:42:46 -0700 | [diff] [blame] | 2458 | amd_romsig->signature = EMBEDDED_FW_SIGNATURE; |
| 2459 | amd_romsig->imc_entry = 0; |
| 2460 | amd_romsig->gec_entry = 0; |
| 2461 | amd_romsig->xhci_entry = 0; |
Martin Roth | 60f1551 | 2016-11-08 09:55:01 -0700 | [diff] [blame] | 2462 | |
Zheng Bao | 4bf6f49 | 2023-01-25 22:37:29 +0800 | [diff] [blame] | 2463 | if (cb_config.soc_id != PLATFORM_UNKNOWN) { |
| 2464 | retval = set_efs_table(cb_config.soc_id, &cb_config, amd_romsig, |
| 2465 | efs_spi_readmode, efs_spi_speed, efs_spi_micron_flag); |
Zheng Bao | 570645d | 2021-11-03 10:25:03 +0800 | [diff] [blame] | 2466 | if (retval) { |
| 2467 | fprintf(stderr, "ERROR: Failed to initialize EFS table!\n"); |
| 2468 | return retval; |
Matt Papageorge | be4376c | 2020-06-15 11:18:15 -0500 | [diff] [blame] | 2469 | } |
| 2470 | } else { |
Zheng Bao | 77a2c67 | 2020-10-01 17:05:43 +0800 | [diff] [blame] | 2471 | fprintf(stderr, "WARNING: No SOC name specified.\n"); |
Matt Papageorge | be4376c | 2020-06-15 11:18:15 -0500 | [diff] [blame] | 2472 | } |
| 2473 | |
Felix Held | 21a8e38 | 2022-03-29 23:10:45 +0200 | [diff] [blame] | 2474 | if (cb_config.need_ish) |
Robert Zieba | 29bc79f | 2022-03-14 15:59:12 -0600 | [diff] [blame] | 2475 | ctx.address_mode = AMD_ADDR_REL_TAB; |
Zheng Bao | c3007f3 | 2022-04-03 12:53:51 +0800 | [diff] [blame] | 2476 | else if (cb_config.second_gen) |
Robert Zieba | 29bc79f | 2022-03-14 15:59:12 -0600 | [diff] [blame] | 2477 | ctx.address_mode = AMD_ADDR_REL_BIOS; |
Zheng Bao | da83d2c | 2021-06-04 19:03:10 +0800 | [diff] [blame] | 2478 | else |
Robert Zieba | 29bc79f | 2022-03-14 15:59:12 -0600 | [diff] [blame] | 2479 | ctx.address_mode = AMD_ADDR_PHYSICAL; |
Zheng Bao | 7c7294f | 2023-01-04 16:38:28 +0800 | [diff] [blame] | 2480 | printf(" AMDFWTOOL Using firmware directory location of address: 0x%08x", |
| 2481 | efs_location); |
| 2482 | if (body_location != efs_location) |
| 2483 | printf(" with a split body at: 0x%08x\n", body_location); |
| 2484 | else |
| 2485 | printf("\n"); |
Zheng Bao | da83d2c | 2021-06-04 19:03:10 +0800 | [diff] [blame] | 2486 | |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 2487 | integrate_firmwares(&ctx, amd_romsig, amd_fw_table); |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 2488 | |
Elyes Haouas | 7d67a19 | 2022-10-14 09:58:29 +0200 | [diff] [blame] | 2489 | ctx.current = ALIGN_UP(ctx.current, 0x10000U); /* TODO: is it necessary? */ |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 2490 | ctx.current_table = 0; |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 2491 | |
Kangheui Won | 3c164e1 | 2021-12-03 20:25:05 +1100 | [diff] [blame] | 2492 | /* If the tool is invoked with command-line options to keep the signed PSP |
| 2493 | binaries separate, process the signed binaries first. */ |
| 2494 | if (signed_output_file && signed_start_addr) |
| 2495 | process_signed_psp_firmwares(signed_output_file, |
| 2496 | amd_psp_fw_table, |
| 2497 | signed_start_addr, |
Zheng Bao | 4bf6f49 | 2023-01-25 22:37:29 +0800 | [diff] [blame] | 2498 | cb_config.soc_id); |
Kangheui Won | 3c164e1 | 2021-12-03 20:25:05 +1100 | [diff] [blame] | 2499 | |
Zheng Bao | 481661e | 2021-08-20 14:47:46 +0800 | [diff] [blame] | 2500 | if (cb_config.multi_level) { |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 2501 | /* Do 2nd PSP directory followed by 1st */ |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 2502 | pspdir2 = new_psp_dir(&ctx, cb_config.multi_level); |
| 2503 | integrate_psp_firmwares(&ctx, pspdir2, NULL, NULL, |
Zheng Bao | 4bf6f49 | 2023-01-25 22:37:29 +0800 | [diff] [blame] | 2504 | amd_psp_fw_table, PSPL2_COOKIE, &cb_config); |
Karthikeyan Ramasubramanian | ad06bae | 2022-04-08 14:19:55 -0600 | [diff] [blame] | 2505 | if (cb_config.recovery_ab && !cb_config.recovery_ab_single_copy) { |
| 2506 | /* Create a copy of PSP Directory 2 in the backup slot B. |
| 2507 | Related biosdir2_b copy will be created later. */ |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 2508 | pspdir2_b = new_psp_dir(&ctx, cb_config.multi_level); |
| 2509 | integrate_psp_firmwares(&ctx, pspdir2_b, NULL, NULL, |
Zheng Bao | 4bf6f49 | 2023-01-25 22:37:29 +0800 | [diff] [blame] | 2510 | amd_psp_fw_table, PSPL2_COOKIE, &cb_config); |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 2511 | } else { |
Karthikeyan Ramasubramanian | ad06bae | 2022-04-08 14:19:55 -0600 | [diff] [blame] | 2512 | /* |
| 2513 | * Either the platform is using only one slot or B is same as above |
| 2514 | * directories for A. Skip creating pspdir2_b here to save flash space. |
| 2515 | * Related biosdir2_b will be skipped automatically. |
| 2516 | */ |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 2517 | pspdir2_b = NULL; /* More explicitly */ |
| 2518 | } |
Zheng Bao | 481661e | 2021-08-20 14:47:46 +0800 | [diff] [blame] | 2519 | pspdir = new_psp_dir(&ctx, cb_config.multi_level); |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 2520 | integrate_psp_firmwares(&ctx, pspdir, pspdir2, pspdir2_b, |
Zheng Bao | 4bf6f49 | 2023-01-25 22:37:29 +0800 | [diff] [blame] | 2521 | amd_psp_fw_table, PSP_COOKIE, &cb_config); |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 2522 | } else { |
| 2523 | /* flat: PSP 1 cookie and no pointer to 2nd table */ |
Zheng Bao | 481661e | 2021-08-20 14:47:46 +0800 | [diff] [blame] | 2524 | pspdir = new_psp_dir(&ctx, cb_config.multi_level); |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 2525 | integrate_psp_firmwares(&ctx, pspdir, NULL, NULL, |
Zheng Bao | 4bf6f49 | 2023-01-25 22:37:29 +0800 | [diff] [blame] | 2526 | amd_psp_fw_table, PSP_COOKIE, &cb_config); |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 2527 | } |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 2528 | |
Zheng Bao | 4bfb36e | 2023-02-11 22:13:36 +0800 | [diff] [blame^] | 2529 | switch (cb_config.soc_id) { |
| 2530 | case PLATFORM_UNKNOWN: |
Felix Held | ad68b07 | 2021-10-18 14:00:35 +0200 | [diff] [blame] | 2531 | amd_romsig->psp_directory = BUFF_TO_RUN(ctx, pspdir); |
Zheng Bao | 4bfb36e | 2023-02-11 22:13:36 +0800 | [diff] [blame^] | 2532 | break; |
| 2533 | case PLATFORM_CEZANNE: |
| 2534 | case PLATFORM_MENDOCINO: |
| 2535 | case PLATFORM_PHOENIX: |
| 2536 | case PLATFORM_GLINDA: |
| 2537 | case PLATFORM_CARRIZO: |
| 2538 | case PLATFORM_STONEYRIDGE: |
| 2539 | case PLATFORM_RAVEN: |
| 2540 | case PLATFORM_PICASSO: |
| 2541 | case PLATFORM_LUCIENNE: |
| 2542 | case PLATFORM_RENOIR: |
| 2543 | default: |
| 2544 | amd_romsig->new_psp_directory = BUFF_TO_RUN(ctx, pspdir); |
| 2545 | break; |
| 2546 | } |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 2547 | |
Zheng Bao | 993b43f | 2021-11-10 12:21:46 +0800 | [diff] [blame] | 2548 | if (cb_config.use_combo) { |
| 2549 | psp_combo_directory *combo_dir = new_combo_dir(&ctx); |
| 2550 | amd_romsig->combo_psp_directory = BUFF_TO_RUN(ctx, combo_dir); |
| 2551 | /* 0 -Compare PSP ID, 1 -Compare chip family ID */ |
| 2552 | combo_dir->entries[0].id_sel = 0; |
Zheng Bao | 4bf6f49 | 2023-01-25 22:37:29 +0800 | [diff] [blame] | 2553 | combo_dir->entries[0].id = get_psp_id(cb_config.soc_id); |
Zheng Bao | 993b43f | 2021-11-10 12:21:46 +0800 | [diff] [blame] | 2554 | combo_dir->entries[0].lvl2_addr = BUFF_TO_RUN(ctx, pspdir); |
Zheng Bao | 4fcc9f2 | 2015-11-20 12:29:04 +0800 | [diff] [blame] | 2555 | |
Zheng Bao | 993b43f | 2021-11-10 12:21:46 +0800 | [diff] [blame] | 2556 | combo_dir->header.lookup = 1; |
| 2557 | fill_dir_header(combo_dir, 1, PSP2_COOKIE, &ctx); |
| 2558 | } |
Zheng Bao | 4fcc9f2 | 2015-11-20 12:29:04 +0800 | [diff] [blame] | 2559 | |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 2560 | if (have_bios_tables(amd_bios_table)) { |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 2561 | bios_directory_table *biosdir = NULL; |
Zheng Bao | 481661e | 2021-08-20 14:47:46 +0800 | [diff] [blame] | 2562 | if (cb_config.multi_level) { |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 2563 | /* Do 2nd level BIOS directory followed by 1st */ |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 2564 | bios_directory_table *biosdir2 = NULL; |
| 2565 | bios_directory_table *biosdir2_b = NULL; |
| 2566 | |
| 2567 | biosdir2 = new_bios_dir(&ctx, cb_config.multi_level); |
| 2568 | |
Zheng Bao | edd1e36 | 2021-11-04 17:47:07 +0800 | [diff] [blame] | 2569 | integrate_bios_firmwares(&ctx, biosdir2, NULL, |
Zheng Bao | 96a3371 | 2021-06-11 15:54:40 +0800 | [diff] [blame] | 2570 | amd_bios_table, BHDL2_COOKIE, &cb_config); |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 2571 | if (cb_config.recovery_ab) { |
| 2572 | if (pspdir2_b != NULL) { |
| 2573 | biosdir2_b = new_bios_dir(&ctx, cb_config.multi_level); |
| 2574 | integrate_bios_firmwares(&ctx, biosdir2_b, NULL, |
Zheng Bao | 96a3371 | 2021-06-11 15:54:40 +0800 | [diff] [blame] | 2575 | amd_bios_table, BHDL2_COOKIE, &cb_config); |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 2576 | } |
| 2577 | add_psp_firmware_entry(&ctx, pspdir2, biosdir2, |
| 2578 | AMD_FW_BIOS_TABLE, TABLE_ALIGNMENT); |
| 2579 | if (pspdir2_b != NULL) |
| 2580 | add_psp_firmware_entry(&ctx, pspdir2_b, biosdir2_b, |
| 2581 | AMD_FW_BIOS_TABLE, TABLE_ALIGNMENT); |
| 2582 | } else { |
| 2583 | biosdir = new_bios_dir(&ctx, cb_config.multi_level); |
| 2584 | integrate_bios_firmwares(&ctx, biosdir, biosdir2, |
Zheng Bao | 96a3371 | 2021-06-11 15:54:40 +0800 | [diff] [blame] | 2585 | amd_bios_table, BHD_COOKIE, &cb_config); |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 2586 | } |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 2587 | } else { |
Zheng Bao | 96a3371 | 2021-06-11 15:54:40 +0800 | [diff] [blame] | 2588 | /* flat: BHD1 cookie and no pointer to 2nd table */ |
Zheng Bao | 481661e | 2021-08-20 14:47:46 +0800 | [diff] [blame] | 2589 | biosdir = new_bios_dir(&ctx, cb_config.multi_level); |
Zheng Bao | edd1e36 | 2021-11-04 17:47:07 +0800 | [diff] [blame] | 2590 | integrate_bios_firmwares(&ctx, biosdir, NULL, |
Zheng Bao | 96a3371 | 2021-06-11 15:54:40 +0800 | [diff] [blame] | 2591 | amd_bios_table, BHD_COOKIE, &cb_config); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 2592 | } |
Zheng Bao | 4bf6f49 | 2023-01-25 22:37:29 +0800 | [diff] [blame] | 2593 | switch (cb_config.soc_id) { |
Zheng Bao | bf29a0d | 2020-12-03 23:00:48 +0800 | [diff] [blame] | 2594 | case PLATFORM_RENOIR: |
| 2595 | case PLATFORM_LUCIENNE: |
| 2596 | case PLATFORM_CEZANNE: |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 2597 | if (!cb_config.recovery_ab) |
| 2598 | amd_romsig->bios3_entry = BUFF_TO_RUN(ctx, biosdir); |
Zheng Bao | bf29a0d | 2020-12-03 23:00:48 +0800 | [diff] [blame] | 2599 | break; |
Zheng Bao | 535ec53 | 2021-08-12 16:30:19 +0800 | [diff] [blame] | 2600 | case PLATFORM_MENDOCINO: |
Zheng Bao | de6f198 | 2022-10-16 20:32:43 +0800 | [diff] [blame] | 2601 | case PLATFORM_PHOENIX: |
| 2602 | case PLATFORM_GLINDA: |
Zheng Bao | 535ec53 | 2021-08-12 16:30:19 +0800 | [diff] [blame] | 2603 | break; |
Zheng Bao | 3d7623f | 2022-08-17 11:52:30 +0800 | [diff] [blame] | 2604 | case PLATFORM_CARRIZO: |
Zheng Bao | bf29a0d | 2020-12-03 23:00:48 +0800 | [diff] [blame] | 2605 | case PLATFORM_STONEYRIDGE: |
| 2606 | case PLATFORM_RAVEN: |
| 2607 | case PLATFORM_PICASSO: |
| 2608 | default: |
| 2609 | amd_romsig->bios1_entry = BUFF_TO_RUN(ctx, biosdir); |
| 2610 | break; |
| 2611 | } |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 2612 | } |
| 2613 | |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 2614 | /* Free the filename. */ |
| 2615 | free_psp_firmware_filenames(amd_psp_fw_table); |
| 2616 | free_bdt_firmware_filenames(amd_bios_table); |
| 2617 | |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 2618 | targetfd = open(output, O_RDWR | O_CREAT | O_TRUNC, 0666); |
Martin Roth | 31d95a2 | 2016-11-08 11:22:12 -0700 | [diff] [blame] | 2619 | if (targetfd >= 0) { |
Zheng Bao | 4739691 | 2020-09-29 17:33:17 +0800 | [diff] [blame] | 2620 | ssize_t bytes; |
Zheng Bao | 4e8fb35 | 2022-11-21 21:34:45 +0800 | [diff] [blame] | 2621 | uint32_t offset = body_location ? body_location : AMD_ROMSIG_OFFSET; |
Karthikeyan Ramasubramanian | ecb4e31 | 2022-11-02 16:53:54 -0600 | [diff] [blame] | 2622 | |
| 2623 | bytes = write(targetfd, BUFF_OFFSET(ctx, offset), ctx.current - offset); |
| 2624 | if (bytes != ctx.current - offset) { |
Zheng Bao | 4739691 | 2020-09-29 17:33:17 +0800 | [diff] [blame] | 2625 | fprintf(stderr, "Error: Writing to file %s failed\n", output); |
| 2626 | retval = 1; |
| 2627 | } |
Martin Roth | 31d95a2 | 2016-11-08 11:22:12 -0700 | [diff] [blame] | 2628 | close(targetfd); |
| 2629 | } else { |
Zheng Bao | 77a2c67 | 2020-10-01 17:05:43 +0800 | [diff] [blame] | 2630 | fprintf(stderr, "Error: could not open file: %s\n", output); |
Martin Roth | 31d95a2 | 2016-11-08 11:22:12 -0700 | [diff] [blame] | 2631 | retval = 1; |
| 2632 | } |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 2633 | |
Zheng Bao | 99945dc | 2023-01-02 10:55:56 +0800 | [diff] [blame] | 2634 | if (efs_location != body_location) { |
Karthikeyan Ramasubramanian | ecb4e31 | 2022-11-02 16:53:54 -0600 | [diff] [blame] | 2635 | ssize_t bytes; |
| 2636 | |
| 2637 | bytes = write_efs(output, amd_romsig); |
| 2638 | if (bytes != sizeof(*amd_romsig)) { |
| 2639 | fprintf(stderr, "Error: Writing EFS\n"); |
| 2640 | retval = 1; |
| 2641 | } |
| 2642 | } |
| 2643 | |
Martin Roth | 31d95a2 | 2016-11-08 11:22:12 -0700 | [diff] [blame] | 2644 | free(rom); |
| 2645 | return retval; |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 2646 | } |