Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 1 | config SOC_INTEL_BROADWELL |
| 2 | bool |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 3 | select CACHE_MRC_SETTINGS |
Angel Pons | 3f0a95a | 2020-11-23 13:34:56 +0100 | [diff] [blame] | 4 | select CPU_INTEL_HASWELL |
Matt DeVillier | 773488f | 2017-10-18 12:27:25 -0500 | [diff] [blame] | 5 | select INTEL_GMA_ACPI |
Angel Pons | dbdd528 | 2021-06-14 12:14:48 +0200 | [diff] [blame] | 6 | select MRC_SETTINGS_PROTECT |
| 7 | select REG_SCRIPT |
Kyösti Mälkki | e8a3af1 | 2022-11-19 18:39:22 +0200 | [diff] [blame] | 8 | select TCO_SPACE_NOT_YET_SPLIT |
Elyes Haouas | 4bf1385 | 2023-07-22 10:32:08 +0200 | [diff] [blame^] | 9 | help |
| 10 | Intel Broadwell and Haswell ULT support. |
| 11 | |
| 12 | if SOC_INTEL_BROADWELL |
Youness Alaoui | b191c9f | 2017-05-08 15:22:03 -0400 | [diff] [blame] | 13 | |
Angel Pons | 865c97c | 2021-06-23 16:51:16 +0200 | [diff] [blame] | 14 | config BROADWELL_LPDDR3 |
| 15 | bool |
| 16 | help |
| 17 | Selected by mainboards using LPDDR3 DRAM to supply mainboard-specific |
| 18 | LPDDR3 DQ and DQS CPU-to-DRAM mapping info needed to perform raminit. |
| 19 | |
Yu-Ping Wu | 35835de | 2022-08-01 02:54:10 +0000 | [diff] [blame] | 20 | config VBOOT |
| 21 | select VBOOT_MUST_REQUEST_DISPLAY |
Yu-Ping Wu | 478c71e | 2022-08-16 11:22:29 +0800 | [diff] [blame] | 22 | select VBOOT_STARTS_IN_BOOTBLOCK |
Yu-Ping Wu | 35835de | 2022-08-01 02:54:10 +0000 | [diff] [blame] | 23 | |
Shelley Chen | 4e9bb33 | 2021-10-20 15:43:45 -0700 | [diff] [blame] | 24 | config ECAM_MMCONF_BASE_ADDRESS |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 25 | default 0xf0000000 |
| 26 | |
Shelley Chen | 4e9bb33 | 2021-10-20 15:43:45 -0700 | [diff] [blame] | 27 | config ECAM_MMCONF_BUS_NUMBER |
Angel Pons | 9debbd6 | 2021-01-28 12:42:53 +0100 | [diff] [blame] | 28 | default 64 |
| 29 | |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 30 | config VGA_BIOS_ID |
| 31 | string |
| 32 | default "8086,0406" |
| 33 | |
Angel Pons | c715dc8 | 2021-01-31 00:33:04 +0100 | [diff] [blame] | 34 | config FIXED_MCHBAR_MMIO_BASE |
| 35 | default 0xfed10000 |
| 36 | |
| 37 | config FIXED_DMIBAR_MMIO_BASE |
| 38 | default 0xfed18000 |
| 39 | |
| 40 | config FIXED_EPBAR_MMIO_BASE |
| 41 | default 0xfed19000 |
| 42 | |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 43 | config DCACHE_RAM_BASE |
| 44 | hex |
| 45 | default 0xff7c0000 |
| 46 | |
| 47 | config DCACHE_RAM_SIZE |
| 48 | hex |
| 49 | default 0x10000 |
| 50 | help |
| 51 | The size of the cache-as-ram region required during bootblock |
| 52 | and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE |
| 53 | must add up to a power of 2. |
| 54 | |
| 55 | config DCACHE_RAM_MRC_VAR_SIZE |
| 56 | hex |
| 57 | default 0x30000 |
| 58 | help |
| 59 | The amount of cache-as-ram region required by the reference code. |
| 60 | |
Arthur Heymans | 5bb15f1 | 2018-12-22 16:02:25 +0100 | [diff] [blame] | 61 | config DCACHE_BSP_STACK_SIZE |
| 62 | hex |
| 63 | default 0x2000 |
| 64 | help |
| 65 | The amount of anticipated stack usage in CAR by bootblock and |
| 66 | other stages. |
| 67 | |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 68 | config HAVE_MRC |
| 69 | bool "Add a Memory Reference Code binary" |
| 70 | help |
| 71 | Select this option to add a Memory Reference Code binary to |
| 72 | the resulting coreboot image. |
| 73 | |
| 74 | Note: Without this binary coreboot will not work |
| 75 | |
| 76 | if HAVE_MRC |
| 77 | |
| 78 | config MRC_FILE |
| 79 | string "Intel Memory Reference Code path and filename" |
| 80 | depends on HAVE_MRC |
| 81 | default "mrc.bin" |
| 82 | help |
| 83 | The filename of the file to use as Memory Reference Code binary. |
| 84 | |
| 85 | config MRC_BIN_ADDRESS |
| 86 | hex |
| 87 | default 0xfffa0000 |
| 88 | |
Yu-Ping Wu | 35835de | 2022-08-01 02:54:10 +0000 | [diff] [blame] | 89 | # The UEFI System Agent binary needs to be at a fixed offset in the flash |
| 90 | # and can therefore only reside in the COREBOOT fmap region |
| 91 | config RO_REGION_ONLY |
| 92 | string |
| 93 | depends on VBOOT |
| 94 | default "mrc.bin" |
| 95 | |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 96 | endif # HAVE_MRC |
| 97 | |
Patrick Georgi | e6e9493 | 2015-06-22 22:26:45 +0200 | [diff] [blame] | 98 | config HAVE_REFCODE_BLOB |
| 99 | depends on ARCH_X86 |
| 100 | bool "An external reference code blob should be put into cbfs." |
| 101 | default n |
| 102 | help |
| 103 | The reference code blob will be placed into cbfs. |
| 104 | |
| 105 | if HAVE_REFCODE_BLOB |
| 106 | |
| 107 | config REFCODE_BLOB_FILE |
| 108 | string "Path and filename to reference code blob." |
| 109 | default "refcode.elf" |
| 110 | help |
| 111 | The path and filename to the file to be added to cbfs. |
| 112 | |
| 113 | endif # HAVE_REFCODE_BLOB |
| 114 | |
Angel Pons | dbdd528 | 2021-06-14 12:14:48 +0200 | [diff] [blame] | 115 | source "src/soc/intel/broadwell/pch/Kconfig" |
| 116 | |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 117 | endif |