soc/intel/broadwell: Select CPU_INTEL_HASWELL
This allows us to drop many now-redundant Kconfig options.
Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical.
The default configuration file also remains identical, as expected.
Change-Id: I20b0200550508679bf2533342ce918b221dcf81e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46953
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig
index 7f27026..14bbb81 100644
--- a/src/soc/intel/broadwell/Kconfig
+++ b/src/soc/intel/broadwell/Kconfig
@@ -12,14 +12,10 @@
config SOC_SPECIFIC_OPTIONS
def_bool y
select ACPI_INTEL_HARDWARE_SLEEP_VALUES
- select ARCH_ALL_STAGES_X86_32
- select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES
select BOOT_DEVICE_SUPPORTS_WRITES
select CACHE_MRC_SETTINGS
+ select CPU_INTEL_HASWELL
select MRC_SETTINGS_PROTECT
- select CPU_INTEL_COMMON
- select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
- select SUPPORT_CPU_UCODE_IN_CBFS
select HAVE_SMI_HANDLER
select SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS
select SOUTHBRIDGE_INTEL_COMMON_RESET
@@ -28,14 +24,10 @@
select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9
select HAVE_USBDEBUG
select IOAPIC
+ select INTEL_LYNXPOINT_LP
select REG_SCRIPT
- select PARALLEL_MP
select RTC
select SPI_FLASH
- select SSE2
- select TSC_SYNC_MFENCE
- select UDELAY_TSC
- select TSC_MONOTONIC_TIMER
select SOC_INTEL_COMMON
select INTEL_DESCRIPTOR_MODE_CAPABLE
select HAVE_EM100PRO_SPI_CONSOLE_SUPPORT
@@ -43,10 +35,6 @@
select HAVE_POWER_STATE_AFTER_FAILURE
select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE
-config MAX_CPUS
- int
- default 8
-
config PCIEXP_ASPM
bool
default y
@@ -91,18 +79,6 @@
hex
default 0xf0000000
-config SMM_TSEG_SIZE
- hex
- default 0x800000
-
-config IED_REGION_SIZE
- hex
- default 0x400000
-
-config SMM_RESERVED_SIZE
- hex
- default 0x100000
-
config VGA_BIOS_ID
string
default "8086,0406"