Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 1 | config SOC_INTEL_BROADWELL |
| 2 | bool |
| 3 | help |
| 4 | Intel Broadwell and Haswell ULT support. |
| 5 | |
| 6 | if SOC_INTEL_BROADWELL |
| 7 | |
Angel Pons | 417a6da | 2020-10-29 13:19:48 +0100 | [diff] [blame] | 8 | config INTEL_LYNXPOINT_LP |
| 9 | bool |
| 10 | default y if SOC_INTEL_BROADWELL |
| 11 | |
Angel Pons | a3288b3 | 2020-11-23 13:00:51 +0100 | [diff] [blame] | 12 | config SOC_SPECIFIC_OPTIONS |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 13 | def_bool y |
Kyösti Mälkki | 4abc731 | 2021-01-12 17:46:30 +0200 | [diff] [blame] | 14 | select ACPI_HAS_DEVICE_NVS |
Aaron Durbin | 9e6d143 | 2016-07-13 23:21:41 -0500 | [diff] [blame] | 15 | select ACPI_INTEL_HARDWARE_SLEEP_VALUES |
Aaron Durbin | e8e118d | 2016-08-12 15:00:10 -0500 | [diff] [blame] | 16 | select BOOT_DEVICE_SUPPORTS_WRITES |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 17 | select CACHE_MRC_SETTINGS |
Angel Pons | 3f0a95a | 2020-11-23 13:34:56 +0100 | [diff] [blame] | 18 | select CPU_INTEL_HASWELL |
Duncan Laurie | f059b24 | 2015-01-15 15:42:43 -0800 | [diff] [blame] | 19 | select MRC_SETTINGS_PROTECT |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 20 | select HAVE_SMI_HANDLER |
Angel Pons | dd558fd | 2020-10-13 20:49:23 +0200 | [diff] [blame] | 21 | select SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS |
Patrick Rudolph | 45022ae | 2018-10-01 19:17:11 +0200 | [diff] [blame] | 22 | select SOUTHBRIDGE_INTEL_COMMON_RESET |
Arthur Heymans | 2abbe46 | 2019-06-04 14:12:01 +0200 | [diff] [blame] | 23 | select SOUTHBRIDGE_INTEL_COMMON_RTC |
Kyösti Mälkki | d1c69c6 | 2020-01-02 18:03:24 +0200 | [diff] [blame] | 24 | select SOUTHBRIDGE_INTEL_COMMON_SMBUS |
Arthur Heymans | 47a6603 | 2019-10-25 23:43:14 +0200 | [diff] [blame] | 25 | select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9 |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 26 | select HAVE_USBDEBUG |
| 27 | select IOAPIC |
Angel Pons | 3f0a95a | 2020-11-23 13:34:56 +0100 | [diff] [blame] | 28 | select INTEL_LYNXPOINT_LP |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 29 | select REG_SCRIPT |
Aaron Durbin | 16246ea | 2016-08-05 21:23:37 -0500 | [diff] [blame] | 30 | select RTC |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 31 | select SPI_FLASH |
Stefan Reinauer | 9616f3c | 2015-04-29 10:45:22 -0700 | [diff] [blame] | 32 | select SOC_INTEL_COMMON |
Stefan Tauner | ef8b957 | 2018-09-06 00:34:28 +0200 | [diff] [blame] | 33 | select INTEL_DESCRIPTOR_MODE_CAPABLE |
Angel Pons | 12d48cd | 2020-10-03 12:22:04 +0200 | [diff] [blame] | 34 | select HAVE_EM100PRO_SPI_CONSOLE_SUPPORT |
Matt DeVillier | 773488f | 2017-10-18 12:27:25 -0500 | [diff] [blame] | 35 | select INTEL_GMA_ACPI |
Nico Huber | 9faae2b | 2018-11-14 00:00:35 +0100 | [diff] [blame] | 36 | select HAVE_POWER_STATE_AFTER_FAILURE |
| 37 | select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 38 | |
Youness Alaoui | b191c9f | 2017-05-08 15:22:03 -0400 | [diff] [blame] | 39 | config PCIEXP_ASPM |
| 40 | bool |
| 41 | default y |
| 42 | |
Youness Alaoui | 7161678 | 2018-05-04 15:34:06 -0400 | [diff] [blame] | 43 | config PCIEXP_AER |
| 44 | bool |
| 45 | default y |
| 46 | |
Youness Alaoui | b191c9f | 2017-05-08 15:22:03 -0400 | [diff] [blame] | 47 | config PCIEXP_COMMON_CLOCK |
| 48 | bool |
| 49 | default y |
| 50 | |
| 51 | config PCIEXP_CLK_PM |
| 52 | bool |
| 53 | default y |
| 54 | |
| 55 | config PCIEXP_L1_SUB_STATE |
| 56 | bool |
| 57 | default y |
| 58 | |
Arthur Heymans | 4d56a06 | 2018-12-22 16:11:52 +0100 | [diff] [blame] | 59 | config BROADWELL_VBOOT_IN_BOOTBLOCK |
| 60 | depends on VBOOT |
| 61 | bool "Start verstage in bootblock" |
| 62 | default y |
| 63 | select VBOOT_STARTS_IN_BOOTBLOCK |
| 64 | select VBOOT_SEPARATE_VERSTAGE |
| 65 | help |
| 66 | Broadwell can either start verstage in a separate stage |
| 67 | right after the bootblock has run or it can start it |
| 68 | after romstage for compatibility reasons. |
| 69 | Broadwell however uses a mrc.bin to initialse memory which |
| 70 | needs to be located at a fixed offset. Therefore even with |
| 71 | a separate verstage starting after the bootblock that same |
| 72 | binary is used meaning a jump is made from RW to the RO region |
| 73 | and back to the RW region after the binary is done. |
| 74 | |
Julius Werner | 1210b41 | 2017-03-27 19:26:32 -0700 | [diff] [blame] | 75 | config VBOOT |
Joel Kitching | 6672bd8 | 2019-04-10 16:06:21 +0800 | [diff] [blame] | 76 | select VBOOT_MUST_REQUEST_DISPLAY |
Arthur Heymans | 4d56a06 | 2018-12-22 16:11:52 +0100 | [diff] [blame] | 77 | select VBOOT_STARTS_IN_ROMSTAGE if !BROADWELL_VBOOT_IN_BOOTBLOCK |
Julius Werner | 1210b41 | 2017-03-27 19:26:32 -0700 | [diff] [blame] | 78 | |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 79 | config MMCONF_BASE_ADDRESS |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 80 | default 0xf0000000 |
| 81 | |
Angel Pons | 9debbd6 | 2021-01-28 12:42:53 +0100 | [diff] [blame] | 82 | config MMCONF_BUS_NUMBER |
| 83 | default 64 |
| 84 | |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 85 | config VGA_BIOS_ID |
| 86 | string |
| 87 | default "8086,0406" |
| 88 | |
Angel Pons | c715dc8 | 2021-01-31 00:33:04 +0100 | [diff] [blame^] | 89 | config FIXED_MCHBAR_MMIO_BASE |
| 90 | default 0xfed10000 |
| 91 | |
| 92 | config FIXED_DMIBAR_MMIO_BASE |
| 93 | default 0xfed18000 |
| 94 | |
| 95 | config FIXED_EPBAR_MMIO_BASE |
| 96 | default 0xfed19000 |
| 97 | |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 98 | config DCACHE_RAM_BASE |
| 99 | hex |
| 100 | default 0xff7c0000 |
| 101 | |
| 102 | config DCACHE_RAM_SIZE |
| 103 | hex |
| 104 | default 0x10000 |
| 105 | help |
| 106 | The size of the cache-as-ram region required during bootblock |
| 107 | and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE |
| 108 | must add up to a power of 2. |
| 109 | |
| 110 | config DCACHE_RAM_MRC_VAR_SIZE |
| 111 | hex |
| 112 | default 0x30000 |
| 113 | help |
| 114 | The amount of cache-as-ram region required by the reference code. |
| 115 | |
Arthur Heymans | 5bb15f1 | 2018-12-22 16:02:25 +0100 | [diff] [blame] | 116 | config DCACHE_BSP_STACK_SIZE |
| 117 | hex |
| 118 | default 0x2000 |
| 119 | help |
| 120 | The amount of anticipated stack usage in CAR by bootblock and |
| 121 | other stages. |
| 122 | |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 123 | config HAVE_MRC |
| 124 | bool "Add a Memory Reference Code binary" |
| 125 | help |
| 126 | Select this option to add a Memory Reference Code binary to |
| 127 | the resulting coreboot image. |
| 128 | |
| 129 | Note: Without this binary coreboot will not work |
| 130 | |
| 131 | if HAVE_MRC |
| 132 | |
| 133 | config MRC_FILE |
| 134 | string "Intel Memory Reference Code path and filename" |
| 135 | depends on HAVE_MRC |
| 136 | default "mrc.bin" |
| 137 | help |
| 138 | The filename of the file to use as Memory Reference Code binary. |
| 139 | |
| 140 | config MRC_BIN_ADDRESS |
| 141 | hex |
| 142 | default 0xfffa0000 |
| 143 | |
Arthur Heymans | 4d56a06 | 2018-12-22 16:11:52 +0100 | [diff] [blame] | 144 | # The UEFI System Agent binary needs to be at a fixed offset in the flash |
| 145 | # and can therefore only reside in the COREBOOT fmap region |
| 146 | config RO_REGION_ONLY |
| 147 | string |
| 148 | depends on VBOOT |
| 149 | default "mrc.bin" |
| 150 | |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 151 | endif # HAVE_MRC |
| 152 | |
Duncan Laurie | 6168027 | 2014-05-05 12:42:35 -0500 | [diff] [blame] | 153 | config INTEL_PCH_UART_CONSOLE |
| 154 | bool "Use Serial IO UART for console" |
| 155 | default n |
Martin Roth | df02c33 | 2015-07-01 23:09:42 -0600 | [diff] [blame] | 156 | select DRIVERS_UART_8250MEM |
Duncan Laurie | 6168027 | 2014-05-05 12:42:35 -0500 | [diff] [blame] | 157 | |
| 158 | config INTEL_PCH_UART_CONSOLE_NUMBER |
| 159 | hex "Serial IO UART number to use for console" |
Martin Roth | 3b87812 | 2016-09-30 14:43:01 -0600 | [diff] [blame] | 160 | default 0x0 |
Duncan Laurie | 6168027 | 2014-05-05 12:42:35 -0500 | [diff] [blame] | 161 | depends on INTEL_PCH_UART_CONSOLE |
| 162 | |
| 163 | config TTYS0_BASE |
| 164 | hex |
| 165 | default 0xd6000000 |
| 166 | depends on INTEL_PCH_UART_CONSOLE |
| 167 | |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 168 | config EHCI_BAR |
| 169 | hex |
| 170 | default 0xd8000000 |
| 171 | |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 172 | config SERIRQ_CONTINUOUS_MODE |
| 173 | bool |
| 174 | default y |
| 175 | help |
| 176 | If you set this option to y, the serial IRQ machine will be |
| 177 | operated in continuous mode. |
Patrick Georgi | e6e9493 | 2015-06-22 22:26:45 +0200 | [diff] [blame] | 178 | |
| 179 | config HAVE_REFCODE_BLOB |
| 180 | depends on ARCH_X86 |
| 181 | bool "An external reference code blob should be put into cbfs." |
| 182 | default n |
| 183 | help |
| 184 | The reference code blob will be placed into cbfs. |
| 185 | |
| 186 | if HAVE_REFCODE_BLOB |
| 187 | |
| 188 | config REFCODE_BLOB_FILE |
| 189 | string "Path and filename to reference code blob." |
| 190 | default "refcode.elf" |
| 191 | help |
| 192 | The path and filename to the file to be added to cbfs. |
| 193 | |
| 194 | endif # HAVE_REFCODE_BLOB |
| 195 | |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 196 | endif |