Angel Pons | 4b42983 | 2020-04-02 23:48:50 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 2 | |
| 3 | #define __SIMPLE_DEVICE__ |
| 4 | |
Damien Zammit | 5680faf | 2016-01-22 22:12:30 +1100 | [diff] [blame] | 5 | #include <cbmem.h> |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 6 | #include <commonlib/helpers.h> |
| 7 | #include <stdint.h> |
Kyösti Mälkki | a963acd | 2019-08-16 20:34:25 +0300 | [diff] [blame] | 8 | #include <arch/romstage.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 9 | #include <device/pci_ops.h> |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 10 | #include <device/pci_def.h> |
| 11 | #include <console/console.h> |
Kyösti Mälkki | 823020d | 2016-07-22 22:53:19 +0300 | [diff] [blame] | 12 | #include <cpu/x86/mtrr.h> |
Kyösti Mälkki | d53fd70 | 2019-08-14 06:25:55 +0300 | [diff] [blame] | 13 | #include <cpu/x86/smm.h> |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 14 | #include <northbridge/intel/x4x/x4x.h> |
Kyösti Mälkki | 823020d | 2016-07-22 22:53:19 +0300 | [diff] [blame] | 15 | #include <program_loading.h> |
Kyösti Mälkki | f091f4d | 2019-08-14 03:49:21 +0300 | [diff] [blame] | 16 | #include <cpu/intel/smm_reloc.h> |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 17 | |
| 18 | /** Decodes used Graphics Mode Select (GMS) to kilobytes. */ |
| 19 | u32 decode_igd_memory_size(const u32 gms) |
| 20 | { |
Arthur Heymans | 27f94ee | 2016-06-18 21:08:58 +0200 | [diff] [blame] | 21 | static const u16 ggc2uma[] = { 0, 1, 4, 8, 16, |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 22 | 32, 48, 64, 128, 256, 96, 160, 224, 352 }; |
| 23 | |
Jacob Garber | f74f6cb | 2019-04-08 17:54:35 -0600 | [diff] [blame] | 24 | if (gms >= ARRAY_SIZE(ggc2uma)) |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 25 | die("Bad Graphics Mode Select (GMS) setting.\n"); |
| 26 | |
| 27 | return ggc2uma[gms] << 10; |
| 28 | } |
| 29 | |
| 30 | /** Decodes used GTT Graphics Memory Size (GGMS) to kilobytes. */ |
| 31 | u32 decode_igd_gtt_size(const u32 gsm) |
| 32 | { |
| 33 | static const u8 ggc2gtt[] = { 0, 1, 0, 2, 0, 0, 0, 0, 0, 2, 3, 4}; |
| 34 | |
Jacob Garber | f74f6cb | 2019-04-08 17:54:35 -0600 | [diff] [blame] | 35 | if (gsm >= ARRAY_SIZE(ggc2gtt)) |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 36 | die("Bad GTT Graphics Memory Size (GGMS) setting.\n"); |
| 37 | |
| 38 | return ggc2gtt[gsm] << 10; |
| 39 | } |
| 40 | |
Arthur Heymans | 4c65bfc | 2018-04-10 13:34:24 +0200 | [diff] [blame] | 41 | /** Decodes used TSEG size to bytes. */ |
| 42 | u32 decode_tseg_size(const u32 esmramc) |
| 43 | { |
| 44 | if (!(esmramc & 1)) |
| 45 | return 0; |
| 46 | |
| 47 | switch ((esmramc >> 1) & 3) { |
| 48 | case 0: |
| 49 | return 1 << 20; |
| 50 | case 1: |
| 51 | return 2 << 20; |
| 52 | case 2: |
| 53 | return 8 << 20; |
| 54 | case 3: |
| 55 | default: |
| 56 | die("Bad TSEG setting.\n"); |
| 57 | } |
| 58 | } |
| 59 | |
Angel Pons | ecec947 | 2020-08-03 15:44:27 +0200 | [diff] [blame] | 60 | int decode_pcie_bar(u32 *const base, u32 *const len) |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 61 | { |
| 62 | *base = 0; |
| 63 | *len = 0; |
Angel Pons | 8f917b1 | 2020-08-03 15:53:20 +0200 | [diff] [blame] | 64 | |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 65 | const struct { |
| 66 | u16 num_buses; |
| 67 | u32 addr_mask; |
| 68 | } busmask[] = { |
| 69 | {256, 0xf0000000}, |
| 70 | {128, 0xf8000000}, |
| 71 | {64, 0xfc000000}, |
| 72 | {0, 0}, |
| 73 | }; |
| 74 | |
Angel Pons | 8f917b1 | 2020-08-03 15:53:20 +0200 | [diff] [blame] | 75 | const u32 pciexbar_reg = pci_read_config32(PCI_DEV(0, 0, 0), D0F0_PCIEXBAR_LO); |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 76 | |
| 77 | if (!(pciexbar_reg & 1)) { |
| 78 | printk(BIOS_WARNING, "WARNING: MMCONF not set\n"); |
| 79 | return 0; |
| 80 | } |
| 81 | |
Angel Pons | 8f917b1 | 2020-08-03 15:53:20 +0200 | [diff] [blame] | 82 | const u32 index = (pciexbar_reg >> 1) & 3; |
| 83 | const u32 pciexbar = pciexbar_reg & busmask[index].addr_mask; |
| 84 | const int max_buses = busmask[index].num_buses; |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 85 | |
| 86 | if (!pciexbar) { |
| 87 | printk(BIOS_WARNING, "WARNING: pciexbar invalid\n"); |
| 88 | return 0; |
| 89 | } |
| 90 | |
| 91 | *base = pciexbar; |
| 92 | *len = max_buses << 20; |
| 93 | return 1; |
| 94 | } |
Damien Zammit | 5680faf | 2016-01-22 22:12:30 +1100 | [diff] [blame] | 95 | |
Kyösti Mälkki | d53fd70 | 2019-08-14 06:25:55 +0300 | [diff] [blame] | 96 | static size_t northbridge_get_tseg_size(void) |
Arthur Heymans | 4c65bfc | 2018-04-10 13:34:24 +0200 | [diff] [blame] | 97 | { |
| 98 | const u8 esmramc = pci_read_config8(PCI_DEV(0, 0, 0), D0F0_ESMRAMC); |
| 99 | return decode_tseg_size(esmramc); |
| 100 | } |
| 101 | |
Kyösti Mälkki | d53fd70 | 2019-08-14 06:25:55 +0300 | [diff] [blame] | 102 | static uintptr_t northbridge_get_tseg_base(void) |
Arthur Heymans | 4c65bfc | 2018-04-10 13:34:24 +0200 | [diff] [blame] | 103 | { |
| 104 | return pci_read_config32(PCI_DEV(0, 0, 0), D0F0_TSEG); |
| 105 | } |
| 106 | |
| 107 | |
Kyösti Mälkki | 811932a | 2016-07-22 22:53:19 +0300 | [diff] [blame] | 108 | /* Depending of UMA and TSEG configuration, TSEG might start at any |
Elyes HAOUAS | 64f6b71 | 2018-08-07 12:16:56 +0200 | [diff] [blame] | 109 | * 1 MiB alignment. As this may cause very greedy MTRR setup, push |
Kyösti Mälkki | 811932a | 2016-07-22 22:53:19 +0300 | [diff] [blame] | 110 | * CBMEM top downwards to 4 MiB boundary. |
| 111 | */ |
Arthur Heymans | 340e4b8 | 2019-10-23 17:25:58 +0200 | [diff] [blame] | 112 | void *cbmem_top_chipset(void) |
Damien Zammit | 5680faf | 2016-01-22 22:12:30 +1100 | [diff] [blame] | 113 | { |
Arthur Heymans | 4c65bfc | 2018-04-10 13:34:24 +0200 | [diff] [blame] | 114 | uintptr_t top_of_ram = ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB); |
Kyösti Mälkki | 811932a | 2016-07-22 22:53:19 +0300 | [diff] [blame] | 115 | return (void *) top_of_ram; |
Damien Zammit | 5680faf | 2016-01-22 22:12:30 +1100 | [diff] [blame] | 116 | } |
Kyösti Mälkki | a4ffe9d | 2016-06-27 13:24:11 +0300 | [diff] [blame] | 117 | |
Kyösti Mälkki | d53fd70 | 2019-08-14 06:25:55 +0300 | [diff] [blame] | 118 | void smm_region(uintptr_t *start, size_t *size) |
Kyösti Mälkki | aba8fb1 | 2019-08-02 06:11:28 +0300 | [diff] [blame] | 119 | { |
Kyösti Mälkki | d53fd70 | 2019-08-14 06:25:55 +0300 | [diff] [blame] | 120 | *start = northbridge_get_tseg_base(); |
| 121 | *size = northbridge_get_tseg_size(); |
Kyösti Mälkki | aba8fb1 | 2019-08-02 06:11:28 +0300 | [diff] [blame] | 122 | } |
| 123 | |
Kyösti Mälkki | 5bc641a | 2019-08-09 09:37:49 +0300 | [diff] [blame] | 124 | void fill_postcar_frame(struct postcar_frame *pcf) |
Kyösti Mälkki | a4ffe9d | 2016-06-27 13:24:11 +0300 | [diff] [blame] | 125 | { |
Kyösti Mälkki | 823020d | 2016-07-22 22:53:19 +0300 | [diff] [blame] | 126 | uintptr_t top_of_ram; |
| 127 | |
Elyes HAOUAS | ef90609 | 2020-02-20 19:41:17 +0100 | [diff] [blame] | 128 | /* Cache 8 MiB region below the top of RAM and 2 MiB above top of |
| 129 | * RAM to cover both cbmem as the TSEG region. |
Kyösti Mälkki | 823020d | 2016-07-22 22:53:19 +0300 | [diff] [blame] | 130 | */ |
| 131 | top_of_ram = (uintptr_t)cbmem_top(); |
Kyösti Mälkki | 5bc641a | 2019-08-09 09:37:49 +0300 | [diff] [blame] | 132 | postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB, |
Arthur Heymans | 4c65bfc | 2018-04-10 13:34:24 +0200 | [diff] [blame] | 133 | MTRR_TYPE_WRBACK); |
Kyösti Mälkki | 5bc641a | 2019-08-09 09:37:49 +0300 | [diff] [blame] | 134 | postcar_frame_add_mtrr(pcf, northbridge_get_tseg_base(), |
Arthur Heymans | 4c65bfc | 2018-04-10 13:34:24 +0200 | [diff] [blame] | 135 | northbridge_get_tseg_size(), MTRR_TYPE_WRBACK); |
Kyösti Mälkki | a4ffe9d | 2016-06-27 13:24:11 +0300 | [diff] [blame] | 136 | } |