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Michael Niewöhner0a6c62f2019-09-18 16:31:50 +02001chip soc/intel/skylake
2
Michael Niewöhner0a6c62f2019-09-18 16:31:50 +02003 # FSP Configuration
Michael Niewöhner0a6c62f2019-09-18 16:31:50 +02004 register "SkipExtGfxScan" = "1"
Michael Niewöhner0a6c62f2019-09-18 16:31:50 +02005
Michael Niewöhner0a6c62f2019-09-18 16:31:50 +02006
Michael Niewöhner1b79b862019-10-20 00:01:58 +02007 # Enabling SLP_S0, SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch
Felix Singer743242b2023-06-16 01:33:25 +02008 register "s0ix_enable" = true
Michael Niewöhner0a6c62f2019-09-18 16:31:50 +02009 register "PmConfigSlpS3MinAssert" = "SLP_S3_MIN_ASSERT_50MS"
10 register "PmConfigSlpS4MinAssert" = "SLP_S4_MIN_ASSERT_4S"
11 register "PmConfigSlpSusMinAssert" = "SLP_SUS_MIN_ASSERT_4S"
12 register "PmConfigSlpAMinAssert" = "SLP_A_MIN_ASSERT_2S"
13
Michael Niewöhner0a6c62f2019-09-18 16:31:50 +020014 device domain 0 on
Felix Singera03999b2023-10-23 09:01:05 +020015 device ref sa_thermal on end
16 device ref south_xhci on end
17 device ref thermal on end
18 device ref heci1 on end
Felix Singerdf7de392024-06-23 04:59:03 +020019 device ref sata on
20 register "SataSalpSupport" = "1"
21 register "SataPortsEnable" = "{
22 [0] = 1,
23 [1] = 1,
24 [2] = 1,
25 [3] = 1,
26 [4] = 1,
27 [5] = 1,
28 [6] = 1,
29 [7] = 1,
30 }"
31 end
Felix Singera03999b2023-10-23 09:01:05 +020032 device ref lpc_espi on
Felix Singer4b722032024-06-23 20:32:15 +020033 register "serirq_mode" = "SERIRQ_CONTINUOUS"
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Michael Niewöhner0a6c62f2019-09-18 16:31:50 +020035 chip superio/common
36 device pnp 2e.0 on end
37 end
38 chip drivers/pc80/tpm # TPM
39 device pnp 0c31.0 on end
40 end
41 end
Felix Singera03999b2023-10-23 09:01:05 +020042 device ref smbus on end
43 device ref fast_spi on end
Michael Niewöhner0a6c62f2019-09-18 16:31:50 +020044 end
45end