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Michael Niewöhner0a6c62f2019-09-18 16:31:50 +02001chip soc/intel/skylake
2
Michael Niewöhner0a6c62f2019-09-18 16:31:50 +02003 # FSP Configuration
Michael Niewöhner0a6c62f2019-09-18 16:31:50 +02004 register "SkipExtGfxScan" = "1"
Michael Niewöhner0a6c62f2019-09-18 16:31:50 +02005
Michael Niewöhner0a6c62f2019-09-18 16:31:50 +02006
Michael Niewöhner0a6c62f2019-09-18 16:31:50 +02007 # LPC
8 register "serirq_mode" = "SERIRQ_CONTINUOUS"
9
Michael Niewöhner1b79b862019-10-20 00:01:58 +020010 # Enabling SLP_S0, SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch
Felix Singer743242b2023-06-16 01:33:25 +020011 register "s0ix_enable" = true
Michael Niewöhner0a6c62f2019-09-18 16:31:50 +020012 register "PmConfigSlpS3MinAssert" = "SLP_S3_MIN_ASSERT_50MS"
13 register "PmConfigSlpS4MinAssert" = "SLP_S4_MIN_ASSERT_4S"
14 register "PmConfigSlpSusMinAssert" = "SLP_SUS_MIN_ASSERT_4S"
15 register "PmConfigSlpAMinAssert" = "SLP_A_MIN_ASSERT_2S"
16
Michael Niewöhner0a6c62f2019-09-18 16:31:50 +020017 device domain 0 on
Felix Singera03999b2023-10-23 09:01:05 +020018 device ref sa_thermal on end
19 device ref south_xhci on end
20 device ref thermal on end
21 device ref heci1 on end
Felix Singerdf7de392024-06-23 04:59:03 +020022 device ref sata on
23 register "SataSalpSupport" = "1"
24 register "SataPortsEnable" = "{
25 [0] = 1,
26 [1] = 1,
27 [2] = 1,
28 [3] = 1,
29 [4] = 1,
30 [5] = 1,
31 [6] = 1,
32 [7] = 1,
33 }"
34 end
Felix Singera03999b2023-10-23 09:01:05 +020035 device ref lpc_espi on
Michael Niewöhner0a6c62f2019-09-18 16:31:50 +020036 chip superio/common
37 device pnp 2e.0 on end
38 end
39 chip drivers/pc80/tpm # TPM
40 device pnp 0c31.0 on end
41 end
42 end
Felix Singera03999b2023-10-23 09:01:05 +020043 device ref smbus on end
44 device ref fast_spi on end
Michael Niewöhner0a6c62f2019-09-18 16:31:50 +020045 end
46end