Michael Niewöhner | 0a6c62f | 2019-09-18 16:31:50 +0200 | [diff] [blame] | 1 | chip soc/intel/skylake |
| 2 | |
| 3 | # Enable deep Sx states |
| 4 | register "deep_s5_enable_ac" = "0" |
| 5 | register "deep_s5_enable_dc" = "0" |
| 6 | register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" |
| 7 | |
| 8 | # Enable "Intel Speed Shift Technology" |
| 9 | register "speed_shift_enable" = "1" |
| 10 | |
| 11 | # FSP Configuration |
| 12 | register "SmbusEnable" = "1" |
| 13 | register "ScsEmmcEnabled" = "0" |
| 14 | register "ScsEmmcHs400Enabled" = "0" |
| 15 | register "ScsSdCardEnabled" = "0" |
| 16 | register "SkipExtGfxScan" = "1" |
| 17 | register "Device4Enable" = "1" |
| 18 | register "SaGv" = "SaGv_Disabled" |
| 19 | |
Patrick Rudolph | 05bad43 | 2019-09-26 10:30:22 +0200 | [diff] [blame] | 20 | # Enable SGX |
| 21 | register "sgx_enable" = "1" |
Michael Niewöhner | 0a6c62f | 2019-09-18 16:31:50 +0200 | [diff] [blame] | 22 | register "PrmrrSize" = "128 * MiB" |
| 23 | |
| 24 | register "pirqa_routing" = "PCH_IRQ11" |
| 25 | register "pirqb_routing" = "PCH_IRQ10" |
| 26 | register "pirqc_routing" = "PCH_IRQ11" |
| 27 | register "pirqd_routing" = "PCH_IRQ11" |
| 28 | register "pirqe_routing" = "PCH_IRQ11" |
| 29 | register "pirqf_routing" = "PCH_IRQ11" |
| 30 | register "pirqg_routing" = "PCH_IRQ11" |
| 31 | register "pirqh_routing" = "PCH_IRQ11" |
| 32 | |
| 33 | # SATA configuration |
| 34 | register "SataMode" = "KBLFSP_SATA_MODE_AHCI" |
| 35 | register "EnableSata" = "1" |
| 36 | register "SataSalpSupport" = "1" |
| 37 | register "SataPortsEnable" = "{ \ |
| 38 | [0] = 1, \ |
| 39 | [1] = 1, \ |
| 40 | [2] = 1, \ |
| 41 | [3] = 1, \ |
| 42 | [4] = 1, \ |
| 43 | [5] = 1, \ |
| 44 | [6] = 1, \ |
| 45 | [7] = 1, \ |
| 46 | }" |
| 47 | |
| 48 | register "SataPortsDevSlp" = "{\ |
| 49 | [0] = 0, \ |
| 50 | [1] = 0, \ |
| 51 | [2] = 0, \ |
| 52 | [3] = 0, \ |
| 53 | [4] = 0, \ |
| 54 | [5] = 0, \ |
| 55 | [6] = 0, \ |
| 56 | [7] = 0, \ |
| 57 | }" |
| 58 | |
| 59 | # superspeed_inter-chip_supplement (SSIC) disabled |
| 60 | register "SsicPortEnable" = "0" |
| 61 | |
Michael Niewöhner | 33533c0 | 2019-10-19 21:15:15 +0200 | [diff] [blame] | 62 | # USB |
| 63 | register "usb2_ports" = "{ |
| 64 | [0] = USB2_PORT_EMPTY, |
| 65 | [1] = USB2_PORT_EMPTY, |
| 66 | [2] = USB2_PORT_EMPTY, |
| 67 | [3] = USB2_PORT_EMPTY, |
| 68 | [4] = USB2_PORT_EMPTY, |
| 69 | [5] = USB2_PORT_EMPTY, |
| 70 | [6] = USB2_PORT_EMPTY, |
| 71 | [7] = USB2_PORT_EMPTY, |
| 72 | [8] = USB2_PORT_EMPTY, |
| 73 | [9] = USB2_PORT_EMPTY, |
| 74 | [10] = USB2_PORT_EMPTY, |
| 75 | [11] = USB2_PORT_EMPTY, |
| 76 | [12] = USB2_PORT_EMPTY, |
| 77 | [13] = USB2_PORT_EMPTY, |
| 78 | }" |
| 79 | register "usb3_ports" = "{ |
| 80 | [0] = USB3_PORT_EMPTY, |
| 81 | [1] = USB3_PORT_EMPTY, |
| 82 | [2] = USB3_PORT_EMPTY, |
| 83 | [3] = USB3_PORT_EMPTY, |
| 84 | [4] = USB3_PORT_EMPTY, |
| 85 | [5] = USB3_PORT_EMPTY, |
| 86 | [6] = USB3_PORT_EMPTY, |
| 87 | [7] = USB3_PORT_EMPTY, |
| 88 | [8] = USB3_PORT_EMPTY, |
| 89 | [9] = USB3_PORT_EMPTY, |
| 90 | }" |
Michael Niewöhner | 0a6c62f | 2019-09-18 16:31:50 +0200 | [diff] [blame] | 91 | |
| 92 | # LPC |
| 93 | register "serirq_mode" = "SERIRQ_CONTINUOUS" |
| 94 | |
Michael Niewöhner | 1b79b86 | 2019-10-20 00:01:58 +0200 | [diff] [blame^] | 95 | # Enabling SLP_S0, SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch |
| 96 | register "s0ix_enable" = "1" |
Michael Niewöhner | 0a6c62f | 2019-09-18 16:31:50 +0200 | [diff] [blame] | 97 | register "PmConfigSlpS3MinAssert" = "SLP_S3_MIN_ASSERT_50MS" |
| 98 | register "PmConfigSlpS4MinAssert" = "SLP_S4_MIN_ASSERT_4S" |
| 99 | register "PmConfigSlpSusMinAssert" = "SLP_SUS_MIN_ASSERT_4S" |
| 100 | register "PmConfigSlpAMinAssert" = "SLP_A_MIN_ASSERT_2S" |
| 101 | |
| 102 | # VR Settings Configuration for 4 Domains |
| 103 | # ICC_MAX = 0 (Auto) |
| 104 | # Voltage limit 1.52V (not used on KBL-S and KBL-DT) |
| 105 | # Disable PS4 powerstate in S0ix, thus no package C10 support |
| 106 | # psi threshold is using FSP default values |
| 107 | register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ |
| 108 | .vr_config_enable = 1, \ |
| 109 | .psi1threshold = VR_CFG_AMP(20), |
| 110 | .psi2threshold = VR_CFG_AMP(5), |
| 111 | .psi3threshold = VR_CFG_AMP(1), |
| 112 | .psi3enable = 1, \ |
| 113 | .psi4enable = 0, \ |
| 114 | .imon_slope = 0x0, \ |
| 115 | .imon_offset = 0x0, \ |
| 116 | .icc_max = 0, \ |
| 117 | .voltage_limit = 1520 \ |
| 118 | }" |
| 119 | |
| 120 | register "domain_vr_config[VR_IA_CORE]" = "{ |
| 121 | .vr_config_enable = 1, \ |
| 122 | .psi1threshold = VR_CFG_AMP(20), |
| 123 | .psi2threshold = VR_CFG_AMP(5), |
| 124 | .psi3threshold = VR_CFG_AMP(1), |
| 125 | .psi3enable = 1, \ |
| 126 | .psi4enable = 0, \ |
| 127 | .imon_slope = 0x0, \ |
| 128 | .imon_offset = 0x0, \ |
| 129 | .icc_max = 0, \ |
| 130 | .voltage_limit = 1520 \ |
| 131 | }" |
| 132 | |
| 133 | register "domain_vr_config[VR_GT_UNSLICED]" = "{ |
| 134 | .vr_config_enable = 1, \ |
| 135 | .psi1threshold = VR_CFG_AMP(20), |
| 136 | .psi2threshold = VR_CFG_AMP(5), |
| 137 | .psi3threshold = VR_CFG_AMP(1), |
| 138 | .psi3enable = 1, \ |
| 139 | .psi4enable = 0, \ |
| 140 | .imon_slope = 0x0, \ |
| 141 | .imon_offset = 0x0, \ |
| 142 | .icc_max = 0 ,\ |
| 143 | .voltage_limit = 1520 \ |
| 144 | }" |
| 145 | |
| 146 | register "domain_vr_config[VR_GT_SLICED]" = "{ |
| 147 | .vr_config_enable = 1, \ |
| 148 | .psi1threshold = VR_CFG_AMP(20), |
| 149 | .psi2threshold = VR_CFG_AMP(5), |
| 150 | .psi3threshold = VR_CFG_AMP(1), |
| 151 | .psi3enable = 1, \ |
| 152 | .psi4enable = 0, \ |
| 153 | .imon_slope = 0x0, \ |
| 154 | .imon_offset = 0x0, \ |
| 155 | .icc_max = 0, \ |
| 156 | .voltage_limit = 1520 \ |
| 157 | }" |
| 158 | |
| 159 | # No extra VR mailbox command |
| 160 | register "SendVrMbxCmd" = "0" |
| 161 | |
| 162 | # Lock Down |
| 163 | register "common_soc_config" = "{ |
| 164 | .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, |
| 165 | }" |
| 166 | |
| 167 | device cpu_cluster 0 on |
| 168 | device lapic 0 on end |
| 169 | end |
| 170 | device domain 0 on |
| 171 | device pci 00.0 on end # Host Bridge |
| 172 | device pci 01.0 off end # CPU PCIe Port 10 (x16) |
| 173 | device pci 01.1 off end # CPU PCIe Port 11 (x8) |
| 174 | device pci 01.2 off end # CPU PCIe Port 12 (x4) |
| 175 | device pci 02.0 off end # Integrated Graphics Device (IGD) |
| 176 | device pci 04.0 on end # SA thermal subsystem |
| 177 | device pci 05.0 off end # Imaging Unit |
| 178 | device pci 08.0 off end # Gaussion Mixture Model (GMM) |
| 179 | device pci 13.0 off end # Integrated Sensor Hub |
| 180 | device pci 14.0 on end # USB xHCI |
| 181 | device pci 14.1 off end # USB xDCI (OTG) |
| 182 | device pci 14.2 on end # Thermal Subsystem |
| 183 | device pci 15.0 off end # I2C #0 |
| 184 | device pci 15.1 off end # I2C #1 |
| 185 | device pci 15.2 off end # I2C #2 |
| 186 | device pci 15.3 off end # I2C #3 |
| 187 | device pci 16.0 on end # Management Engine Interface 1 |
| 188 | device pci 16.1 off end # Management Engine Interface 2 |
| 189 | device pci 16.2 off end # Management Engine IDE-R |
| 190 | device pci 16.3 off end # Management Engine KT Redirection |
| 191 | device pci 16.4 off end # Management Engine Interface 3 |
| 192 | device pci 17.0 on end # SATA |
| 193 | device pci 19.0 off end # UART #2 |
| 194 | device pci 19.1 off end # I2C #5 |
| 195 | device pci 19.2 off end # I2C #4 |
| 196 | device pci 1b.0 off end # PCH PCIe Port 17 |
| 197 | device pci 1b.1 off end # PCH PCIe Port 18 |
| 198 | device pci 1b.2 off end # PCH PCIe Port 19 |
| 199 | device pci 1b.3 off end # PCH PCIe Port 20 |
| 200 | device pci 1c.0 off end # PCH PCIe Port 1 |
| 201 | device pci 1c.1 off end # PCH PCIe Port 2 |
| 202 | device pci 1c.2 off end # PCH PCIe Port 3 |
| 203 | device pci 1c.3 off end # PCH PCIe Port 4 |
| 204 | device pci 1c.4 off end # PCH PCIe Port 5 |
| 205 | device pci 1c.5 off end # PCH PCIe Port 6 |
| 206 | device pci 1c.6 off end # PCH PCIe Port 7 |
| 207 | device pci 1c.7 off end # PCH PCIe Port 8 |
| 208 | device pci 1d.0 off end # PCH PCIe Port 9 |
| 209 | device pci 1d.1 off end # PCH PCIe Port 10 |
| 210 | device pci 1d.2 off end # PCH PCIe Port 11 |
| 211 | device pci 1d.3 off end # PCH PCIe Port 12 |
| 212 | device pci 1d.4 off end # PCH PCIe Port 13 |
| 213 | device pci 1d.5 off end # PCH PCIe Port 14 |
| 214 | device pci 1d.6 off end # PCH PCIe Port 15 |
| 215 | device pci 1d.7 off end # PCH PCIe Port 16 |
| 216 | device pci 1e.0 off end # UART #0 |
| 217 | device pci 1e.1 off end # UART #1 |
| 218 | device pci 1e.2 off end # SPI #0 |
| 219 | device pci 1f.0 on # LPC Interface |
| 220 | chip superio/common |
| 221 | device pnp 2e.0 on end |
| 222 | end |
| 223 | chip drivers/pc80/tpm # TPM |
| 224 | device pnp 0c31.0 on end |
| 225 | end |
| 226 | end |
| 227 | device pci 1f.1 on end # P2SB |
| 228 | device pci 1f.2 on end # Power Management Controller |
| 229 | device pci 1f.3 off end # Intel HDA |
| 230 | device pci 1f.4 on end # SMBus |
| 231 | device pci 1f.5 on end # SPI Controller |
| 232 | device pci 1f.6 off end # GbE |
| 233 | device pci 1f.7 off end # Intel Trace Hub |
| 234 | end |
| 235 | end |