src/mainboard/supermicro/x11-lga1151-series/devicetree.cb

chip soc/intel/skylake

	# Enable deep Sx states
	register "deep_s5_enable_ac" = "0"
	register "deep_s5_enable_dc" = "0"
	register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"

	# Enable "Intel Speed Shift Technology"
	register "speed_shift_enable" = "1"

	# FSP Configuration
	register "SmbusEnable" = "1"
	register "ScsEmmcEnabled" = "0"
	register "ScsEmmcHs400Enabled" = "0"
	register "ScsSdCardEnabled" = "0"
	register "SkipExtGfxScan" = "1"
	register "Device4Enable" = "1"
	register "SaGv" = "SaGv_Disabled"

	# Enable SGX
	register "sgx_enable" = "1"
	register "PrmrrSize" = "128 * MiB"

	register "pirqa_routing" = "PCH_IRQ11"
	register "pirqb_routing" = "PCH_IRQ10"
	register "pirqc_routing" = "PCH_IRQ11"
	register "pirqd_routing" = "PCH_IRQ11"
	register "pirqe_routing" = "PCH_IRQ11"
	register "pirqf_routing" = "PCH_IRQ11"
	register "pirqg_routing" = "PCH_IRQ11"
	register "pirqh_routing" = "PCH_IRQ11"

	# SATA configuration
	register "SataMode" = "KBLFSP_SATA_MODE_AHCI"
	register "EnableSata" = "1"
	register "SataSalpSupport" = "1"
	register "SataPortsEnable" = "{ \
		[0]	= 1, \
		[1]	= 1, \
		[2]	= 1, \
		[3]	= 1, \
		[4]	= 1, \
		[5]	= 1, \
		[6]	= 1, \
		[7]	= 1, \
	}"

	register "SataPortsDevSlp" = "{\
		[0]	= 0, \
		[1]	= 0, \
		[2]	= 0, \
		[3]	= 0, \
		[4]	= 0, \
		[5]	= 0, \
		[6]	= 0, \
		[7]	= 0, \
	}"

	# superspeed_inter-chip_supplement (SSIC) disabled
	register "SsicPortEnable" = "0"

	# USB
	register "usb2_ports" = "{
		[0]	= USB2_PORT_EMPTY,
		[1]	= USB2_PORT_EMPTY,
		[2]	= USB2_PORT_EMPTY,
		[3]	= USB2_PORT_EMPTY,
		[4]	= USB2_PORT_EMPTY,
		[5]	= USB2_PORT_EMPTY,
		[6]	= USB2_PORT_EMPTY,
		[7]	= USB2_PORT_EMPTY,
		[8]	= USB2_PORT_EMPTY,
		[9]	= USB2_PORT_EMPTY,
		[10]	= USB2_PORT_EMPTY,
		[11]	= USB2_PORT_EMPTY,
		[12]	= USB2_PORT_EMPTY,
		[13]	= USB2_PORT_EMPTY,
	}"
	register "usb3_ports" = "{
		[0]	= USB3_PORT_EMPTY,
		[1]	= USB3_PORT_EMPTY,
		[2]	= USB3_PORT_EMPTY,
		[3]	= USB3_PORT_EMPTY,
		[4]	= USB3_PORT_EMPTY,
		[5]	= USB3_PORT_EMPTY,
		[6]	= USB3_PORT_EMPTY,
		[7]	= USB3_PORT_EMPTY,
		[8]	= USB3_PORT_EMPTY,
		[9]	= USB3_PORT_EMPTY,
	}"

	# LPC
	register "serirq_mode" = "SERIRQ_CONTINUOUS"

	# Enabling SLP_S0, SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch
	register "s0ix_enable"			= "1"
	register "PmConfigSlpS3MinAssert"	= "SLP_S3_MIN_ASSERT_50MS"
	register "PmConfigSlpS4MinAssert"	= "SLP_S4_MIN_ASSERT_4S"
	register "PmConfigSlpSusMinAssert"	= "SLP_SUS_MIN_ASSERT_4S"
	register "PmConfigSlpAMinAssert"	= "SLP_A_MIN_ASSERT_2S"

	# VR Settings Configuration for 4 Domains
	# ICC_MAX = 0 (Auto)
	# Voltage limit 1.52V (not used on KBL-S and KBL-DT)
	# Disable PS4 powerstate in S0ix, thus no package C10 support
	# psi threshold is using FSP default values
	register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
		.vr_config_enable = 1, \
		.psi1threshold = VR_CFG_AMP(20),
		.psi2threshold = VR_CFG_AMP(5),
		.psi3threshold = VR_CFG_AMP(1),
		.psi3enable = 1, \
		.psi4enable = 0, \
		.imon_slope = 0x0, \
		.imon_offset = 0x0, \
		.icc_max = 0, \
		.voltage_limit = 1520 \
	}"

	register "domain_vr_config[VR_IA_CORE]" = "{
		.vr_config_enable = 1, \
		.psi1threshold = VR_CFG_AMP(20),
		.psi2threshold = VR_CFG_AMP(5),
		.psi3threshold = VR_CFG_AMP(1),
		.psi3enable = 1, \
		.psi4enable = 0, \
		.imon_slope = 0x0, \
		.imon_offset = 0x0, \
		.icc_max = 0, \
		.voltage_limit = 1520 \
	}"

	register "domain_vr_config[VR_GT_UNSLICED]" = "{
		.vr_config_enable = 1, \
		.psi1threshold = VR_CFG_AMP(20),
		.psi2threshold = VR_CFG_AMP(5),
		.psi3threshold = VR_CFG_AMP(1),
		.psi3enable = 1, \
		.psi4enable = 0, \
		.imon_slope = 0x0, \
		.imon_offset = 0x0, \
		.icc_max = 0 ,\
		.voltage_limit = 1520 \
	}"

	register "domain_vr_config[VR_GT_SLICED]" = "{
		.vr_config_enable = 1, \
		.psi1threshold = VR_CFG_AMP(20),
		.psi2threshold = VR_CFG_AMP(5),
		.psi3threshold = VR_CFG_AMP(1),
		.psi3enable = 1, \
		.psi4enable = 0, \
		.imon_slope = 0x0, \
		.imon_offset = 0x0, \
		.icc_max = 0, \
		.voltage_limit = 1520 \
	}"

	# No extra VR mailbox command
	register "SendVrMbxCmd" = "0"

	# Lock Down
	register "common_soc_config" = "{
	.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
	}"

	device cpu_cluster 0 on
		device lapic 0 on end
	end
	device domain 0 on
		device pci 00.0 on  end	# Host Bridge
		device pci 01.0 off end	# CPU PCIe Port 10 (x16)
		device pci 01.1 off end	# CPU PCIe Port 11 (x8)
		device pci 01.2 off end	# CPU PCIe Port 12 (x4)
		device pci 02.0 off end	# Integrated Graphics Device (IGD)
		device pci 04.0 on  end	# SA thermal subsystem
		device pci 05.0 off end	# Imaging Unit
		device pci 08.0 off end	# Gaussion Mixture Model (GMM)
		device pci 13.0 off end	# Integrated Sensor Hub
		device pci 14.0 on  end	# USB xHCI
		device pci 14.1 off end	# USB xDCI (OTG)
		device pci 14.2 on  end	# Thermal Subsystem
		device pci 15.0 off end	# I2C #0
		device pci 15.1 off end	# I2C #1
		device pci 15.2 off end	# I2C #2
		device pci 15.3 off end	# I2C #3
		device pci 16.0 on  end	# Management Engine Interface 1
		device pci 16.1 off end	# Management Engine Interface 2
		device pci 16.2 off end	# Management Engine IDE-R
		device pci 16.3 off end	# Management Engine KT Redirection
		device pci 16.4 off end	# Management Engine Interface 3
		device pci 17.0 on  end	# SATA
		device pci 19.0 off end	# UART #2
		device pci 19.1 off end	# I2C #5
		device pci 19.2 off end	# I2C #4
		device pci 1b.0 off end	# PCH PCIe Port 17
		device pci 1b.1 off end	# PCH PCIe Port 18
		device pci 1b.2 off end	# PCH PCIe Port 19
		device pci 1b.3 off end	# PCH PCIe Port 20
		device pci 1c.0 off end	# PCH PCIe Port  1
		device pci 1c.1 off end	# PCH PCIe Port  2
		device pci 1c.2 off end	# PCH PCIe Port  3
		device pci 1c.3 off end	# PCH PCIe Port  4
		device pci 1c.4 off end	# PCH PCIe Port  5
		device pci 1c.5 off end	# PCH PCIe Port  6
		device pci 1c.6 off end	# PCH PCIe Port  7
		device pci 1c.7 off end	# PCH PCIe Port  8
		device pci 1d.0 off end	# PCH PCIe Port  9
		device pci 1d.1 off end	# PCH PCIe Port 10
		device pci 1d.2 off end	# PCH PCIe Port 11
		device pci 1d.3 off end	# PCH PCIe Port 12
		device pci 1d.4 off end	# PCH PCIe Port 13
		device pci 1d.5 off end	# PCH PCIe Port 14
		device pci 1d.6 off end	# PCH PCIe Port 15
		device pci 1d.7 off end	# PCH PCIe Port 16
		device pci 1e.0 off end	# UART #0
		device pci 1e.1 off end	# UART #1
		device pci 1e.2 off end	# SPI #0
		device pci 1f.0 on	# LPC Interface
			chip superio/common
				device pnp 2e.0 on  end
			end
			chip drivers/pc80/tpm	# TPM
				device pnp 0c31.0 on  end
			end
		end
		device pci 1f.1 on  end	# P2SB
		device pci 1f.2 on  end	# Power Management Controller
		device pci 1f.3 off end	# Intel HDA
		device pci 1f.4 on  end	# SMBus
		device pci 1f.5 on  end	# SPI Controller
		device pci 1f.6 off end	# GbE
		device pci 1f.7 off end	# Intel Trace Hub
	end
end