Youness Alaoui | 047475c | 2017-05-08 16:50:23 -0400 | [diff] [blame] | 1 | chip soc/intel/skylake |
| 2 | |
Benjamin Doron | ac08c81 | 2020-04-04 05:58:54 +0000 | [diff] [blame] | 3 | # IGD Displays |
| 4 | register "gfx" = "GMA_STATIC_DISPLAYS(0)" |
| 5 | |
Michael Niewöhner | 97e21d3 | 2020-12-28 00:49:33 +0100 | [diff] [blame] | 6 | register "panel_cfg" = "{ |
| 7 | .up_delay_ms = 200, |
| 8 | .down_delay_ms = 50, |
| 9 | .cycle_delay_ms = 500, |
| 10 | .backlight_on_delay_ms = 1, |
| 11 | .backlight_off_delay_ms = 200, |
| 12 | .backlight_pwm_hz = 200, |
| 13 | }" |
| 14 | |
Youness Alaoui | 047475c | 2017-05-08 16:50:23 -0400 | [diff] [blame] | 15 | register "deep_s3_enable_ac" = "0" |
| 16 | register "deep_s3_enable_dc" = "0" |
Youness Alaoui | c5b9658 | 2017-06-19 20:47:27 -0400 | [diff] [blame] | 17 | register "deep_s5_enable_ac" = "0" |
| 18 | register "deep_s5_enable_dc" = "0" |
Youness Alaoui | 047475c | 2017-05-08 16:50:23 -0400 | [diff] [blame] | 19 | register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" |
| 20 | |
Youness Alaoui | 0601f1e | 2018-02-09 18:44:45 -0500 | [diff] [blame] | 21 | register "eist_enable" = "1" |
Youness Alaoui | 0601f1e | 2018-02-09 18:44:45 -0500 | [diff] [blame] | 22 | |
Youness Alaoui | cb8f04d | 2018-03-02 16:12:04 -0500 | [diff] [blame] | 23 | # Set the Thermal Control Circuit (TCC) activaction value to 95C |
| 24 | # even though FSP integration guide says to set it to 100C for SKL-U |
| 25 | # (offset at 0), because when the TCC activates at 100C, the CPU |
| 26 | # will have already shut itself down from overheating protection. |
| 27 | register "tcc_offset" = "5" # TCC of 95C |
| 28 | |
Youness Alaoui | 047475c | 2017-05-08 16:50:23 -0400 | [diff] [blame] | 29 | # GPE configuration |
| 30 | # Note that GPE events called out in ASL code rely on this |
| 31 | # route. i.e. If this route changes then the affected GPE |
| 32 | # offset bits also need to be changed. |
Youness Alaoui | 34a30a6 | 2017-05-25 13:25:41 -0500 | [diff] [blame] | 33 | register "gpe0_dw0" = "GPP_C" |
Youness Alaoui | 047475c | 2017-05-08 16:50:23 -0400 | [diff] [blame] | 34 | register "gpe0_dw1" = "GPP_D" |
| 35 | register "gpe0_dw2" = "GPP_E" |
| 36 | |
Youness Alaoui | 3f42a26b | 2018-03-20 18:32:23 -0400 | [diff] [blame] | 37 | # Disable DPTF |
| 38 | register "dptf_enable" = "0" |
Youness Alaoui | 047475c | 2017-05-08 16:50:23 -0400 | [diff] [blame] | 39 | |
| 40 | # FSP Configuration |
Youness Alaoui | eacac20 | 2017-05-17 17:16:09 -0400 | [diff] [blame] | 41 | register "DspEnable" = "0" |
| 42 | register "IoBufferOwnership" = "0" |
Youness Alaoui | 047475c | 2017-05-08 16:50:23 -0400 | [diff] [blame] | 43 | register "SkipExtGfxScan" = "1" |
Angel Pons | 6fadde0 | 2021-04-04 16:11:53 +0200 | [diff] [blame] | 44 | register "SaGv" = "SaGv_Enabled" |
Elyes HAOUAS | b0f1988 | 2018-06-09 11:59:00 +0200 | [diff] [blame] | 45 | register "PmConfigSlpS3MinAssert" = "2" # 50ms |
| 46 | register "PmConfigSlpS4MinAssert" = "1" # 1s |
| 47 | register "PmConfigSlpSusMinAssert" = "3" # 500ms |
| 48 | register "PmConfigSlpAMinAssert" = "3" # 2s |
Youness Alaoui | 047475c | 2017-05-08 16:50:23 -0400 | [diff] [blame] | 49 | |
Nico Huber | 44e89af | 2019-02-23 19:24:51 +0100 | [diff] [blame] | 50 | # EC/KBC requires continuous mode |
| 51 | register "serirq_mode" = "SERIRQ_CONTINUOUS" |
| 52 | |
Matt DeVillier | fb1cd09 | 2017-06-22 15:54:07 -0400 | [diff] [blame] | 53 | # VR Settings Configuration for 4 Domains |
Youness Alaoui | 3f42a26b | 2018-03-20 18:32:23 -0400 | [diff] [blame] | 54 | #+----------------+-----------+-----------+-------------+----------+ |
| 55 | #| Domain/Setting | SA | IA | GT Unsliced | GT | |
| 56 | #+----------------+-----------+-----------+-------------+----------+ |
| 57 | #| Psi1Threshold | 20A | 20A | 20A | 20A | |
| 58 | #| Psi2Threshold | 4A | 5A | 5A | 5A | |
| 59 | #| Psi3Threshold | 1A | 1A | 1A | 1A | |
| 60 | #| Psi3Enable | 1 | 1 | 1 | 1 | |
| 61 | #| Psi4Enable | 1 | 1 | 1 | 1 | |
| 62 | #| ImonSlope | 0 | 0 | 0 | 0 | |
| 63 | #| ImonOffset | 0 | 0 | 0 | 0 | |
| 64 | #| IccMax | 7A | 34A | 35A | 35A | |
| 65 | #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | |
| 66 | #| AC LoadLine | 15 mOhm | 5.7 mOhm | 5.2 mOhm | 5.2 mOhm | |
| 67 | #| DC LoadLine | 14.3 mOhm | 4.83 mOhm | 4.2 mOhm | 4.2 mOhm | |
| 68 | #+----------------+-----------+-----------+-------------+----------+ |
Youness Alaoui | 047475c | 2017-05-08 16:50:23 -0400 | [diff] [blame] | 69 | register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ |
| 70 | .vr_config_enable = 1, |
| 71 | .psi1threshold = VR_CFG_AMP(20), |
| 72 | .psi2threshold = VR_CFG_AMP(4), |
| 73 | .psi3threshold = VR_CFG_AMP(1), |
| 74 | .psi3enable = 1, |
| 75 | .psi4enable = 1, |
| 76 | .imon_slope = 0x0, |
| 77 | .imon_offset = 0x0, |
| 78 | .icc_max = VR_CFG_AMP(7), |
| 79 | .voltage_limit = 1520, |
Youness Alaoui | 3f42a26b | 2018-03-20 18:32:23 -0400 | [diff] [blame] | 80 | .ac_loadline = 1500, |
| 81 | .dc_loadline = 1430, |
Youness Alaoui | 047475c | 2017-05-08 16:50:23 -0400 | [diff] [blame] | 82 | }" |
| 83 | |
| 84 | register "domain_vr_config[VR_IA_CORE]" = "{ |
| 85 | .vr_config_enable = 1, |
| 86 | .psi1threshold = VR_CFG_AMP(20), |
| 87 | .psi2threshold = VR_CFG_AMP(5), |
| 88 | .psi3threshold = VR_CFG_AMP(1), |
| 89 | .psi3enable = 1, |
| 90 | .psi4enable = 1, |
| 91 | .imon_slope = 0x0, |
| 92 | .imon_offset = 0x0, |
| 93 | .icc_max = VR_CFG_AMP(34), |
| 94 | .voltage_limit = 1520, |
Youness Alaoui | 3f42a26b | 2018-03-20 18:32:23 -0400 | [diff] [blame] | 95 | .ac_loadline = 570, |
| 96 | .dc_loadline = 483, |
Youness Alaoui | 047475c | 2017-05-08 16:50:23 -0400 | [diff] [blame] | 97 | }" |
| 98 | |
Youness Alaoui | 047475c | 2017-05-08 16:50:23 -0400 | [diff] [blame] | 99 | register "domain_vr_config[VR_GT_UNSLICED]" = "{ |
| 100 | .vr_config_enable = 1, |
| 101 | .psi1threshold = VR_CFG_AMP(20), |
| 102 | .psi2threshold = VR_CFG_AMP(5), |
| 103 | .psi3threshold = VR_CFG_AMP(1), |
| 104 | .psi3enable = 1, |
| 105 | .psi4enable = 1, |
| 106 | .imon_slope = 0x0, |
| 107 | .imon_offset = 0x0, |
| 108 | .icc_max = VR_CFG_AMP(35), |
| 109 | .voltage_limit = 1520, |
Youness Alaoui | 3f42a26b | 2018-03-20 18:32:23 -0400 | [diff] [blame] | 110 | .ac_loadline = 520, |
| 111 | .dc_loadline = 420, |
Youness Alaoui | 047475c | 2017-05-08 16:50:23 -0400 | [diff] [blame] | 112 | }" |
| 113 | |
| 114 | register "domain_vr_config[VR_GT_SLICED]" = "{ |
| 115 | .vr_config_enable = 1, |
| 116 | .psi1threshold = VR_CFG_AMP(20), |
| 117 | .psi2threshold = VR_CFG_AMP(5), |
| 118 | .psi3threshold = VR_CFG_AMP(1), |
| 119 | .psi3enable = 1, |
| 120 | .psi4enable = 1, |
| 121 | .imon_slope = 0x0, |
| 122 | .imon_offset = 0x0, |
| 123 | .icc_max = VR_CFG_AMP(35), |
| 124 | .voltage_limit = 1520, |
Youness Alaoui | 3f42a26b | 2018-03-20 18:32:23 -0400 | [diff] [blame] | 125 | .ac_loadline = 520, |
| 126 | .dc_loadline = 420, |
Youness Alaoui | 047475c | 2017-05-08 16:50:23 -0400 | [diff] [blame] | 127 | }" |
| 128 | |
Youness Alaoui | debb785 | 2017-05-25 15:40:13 -0500 | [diff] [blame] | 129 | # Enable Root Ports 5 and 9 |
| 130 | register "PcieRpEnable[4]" = "1" |
| 131 | register "PcieRpEnable[8]" = "1" |
Youness Alaoui | 047475c | 2017-05-08 16:50:23 -0400 | [diff] [blame] | 132 | |
Matt DeVillier | 2ae2742 | 2017-05-25 15:53:29 -0500 | [diff] [blame] | 133 | # PL2 override 25W |
Sumeet R Pawnikar | 97c5464 | 2020-05-10 01:24:11 +0530 | [diff] [blame] | 134 | register "power_limits_config" = "{ |
| 135 | .tdp_pl2_override = 25, |
| 136 | }" |
Youness Alaoui | 047475c | 2017-05-08 16:50:23 -0400 | [diff] [blame] | 137 | |
Matt DeVillier | 2ae2742 | 2017-05-25 15:53:29 -0500 | [diff] [blame] | 138 | # Send an extra VR mailbox command for the PS4 exit issue |
| 139 | register "SendVrMbxCmd" = "2" |
Youness Alaoui | 047475c | 2017-05-08 16:50:23 -0400 | [diff] [blame] | 140 | |
Youness Alaoui | 047475c | 2017-05-08 16:50:23 -0400 | [diff] [blame] | 141 | device domain 0 on |
Felix Singer | 13ee2e6 | 2023-11-12 18:29:57 +0000 | [diff] [blame] | 142 | device ref igpu on end |
| 143 | device ref sa_thermal on end |
| 144 | device ref south_xhci on end |
| 145 | device ref south_xdci on end |
| 146 | device ref thermal on end |
Felix Singer | df7de39 | 2024-06-23 04:59:03 +0200 | [diff] [blame^] | 147 | device ref sata on |
| 148 | register "SataPortsEnable" = "{ |
| 149 | [0] = 1, |
| 150 | [2] = 1, |
| 151 | }" |
| 152 | end |
Jonathon Hall | 5fe0f90 | 2024-01-18 13:49:58 -0500 | [diff] [blame] | 153 | device ref pcie_rp5 on end |
Felix Singer | 13ee2e6 | 2023-11-12 18:29:57 +0000 | [diff] [blame] | 154 | device ref pcie_rp9 on end |
| 155 | device ref lpc_espi on |
Felix Singer | dcddc53f | 2024-06-23 03:39:24 +0200 | [diff] [blame] | 156 | # EC host command ranges are in 0x380-0x383 & 0x80-0x8f |
| 157 | register "gen1_dec" = "0x00000381" |
Elyes HAOUAS | b0f1988 | 2018-06-09 11:59:00 +0200 | [diff] [blame] | 158 | chip drivers/pc80/tpm |
| 159 | device pnp 0c31.0 on end |
| 160 | end |
Felix Singer | 13ee2e6 | 2023-11-12 18:29:57 +0000 | [diff] [blame] | 161 | end |
| 162 | device ref hda on end |
| 163 | device ref smbus on end |
| 164 | device ref fast_spi on end |
Youness Alaoui | 047475c | 2017-05-08 16:50:23 -0400 | [diff] [blame] | 165 | end |
| 166 | end |