Youness Alaoui | 047475c | 2017-05-08 16:50:23 -0400 | [diff] [blame] | 1 | chip soc/intel/skylake |
| 2 | |
| 3 | # Enable deep Sx states |
| 4 | register "deep_s3_enable_ac" = "0" |
| 5 | register "deep_s3_enable_dc" = "0" |
Youness Alaoui | c5b9658 | 2017-06-19 20:47:27 -0400 | [diff] [blame^] | 6 | register "deep_s5_enable_ac" = "0" |
| 7 | register "deep_s5_enable_dc" = "0" |
Youness Alaoui | 047475c | 2017-05-08 16:50:23 -0400 | [diff] [blame] | 8 | register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" |
| 9 | |
| 10 | # GPE configuration |
| 11 | # Note that GPE events called out in ASL code rely on this |
| 12 | # route. i.e. If this route changes then the affected GPE |
| 13 | # offset bits also need to be changed. |
Youness Alaoui | 34a30a6 | 2017-05-25 13:25:41 -0500 | [diff] [blame] | 14 | register "gpe0_dw0" = "GPP_C" |
Youness Alaoui | 047475c | 2017-05-08 16:50:23 -0400 | [diff] [blame] | 15 | register "gpe0_dw1" = "GPP_D" |
| 16 | register "gpe0_dw2" = "GPP_E" |
| 17 | |
| 18 | # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f |
| 19 | register "gen1_dec" = "0x00fc0801" |
| 20 | register "gen2_dec" = "0x000c0201" |
| 21 | |
| 22 | # Enable "Intel Speed Shift Technology" |
| 23 | register "speed_shift_enable" = "1" |
| 24 | |
| 25 | # Enable DPTF |
| 26 | register "dptf_enable" = "1" |
| 27 | |
| 28 | # FSP Configuration |
| 29 | register "ProbelessTrace" = "0" |
| 30 | register "EnableLan" = "0" |
Youness Alaoui | 9d8cd50 | 2017-05-25 15:30:35 -0500 | [diff] [blame] | 31 | register "EnableSata" = "1" |
Youness Alaoui | 047475c | 2017-05-08 16:50:23 -0400 | [diff] [blame] | 32 | register "SataSalpSupport" = "0" |
| 33 | register "SataMode" = "0" |
Youness Alaoui | 9d8cd50 | 2017-05-25 15:30:35 -0500 | [diff] [blame] | 34 | register "SataPortsEnable[0]" = "1" |
Youness Alaoui | c5b9658 | 2017-06-19 20:47:27 -0400 | [diff] [blame^] | 35 | register "SataPortsEnable[1]" = "0" |
Youness Alaoui | 9d8cd50 | 2017-05-25 15:30:35 -0500 | [diff] [blame] | 36 | register "SataPortsEnable[2]" = "1" |
Youness Alaoui | c5b9658 | 2017-06-19 20:47:27 -0400 | [diff] [blame^] | 37 | register "SataPortsDevSlp[0]" = "0" |
| 38 | register "SataPortsDevSlp[2]" = "0" |
Youness Alaoui | 047475c | 2017-05-08 16:50:23 -0400 | [diff] [blame] | 39 | register "EnableAzalia" = "1" |
Youness Alaoui | eacac20 | 2017-05-17 17:16:09 -0400 | [diff] [blame] | 40 | register "DspEnable" = "0" |
| 41 | register "IoBufferOwnership" = "0" |
Youness Alaoui | 047475c | 2017-05-08 16:50:23 -0400 | [diff] [blame] | 42 | register "EnableTraceHub" = "0" |
| 43 | register "XdciEnable" = "0" |
| 44 | register "SsicPortEnable" = "0" |
| 45 | register "SmbusEnable" = "1" |
| 46 | register "Cio2Enable" = "0" |
Youness Alaoui | 9d8cd50 | 2017-05-25 15:30:35 -0500 | [diff] [blame] | 47 | register "ScsEmmcEnabled" = "0" |
| 48 | register "ScsEmmcHs400Enabled" = "0" |
Youness Alaoui | 047475c | 2017-05-08 16:50:23 -0400 | [diff] [blame] | 49 | register "ScsSdCardEnabled" = "0" |
| 50 | register "IshEnable" = "0" |
| 51 | register "PttSwitch" = "0" |
| 52 | register "InternalGfx" = "1" |
| 53 | register "SkipExtGfxScan" = "1" |
| 54 | register "Device4Enable" = "1" |
| 55 | register "HeciEnabled" = "0" |
| 56 | register "FspSkipMpInit" = "1" |
| 57 | register "SaGv" = "3" |
| 58 | register "SerialIrqConfigSirqEnable" = "1" |
| 59 | register "PmConfigSlpS3MinAssert" = "2" # 50ms |
| 60 | register "PmConfigSlpS4MinAssert" = "1" # 1s |
Youness Alaoui | c5b9658 | 2017-06-19 20:47:27 -0400 | [diff] [blame^] | 61 | register "PmConfigSlpSusMinAssert" = "3" # 500ms |
Youness Alaoui | 047475c | 2017-05-08 16:50:23 -0400 | [diff] [blame] | 62 | register "PmConfigSlpAMinAssert" = "3" # 2s |
Matt DeVillier | 0ff3b73 | 2017-05-25 15:31:49 -0500 | [diff] [blame] | 63 | register "PmTimerDisabled" = "0" |
Youness Alaoui | 047475c | 2017-05-08 16:50:23 -0400 | [diff] [blame] | 64 | |
| 65 | register "pirqa_routing" = "PCH_IRQ11" |
| 66 | register "pirqb_routing" = "PCH_IRQ10" |
| 67 | register "pirqc_routing" = "PCH_IRQ11" |
| 68 | register "pirqd_routing" = "PCH_IRQ11" |
| 69 | register "pirqe_routing" = "PCH_IRQ11" |
| 70 | register "pirqf_routing" = "PCH_IRQ11" |
| 71 | register "pirqg_routing" = "PCH_IRQ11" |
| 72 | register "pirqh_routing" = "PCH_IRQ11" |
| 73 | |
| 74 | # VR Settings Configuration for 5 Domains |
| 75 | #+----------------+-------+-------+-------------+-------------+-------+ |
| 76 | #| Domain/Setting | SA | IA | Ring Sliced | GT Unsliced | GT | |
| 77 | #+----------------+-------+-------+-------------+-------------+-------+ |
| 78 | #| Psi1Threshold | 20A | 20A | 20A | 20A | 20A | |
| 79 | #| Psi2Threshold | 4A | 5A | 5A | 5A | 5A | |
| 80 | #| Psi3Threshold | 1A | 1A | 1A | 1A | 1A | |
| 81 | #| Psi3Enable | 1 | 1 | 1 | 1 | 1 | |
| 82 | #| Psi4Enable | 1 | 1 | 1 | 1 | 1 | |
| 83 | #| ImonSlope | 0 | 0 | 0 | 0 | 0 | |
| 84 | #| ImonOffset | 0 | 0 | 0 | 0 | 0 | |
| 85 | #| IccMax | 7A | 34A | 34A | 35A | 35A | |
| 86 | #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | 1.52V | |
| 87 | #+----------------+-------+-------+-------------+-------------+-------+ |
| 88 | register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ |
| 89 | .vr_config_enable = 1, |
| 90 | .psi1threshold = VR_CFG_AMP(20), |
| 91 | .psi2threshold = VR_CFG_AMP(4), |
| 92 | .psi3threshold = VR_CFG_AMP(1), |
| 93 | .psi3enable = 1, |
| 94 | .psi4enable = 1, |
| 95 | .imon_slope = 0x0, |
| 96 | .imon_offset = 0x0, |
| 97 | .icc_max = VR_CFG_AMP(7), |
| 98 | .voltage_limit = 1520, |
| 99 | }" |
| 100 | |
| 101 | register "domain_vr_config[VR_IA_CORE]" = "{ |
| 102 | .vr_config_enable = 1, |
| 103 | .psi1threshold = VR_CFG_AMP(20), |
| 104 | .psi2threshold = VR_CFG_AMP(5), |
| 105 | .psi3threshold = VR_CFG_AMP(1), |
| 106 | .psi3enable = 1, |
| 107 | .psi4enable = 1, |
| 108 | .imon_slope = 0x0, |
| 109 | .imon_offset = 0x0, |
| 110 | .icc_max = VR_CFG_AMP(34), |
| 111 | .voltage_limit = 1520, |
| 112 | }" |
| 113 | |
| 114 | register "domain_vr_config[VR_RING]" = "{ |
| 115 | .vr_config_enable = 1, |
| 116 | .psi1threshold = VR_CFG_AMP(20), |
| 117 | .psi2threshold = VR_CFG_AMP(5), |
| 118 | .psi3threshold = VR_CFG_AMP(1), |
| 119 | .psi3enable = 1, |
| 120 | .psi4enable = 1, |
| 121 | .imon_slope = 0x0, |
| 122 | .imon_offset = 0x0, |
| 123 | .icc_max = VR_CFG_AMP(34), |
| 124 | .voltage_limit = 1520, |
| 125 | }" |
| 126 | |
| 127 | register "domain_vr_config[VR_GT_UNSLICED]" = "{ |
| 128 | .vr_config_enable = 1, |
| 129 | .psi1threshold = VR_CFG_AMP(20), |
| 130 | .psi2threshold = VR_CFG_AMP(5), |
| 131 | .psi3threshold = VR_CFG_AMP(1), |
| 132 | .psi3enable = 1, |
| 133 | .psi4enable = 1, |
| 134 | .imon_slope = 0x0, |
| 135 | .imon_offset = 0x0, |
| 136 | .icc_max = VR_CFG_AMP(35), |
| 137 | .voltage_limit = 1520, |
| 138 | }" |
| 139 | |
| 140 | register "domain_vr_config[VR_GT_SLICED]" = "{ |
| 141 | .vr_config_enable = 1, |
| 142 | .psi1threshold = VR_CFG_AMP(20), |
| 143 | .psi2threshold = VR_CFG_AMP(5), |
| 144 | .psi3threshold = VR_CFG_AMP(1), |
| 145 | .psi3enable = 1, |
| 146 | .psi4enable = 1, |
| 147 | .imon_slope = 0x0, |
| 148 | .imon_offset = 0x0, |
| 149 | .icc_max = VR_CFG_AMP(35), |
| 150 | .voltage_limit = 1520, |
| 151 | }" |
| 152 | |
Youness Alaoui | debb785 | 2017-05-25 15:40:13 -0500 | [diff] [blame] | 153 | # Enable Root Ports 5 and 9 |
| 154 | register "PcieRpEnable[4]" = "1" |
| 155 | register "PcieRpEnable[8]" = "1" |
Youness Alaoui | 047475c | 2017-05-08 16:50:23 -0400 | [diff] [blame] | 156 | |
Matt DeVillier | 2fa6616 | 2017-05-25 15:50:59 -0500 | [diff] [blame] | 157 | register "usb2_ports[0]" = "USB2_PORT_LONG(OC_SKIP)" # Type-C Port |
| 158 | register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port (right) |
Youness Alaoui | 047475c | 2017-05-08 16:50:23 -0400 | [diff] [blame] | 159 | register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth |
Matt DeVillier | 2fa6616 | 2017-05-25 15:50:59 -0500 | [diff] [blame] | 160 | register "usb2_ports[3]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera |
| 161 | register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port (left) |
| 162 | register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # SD |
Youness Alaoui | 047475c | 2017-05-08 16:50:23 -0400 | [diff] [blame] | 163 | |
Matt DeVillier | 2fa6616 | 2017-05-25 15:50:59 -0500 | [diff] [blame] | 164 | register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port (right) |
| 165 | register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port |
Youness Alaoui | 047475c | 2017-05-08 16:50:23 -0400 | [diff] [blame] | 166 | |
Matt DeVillier | 2ae2742 | 2017-05-25 15:53:29 -0500 | [diff] [blame] | 167 | # PL2 override 25W |
| 168 | register "tdp_pl2_override" = "25" |
Youness Alaoui | 047475c | 2017-05-08 16:50:23 -0400 | [diff] [blame] | 169 | |
Matt DeVillier | 2ae2742 | 2017-05-25 15:53:29 -0500 | [diff] [blame] | 170 | # Send an extra VR mailbox command for the PS4 exit issue |
| 171 | register "SendVrMbxCmd" = "2" |
Youness Alaoui | 047475c | 2017-05-08 16:50:23 -0400 | [diff] [blame] | 172 | |
Subrata Banik | c204aaa | 2017-08-17 15:49:58 +0530 | [diff] [blame] | 173 | # Lock Down |
| 174 | register "chipset_lockdown" = "CHIPSET_LOCKDOWN_COREBOOT" |
| 175 | |
Youness Alaoui | 047475c | 2017-05-08 16:50:23 -0400 | [diff] [blame] | 176 | device cpu_cluster 0 on |
| 177 | device lapic 0 on end |
| 178 | end |
| 179 | device domain 0 on |
| 180 | device pci 00.0 on end # Host Bridge |
| 181 | device pci 02.0 on end # Integrated Graphics Device |
| 182 | device pci 14.0 on end # USB xHCI |
Youness Alaoui | debb785 | 2017-05-25 15:40:13 -0500 | [diff] [blame] | 183 | device pci 14.1 on end # USB xDCI (OTG) |
Youness Alaoui | 047475c | 2017-05-08 16:50:23 -0400 | [diff] [blame] | 184 | device pci 14.2 on end # Thermal Subsystem |
| 185 | device pci 16.0 on end # Management Engine Interface 1 |
| 186 | device pci 16.1 off end # Management Engine Interface 2 |
| 187 | device pci 16.2 off end # Management Engine IDE-R |
| 188 | device pci 16.3 off end # Management Engine KT Redirection |
| 189 | device pci 16.4 off end # Management Engine Interface 3 |
| 190 | device pci 17.0 on end # SATA |
Youness Alaoui | debb785 | 2017-05-25 15:40:13 -0500 | [diff] [blame] | 191 | device pci 1c.0 on end # PCI Express Port 1 |
Youness Alaoui | 047475c | 2017-05-08 16:50:23 -0400 | [diff] [blame] | 192 | device pci 1c.1 off end # PCI Express Port 2 |
| 193 | device pci 1c.2 off end # PCI Express Port 3 |
| 194 | device pci 1c.3 off end # PCI Express Port 4 |
| 195 | device pci 1c.4 off end # PCI Express Port 5 |
| 196 | device pci 1c.5 off end # PCI Express Port 6 |
| 197 | device pci 1c.6 off end # PCI Express Port 7 |
| 198 | device pci 1c.7 off end # PCI Express Port 8 |
Youness Alaoui | debb785 | 2017-05-25 15:40:13 -0500 | [diff] [blame] | 199 | device pci 1d.0 on end # PCI Express Port 9 |
Youness Alaoui | 047475c | 2017-05-08 16:50:23 -0400 | [diff] [blame] | 200 | device pci 1d.1 off end # PCI Express Port 10 |
| 201 | device pci 1d.2 off end # PCI Express Port 11 |
| 202 | device pci 1d.3 off end # PCI Express Port 12 |
| 203 | device pci 1f.0 on |
| 204 | chip ec/purism/librem |
| 205 | device pnp 0c09.0 on end |
| 206 | end |
| 207 | end # LPC Interface |
Youness Alaoui | debb785 | 2017-05-25 15:40:13 -0500 | [diff] [blame] | 208 | device pci 1f.1 on end # P2SB |
Youness Alaoui | 047475c | 2017-05-08 16:50:23 -0400 | [diff] [blame] | 209 | device pci 1f.2 on end # Power Management Controller |
| 210 | device pci 1f.3 on end # Intel HDA |
| 211 | device pci 1f.4 on end # SMBus |
| 212 | device pci 1f.5 on end # PCH SPI |
| 213 | device pci 1f.6 off end # GbE |
| 214 | end |
| 215 | end |