Youness Alaoui | 047475c | 2017-05-08 16:50:23 -0400 | [diff] [blame] | 1 | chip soc/intel/skylake |
| 2 | |
| 3 | # Enable deep Sx states |
| 4 | register "deep_s3_enable_ac" = "0" |
| 5 | register "deep_s3_enable_dc" = "0" |
Youness Alaoui | c5b9658 | 2017-06-19 20:47:27 -0400 | [diff] [blame] | 6 | register "deep_s5_enable_ac" = "0" |
| 7 | register "deep_s5_enable_dc" = "0" |
Youness Alaoui | 047475c | 2017-05-08 16:50:23 -0400 | [diff] [blame] | 8 | register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" |
| 9 | |
Youness Alaoui | 0601f1e | 2018-02-09 18:44:45 -0500 | [diff] [blame] | 10 | register "eist_enable" = "1" |
| 11 | register "VmxEnable" = "1" |
| 12 | |
Youness Alaoui | cb8f04d | 2018-03-02 16:12:04 -0500 | [diff] [blame] | 13 | # Set the Thermal Control Circuit (TCC) activaction value to 95C |
| 14 | # even though FSP integration guide says to set it to 100C for SKL-U |
| 15 | # (offset at 0), because when the TCC activates at 100C, the CPU |
| 16 | # will have already shut itself down from overheating protection. |
| 17 | register "tcc_offset" = "5" # TCC of 95C |
| 18 | |
Youness Alaoui | 047475c | 2017-05-08 16:50:23 -0400 | [diff] [blame] | 19 | # GPE configuration |
| 20 | # Note that GPE events called out in ASL code rely on this |
| 21 | # route. i.e. If this route changes then the affected GPE |
| 22 | # offset bits also need to be changed. |
Youness Alaoui | 34a30a6 | 2017-05-25 13:25:41 -0500 | [diff] [blame] | 23 | register "gpe0_dw0" = "GPP_C" |
Youness Alaoui | 047475c | 2017-05-08 16:50:23 -0400 | [diff] [blame] | 24 | register "gpe0_dw1" = "GPP_D" |
| 25 | register "gpe0_dw2" = "GPP_E" |
| 26 | |
Youness Alaoui | 6aa28d9 | 2018-03-13 16:53:30 -0400 | [diff] [blame] | 27 | # EC host command ranges are in 0x380-0x383 & 0x80-0x8f |
| 28 | register "gen1_dec" = "0x00000381" |
| 29 | register "gen2_dec" = "0x000c0081" |
Youness Alaoui | 047475c | 2017-05-08 16:50:23 -0400 | [diff] [blame] | 30 | |
| 31 | # Enable "Intel Speed Shift Technology" |
| 32 | register "speed_shift_enable" = "1" |
| 33 | |
Youness Alaoui | 3f42a26b | 2018-03-20 18:32:23 -0400 | [diff] [blame^] | 34 | # Disable DPTF |
| 35 | register "dptf_enable" = "0" |
Youness Alaoui | 047475c | 2017-05-08 16:50:23 -0400 | [diff] [blame] | 36 | |
| 37 | # FSP Configuration |
| 38 | register "ProbelessTrace" = "0" |
| 39 | register "EnableLan" = "0" |
Youness Alaoui | 9d8cd50 | 2017-05-25 15:30:35 -0500 | [diff] [blame] | 40 | register "EnableSata" = "1" |
Youness Alaoui | 047475c | 2017-05-08 16:50:23 -0400 | [diff] [blame] | 41 | register "SataSalpSupport" = "0" |
| 42 | register "SataMode" = "0" |
Youness Alaoui | 9d8cd50 | 2017-05-25 15:30:35 -0500 | [diff] [blame] | 43 | register "SataPortsEnable[0]" = "1" |
Youness Alaoui | c5b9658 | 2017-06-19 20:47:27 -0400 | [diff] [blame] | 44 | register "SataPortsEnable[1]" = "0" |
Youness Alaoui | 9d8cd50 | 2017-05-25 15:30:35 -0500 | [diff] [blame] | 45 | register "SataPortsEnable[2]" = "1" |
Youness Alaoui | c5b9658 | 2017-06-19 20:47:27 -0400 | [diff] [blame] | 46 | register "SataPortsDevSlp[0]" = "0" |
| 47 | register "SataPortsDevSlp[2]" = "0" |
Matt DeVillier | fb1cd09 | 2017-06-22 15:54:07 -0400 | [diff] [blame] | 48 | register "SataSpeedLimit" = "2" |
Youness Alaoui | 047475c | 2017-05-08 16:50:23 -0400 | [diff] [blame] | 49 | register "EnableAzalia" = "1" |
Youness Alaoui | eacac20 | 2017-05-17 17:16:09 -0400 | [diff] [blame] | 50 | register "DspEnable" = "0" |
| 51 | register "IoBufferOwnership" = "0" |
Youness Alaoui | 047475c | 2017-05-08 16:50:23 -0400 | [diff] [blame] | 52 | register "EnableTraceHub" = "0" |
Youness Alaoui | 047475c | 2017-05-08 16:50:23 -0400 | [diff] [blame] | 53 | register "SsicPortEnable" = "0" |
| 54 | register "SmbusEnable" = "1" |
| 55 | register "Cio2Enable" = "0" |
Youness Alaoui | 9d8cd50 | 2017-05-25 15:30:35 -0500 | [diff] [blame] | 56 | register "ScsEmmcEnabled" = "0" |
| 57 | register "ScsEmmcHs400Enabled" = "0" |
Youness Alaoui | 047475c | 2017-05-08 16:50:23 -0400 | [diff] [blame] | 58 | register "ScsSdCardEnabled" = "0" |
| 59 | register "IshEnable" = "0" |
| 60 | register "PttSwitch" = "0" |
| 61 | register "InternalGfx" = "1" |
| 62 | register "SkipExtGfxScan" = "1" |
| 63 | register "Device4Enable" = "1" |
| 64 | register "HeciEnabled" = "0" |
| 65 | register "FspSkipMpInit" = "1" |
| 66 | register "SaGv" = "3" |
| 67 | register "SerialIrqConfigSirqEnable" = "1" |
| 68 | register "PmConfigSlpS3MinAssert" = "2" # 50ms |
| 69 | register "PmConfigSlpS4MinAssert" = "1" # 1s |
Youness Alaoui | c5b9658 | 2017-06-19 20:47:27 -0400 | [diff] [blame] | 70 | register "PmConfigSlpSusMinAssert" = "3" # 500ms |
Youness Alaoui | 047475c | 2017-05-08 16:50:23 -0400 | [diff] [blame] | 71 | register "PmConfigSlpAMinAssert" = "3" # 2s |
Matt DeVillier | 0ff3b73 | 2017-05-25 15:31:49 -0500 | [diff] [blame] | 72 | register "PmTimerDisabled" = "0" |
Youness Alaoui | 047475c | 2017-05-08 16:50:23 -0400 | [diff] [blame] | 73 | |
| 74 | register "pirqa_routing" = "PCH_IRQ11" |
| 75 | register "pirqb_routing" = "PCH_IRQ10" |
| 76 | register "pirqc_routing" = "PCH_IRQ11" |
| 77 | register "pirqd_routing" = "PCH_IRQ11" |
| 78 | register "pirqe_routing" = "PCH_IRQ11" |
| 79 | register "pirqf_routing" = "PCH_IRQ11" |
| 80 | register "pirqg_routing" = "PCH_IRQ11" |
| 81 | register "pirqh_routing" = "PCH_IRQ11" |
| 82 | |
Matt DeVillier | fb1cd09 | 2017-06-22 15:54:07 -0400 | [diff] [blame] | 83 | # VR Settings Configuration for 4 Domains |
Youness Alaoui | 3f42a26b | 2018-03-20 18:32:23 -0400 | [diff] [blame^] | 84 | #+----------------+-----------+-----------+-------------+----------+ |
| 85 | #| Domain/Setting | SA | IA | GT Unsliced | GT | |
| 86 | #+----------------+-----------+-----------+-------------+----------+ |
| 87 | #| Psi1Threshold | 20A | 20A | 20A | 20A | |
| 88 | #| Psi2Threshold | 4A | 5A | 5A | 5A | |
| 89 | #| Psi3Threshold | 1A | 1A | 1A | 1A | |
| 90 | #| Psi3Enable | 1 | 1 | 1 | 1 | |
| 91 | #| Psi4Enable | 1 | 1 | 1 | 1 | |
| 92 | #| ImonSlope | 0 | 0 | 0 | 0 | |
| 93 | #| ImonOffset | 0 | 0 | 0 | 0 | |
| 94 | #| IccMax | 7A | 34A | 35A | 35A | |
| 95 | #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | |
| 96 | #| AC LoadLine | 15 mOhm | 5.7 mOhm | 5.2 mOhm | 5.2 mOhm | |
| 97 | #| DC LoadLine | 14.3 mOhm | 4.83 mOhm | 4.2 mOhm | 4.2 mOhm | |
| 98 | #+----------------+-----------+-----------+-------------+----------+ |
Youness Alaoui | 047475c | 2017-05-08 16:50:23 -0400 | [diff] [blame] | 99 | register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ |
| 100 | .vr_config_enable = 1, |
| 101 | .psi1threshold = VR_CFG_AMP(20), |
| 102 | .psi2threshold = VR_CFG_AMP(4), |
| 103 | .psi3threshold = VR_CFG_AMP(1), |
| 104 | .psi3enable = 1, |
| 105 | .psi4enable = 1, |
| 106 | .imon_slope = 0x0, |
| 107 | .imon_offset = 0x0, |
| 108 | .icc_max = VR_CFG_AMP(7), |
| 109 | .voltage_limit = 1520, |
Youness Alaoui | 3f42a26b | 2018-03-20 18:32:23 -0400 | [diff] [blame^] | 110 | .ac_loadline = 1500, |
| 111 | .dc_loadline = 1430, |
Youness Alaoui | 047475c | 2017-05-08 16:50:23 -0400 | [diff] [blame] | 112 | }" |
| 113 | |
| 114 | register "domain_vr_config[VR_IA_CORE]" = "{ |
| 115 | .vr_config_enable = 1, |
| 116 | .psi1threshold = VR_CFG_AMP(20), |
| 117 | .psi2threshold = VR_CFG_AMP(5), |
| 118 | .psi3threshold = VR_CFG_AMP(1), |
| 119 | .psi3enable = 1, |
| 120 | .psi4enable = 1, |
| 121 | .imon_slope = 0x0, |
| 122 | .imon_offset = 0x0, |
| 123 | .icc_max = VR_CFG_AMP(34), |
| 124 | .voltage_limit = 1520, |
Youness Alaoui | 3f42a26b | 2018-03-20 18:32:23 -0400 | [diff] [blame^] | 125 | .ac_loadline = 570, |
| 126 | .dc_loadline = 483, |
Youness Alaoui | 047475c | 2017-05-08 16:50:23 -0400 | [diff] [blame] | 127 | }" |
| 128 | |
Youness Alaoui | 047475c | 2017-05-08 16:50:23 -0400 | [diff] [blame] | 129 | register "domain_vr_config[VR_GT_UNSLICED]" = "{ |
| 130 | .vr_config_enable = 1, |
| 131 | .psi1threshold = VR_CFG_AMP(20), |
| 132 | .psi2threshold = VR_CFG_AMP(5), |
| 133 | .psi3threshold = VR_CFG_AMP(1), |
| 134 | .psi3enable = 1, |
| 135 | .psi4enable = 1, |
| 136 | .imon_slope = 0x0, |
| 137 | .imon_offset = 0x0, |
| 138 | .icc_max = VR_CFG_AMP(35), |
| 139 | .voltage_limit = 1520, |
Youness Alaoui | 3f42a26b | 2018-03-20 18:32:23 -0400 | [diff] [blame^] | 140 | .ac_loadline = 520, |
| 141 | .dc_loadline = 420, |
Youness Alaoui | 047475c | 2017-05-08 16:50:23 -0400 | [diff] [blame] | 142 | }" |
| 143 | |
| 144 | register "domain_vr_config[VR_GT_SLICED]" = "{ |
| 145 | .vr_config_enable = 1, |
| 146 | .psi1threshold = VR_CFG_AMP(20), |
| 147 | .psi2threshold = VR_CFG_AMP(5), |
| 148 | .psi3threshold = VR_CFG_AMP(1), |
| 149 | .psi3enable = 1, |
| 150 | .psi4enable = 1, |
| 151 | .imon_slope = 0x0, |
| 152 | .imon_offset = 0x0, |
| 153 | .icc_max = VR_CFG_AMP(35), |
| 154 | .voltage_limit = 1520, |
Youness Alaoui | 3f42a26b | 2018-03-20 18:32:23 -0400 | [diff] [blame^] | 155 | .ac_loadline = 520, |
| 156 | .dc_loadline = 420, |
Youness Alaoui | 047475c | 2017-05-08 16:50:23 -0400 | [diff] [blame] | 157 | }" |
| 158 | |
Youness Alaoui | debb785 | 2017-05-25 15:40:13 -0500 | [diff] [blame] | 159 | # Enable Root Ports 5 and 9 |
| 160 | register "PcieRpEnable[4]" = "1" |
| 161 | register "PcieRpEnable[8]" = "1" |
Youness Alaoui | 047475c | 2017-05-08 16:50:23 -0400 | [diff] [blame] | 162 | |
Youness Alaoui | a8b35be | 2017-07-25 14:11:31 -0400 | [diff] [blame] | 163 | register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port |
| 164 | register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" # Type-A Port (right) |
Youness Alaoui | 047475c | 2017-05-08 16:50:23 -0400 | [diff] [blame] | 165 | register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth |
Matt DeVillier | 2fa6616 | 2017-05-25 15:50:59 -0500 | [diff] [blame] | 166 | register "usb2_ports[3]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera |
Youness Alaoui | a8b35be | 2017-07-25 14:11:31 -0400 | [diff] [blame] | 167 | register "usb2_ports[5]" = "USB2_PORT_FLEX(OC2)" # Type-A Port (left) |
Matt DeVillier | 2fa6616 | 2017-05-25 15:50:59 -0500 | [diff] [blame] | 168 | register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # SD |
Youness Alaoui | 047475c | 2017-05-08 16:50:23 -0400 | [diff] [blame] | 169 | |
Youness Alaoui | a8b35be | 2017-07-25 14:11:31 -0400 | [diff] [blame] | 170 | # OC1 should be for Type-C but it seems to not have been wired, according to |
| 171 | # the available schematics, even though it is labeled as USB_OC_TYPEC. |
| 172 | register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port |
| 173 | register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # Type-A Port (right) |
Matt DeVillier | 2fa6616 | 2017-05-25 15:50:59 -0500 | [diff] [blame] | 174 | register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port |
Youness Alaoui | 047475c | 2017-05-08 16:50:23 -0400 | [diff] [blame] | 175 | |
Matt DeVillier | 2ae2742 | 2017-05-25 15:53:29 -0500 | [diff] [blame] | 176 | # PL2 override 25W |
| 177 | register "tdp_pl2_override" = "25" |
Youness Alaoui | 047475c | 2017-05-08 16:50:23 -0400 | [diff] [blame] | 178 | |
Matt DeVillier | 2ae2742 | 2017-05-25 15:53:29 -0500 | [diff] [blame] | 179 | # Send an extra VR mailbox command for the PS4 exit issue |
| 180 | register "SendVrMbxCmd" = "2" |
Youness Alaoui | 047475c | 2017-05-08 16:50:23 -0400 | [diff] [blame] | 181 | |
Subrata Banik | c204aaa | 2017-08-17 15:49:58 +0530 | [diff] [blame] | 182 | # Lock Down |
| 183 | register "chipset_lockdown" = "CHIPSET_LOCKDOWN_COREBOOT" |
| 184 | |
Youness Alaoui | 047475c | 2017-05-08 16:50:23 -0400 | [diff] [blame] | 185 | device cpu_cluster 0 on |
| 186 | device lapic 0 on end |
| 187 | end |
| 188 | device domain 0 on |
| 189 | device pci 00.0 on end # Host Bridge |
| 190 | device pci 02.0 on end # Integrated Graphics Device |
| 191 | device pci 14.0 on end # USB xHCI |
Youness Alaoui | debb785 | 2017-05-25 15:40:13 -0500 | [diff] [blame] | 192 | device pci 14.1 on end # USB xDCI (OTG) |
Youness Alaoui | 047475c | 2017-05-08 16:50:23 -0400 | [diff] [blame] | 193 | device pci 14.2 on end # Thermal Subsystem |
| 194 | device pci 16.0 on end # Management Engine Interface 1 |
| 195 | device pci 16.1 off end # Management Engine Interface 2 |
| 196 | device pci 16.2 off end # Management Engine IDE-R |
| 197 | device pci 16.3 off end # Management Engine KT Redirection |
| 198 | device pci 16.4 off end # Management Engine Interface 3 |
| 199 | device pci 17.0 on end # SATA |
Youness Alaoui | debb785 | 2017-05-25 15:40:13 -0500 | [diff] [blame] | 200 | device pci 1c.0 on end # PCI Express Port 1 |
Youness Alaoui | 047475c | 2017-05-08 16:50:23 -0400 | [diff] [blame] | 201 | device pci 1c.1 off end # PCI Express Port 2 |
| 202 | device pci 1c.2 off end # PCI Express Port 3 |
| 203 | device pci 1c.3 off end # PCI Express Port 4 |
| 204 | device pci 1c.4 off end # PCI Express Port 5 |
| 205 | device pci 1c.5 off end # PCI Express Port 6 |
| 206 | device pci 1c.6 off end # PCI Express Port 7 |
| 207 | device pci 1c.7 off end # PCI Express Port 8 |
Youness Alaoui | debb785 | 2017-05-25 15:40:13 -0500 | [diff] [blame] | 208 | device pci 1d.0 on end # PCI Express Port 9 |
Youness Alaoui | 047475c | 2017-05-08 16:50:23 -0400 | [diff] [blame] | 209 | device pci 1d.1 off end # PCI Express Port 10 |
| 210 | device pci 1d.2 off end # PCI Express Port 11 |
| 211 | device pci 1d.3 off end # PCI Express Port 12 |
| 212 | device pci 1f.0 on |
| 213 | chip ec/purism/librem |
| 214 | device pnp 0c09.0 on end |
| 215 | end |
Youness Alaoui | 59d89a8 | 2018-02-09 18:42:49 -0500 | [diff] [blame] | 216 | chip drivers/pc80/tpm |
| 217 | device pnp 0c31.0 on end |
| 218 | end |
Youness Alaoui | 047475c | 2017-05-08 16:50:23 -0400 | [diff] [blame] | 219 | end # LPC Interface |
Youness Alaoui | debb785 | 2017-05-25 15:40:13 -0500 | [diff] [blame] | 220 | device pci 1f.1 on end # P2SB |
Youness Alaoui | 047475c | 2017-05-08 16:50:23 -0400 | [diff] [blame] | 221 | device pci 1f.2 on end # Power Management Controller |
| 222 | device pci 1f.3 on end # Intel HDA |
| 223 | device pci 1f.4 on end # SMBus |
| 224 | device pci 1f.5 on end # PCH SPI |
| 225 | device pci 1f.6 off end # GbE |
| 226 | end |
| 227 | end |