src/mainboard/protectli/vault_kbl/devicetree.cb

chip soc/intel/skylake

	# Enable deep Sx states
	register "deep_s3_enable_ac" = "0"
	register "deep_s3_enable_dc" = "0"
	register "deep_s5_enable_ac" = "1"
	register "deep_s5_enable_dc" = "1"
	register "deep_sx_config" = "DSX_EN_WAKE_PIN | DSX_DIS_AC_PRESENT_PD"
	register "s0ix_enable" = true

	register "gpe0_dw0" = "GPP_B"
	register "gpe0_dw1" = "GPP_D"
	register "gpe0_dw2" = "GPP_E"

	register "eist_enable" = "1"

	# Disable DPTF
	register "dptf_enable" = "0"

	# Enable SERIRQ continuous
	register "serirq_mode" = "SERIRQ_CONTINUOUS"

	register "tcc_offset" = "5" # TCC of 95C

	# FSP Configuration
	register "DspEnable" = "0"
	register "IoBufferOwnership" = "0"
	register "SkipExtGfxScan" = "1"
	register "SaGv" = "SaGv_Enabled"
	register "IslVrCmd" = "2"
	register "PmConfigSlpS3MinAssert" = "2"		# 50ms
	register "PmConfigSlpS4MinAssert" = "4"		# 4s
	register "PmConfigSlpSusMinAssert" = "1"	# 500ms
	register "PmConfigSlpAMinAssert" = "3"		# 2s

	# VR Settings Configuration for 4 Domains
	#+----------------+-------+-------+-------+-------+
	#| Domain/Setting |  SA   |  IA   | GTUS  |  GTS  |
	#+----------------+-------+-------+-------+-------+
	#| Psi1Threshold  | 20A   | 20A   | 20A   | 20A   |
	#| Psi2Threshold  | 4A    | 5A    | 5A    | 5A    |
	#| Psi3Threshold  | 1A    | 1A    | 1A    | 1A    |
	#| Psi3Enable     | 1     | 1     | 1     | 1     |
	#| Psi4Enable     | 1     | 1     | 1     | 1     |
	#| ImonSlope      | 0     | 0     | 0     | 0     |
	#| ImonOffset     | 0     | 0     | 0     | 0     |
	#| IccMax         | 7A    | 34A   | 35A   | 35A   |
	#| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |
	#| AcLoadline(ohm)| 10.3m | 2.4m  | 3.1m  | 3.1m  |
	#| DcLoadline(ohm)| 10.3m | 2.4m  | 3.1m  | 3.1m  |
	#+----------------+-------+-------+-------+-------+
	#Note: IccMax settings are moved to SoC code
	register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
		.vr_config_enable = 1,
		.psi1threshold = VR_CFG_AMP(20),
		.psi2threshold = VR_CFG_AMP(4),
		.psi3threshold = VR_CFG_AMP(1),
		.psi3enable = 1,
		.psi4enable = 1,
		.imon_slope = 0x0,
		.imon_offset = 0x0,
		.voltage_limit = 1520,
	}"

	register "domain_vr_config[VR_IA_CORE]" = "{
		.vr_config_enable = 1,
		.psi1threshold = VR_CFG_AMP(20),
		.psi2threshold = VR_CFG_AMP(5),
		.psi3threshold = VR_CFG_AMP(1),
		.psi3enable = 1,
		.psi4enable = 1,
		.imon_slope = 0x0,
		.imon_offset = 0x0,
		.voltage_limit = 1520,
	}"

	register "domain_vr_config[VR_GT_UNSLICED]" = "{
		.vr_config_enable = 1,
		.psi1threshold = VR_CFG_AMP(20),
		.psi2threshold = VR_CFG_AMP(5),
		.psi3threshold = VR_CFG_AMP(1),
		.psi3enable = 1,
		.psi4enable = 1,
		.imon_slope = 0x0,
		.imon_offset = 0x0,
		.voltage_limit = 1520,
	}"

	register "domain_vr_config[VR_GT_SLICED]" = "{
		.vr_config_enable = 1,
		.psi1threshold = VR_CFG_AMP(20),
		.psi2threshold = VR_CFG_AMP(5),
		.psi3threshold = VR_CFG_AMP(1),
		.psi3enable = 1,
		.psi4enable = 1,
		.imon_slope = 0x0,
		.imon_offset = 0x0,
		.voltage_limit = 1520,
	}"

	# Send an extra VR mailbox command for the PS4 exit issue
	register "SendVrMbxCmd" = "2"

	# Enable Root ports. 1-6 for LAN and Root Port 9
	register "PcieRpEnable[0]" = "1"
	register "PcieRpEnable[1]" = "1"
	register "PcieRpEnable[2]" = "1"
	register "PcieRpEnable[3]" = "1"
	register "PcieRpEnable[4]" = "1"
	register "PcieRpEnable[5]" = "1"
	register "PcieRpEnable[8]" = "1" # mPCIe WiFi

	# Enable Advanced Error Reporting for RP 1-6, 9
	register "PcieRpAdvancedErrorReporting[0]" = "1"
	register "PcieRpAdvancedErrorReporting[1]" = "1"
	register "PcieRpAdvancedErrorReporting[2]" = "1"
	register "PcieRpAdvancedErrorReporting[3]" = "1"
	register "PcieRpAdvancedErrorReporting[4]" = "1"
	register "PcieRpAdvancedErrorReporting[5]" = "1"
	register "PcieRpAdvancedErrorReporting[8]" = "1"

	# Enable Latency Tolerance Reporting Mechanism RP 1-6, 9
	register "PcieRpLtrEnable[0]" = "1"
	register "PcieRpLtrEnable[1]" = "1"
	register "PcieRpLtrEnable[2]" = "1"
	register "PcieRpLtrEnable[3]" = "1"
	register "PcieRpLtrEnable[4]" = "1"
	register "PcieRpLtrEnable[5]" = "1"
	register "PcieRpLtrEnable[8]" = "1"

	# Enable RP 9 CLKREQ# support
	register "PcieRpClkReqSupport[8]" = "1"
	# RP 9 uses CLKREQ0#
	register "PcieRpClkReqNumber[8]" = "0"

	# Clocks 0-5 for RP 1-6
	register "PcieRpClkSrcNumber[0]" = "0"
	register "PcieRpClkSrcNumber[1]" = "1"
	register "PcieRpClkSrcNumber[2]" = "2"
	register "PcieRpClkSrcNumber[3]" = "3"
	register "PcieRpClkSrcNumber[4]" = "4"
	register "PcieRpClkSrcNumber[5]" = "5"
	# RP 9 shares CLKSRC5# with RP 6
	register "PcieRpClkSrcNumber[8]" = "5"

	register "SerialIoDevMode" = "{
		[PchSerialIoIndexI2C0]  = PchSerialIoDisabled,
		[PchSerialIoIndexI2C1]  = PchSerialIoDisabled,
		[PchSerialIoIndexI2C2]  = PchSerialIoDisabled,
		[PchSerialIoIndexI2C3]  = PchSerialIoDisabled,
		[PchSerialIoIndexI2C4]  = PchSerialIoDisabled,
		[PchSerialIoIndexI2C5]  = PchSerialIoDisabled,
		[PchSerialIoIndexSpi0]  = PchSerialIoDisabled,
		[PchSerialIoIndexSpi1]  = PchSerialIoDisabled,
		[PchSerialIoIndexUart0] = PchSerialIoDisabled,
		[PchSerialIoIndexUart1] = PchSerialIoDisabled,
		[PchSerialIoIndexUart2] = PchSerialIoDisabled,
	}"

	device domain 0 on
		device ref igpu		on  end
		device ref south_xhci	on
			register "usb2_ports" = "{
				[0]  = USB2_PORT_SHORT(OC_SKIP),	// TYPE-A Port
				[1]  = USB2_PORT_SHORT(OC_SKIP),	// TYPE-A Port
				[2]  = USB2_PORT_SHORT(OC_SKIP),	// TYPE-A Port
				[3]  = USB2_PORT_SHORT(OC_SKIP),	// TYPE-A Port
				[4]  = USB2_PORT_SHORT(OC_SKIP),	// Type-A Port
				[5]  = USB2_PORT_SHORT(OC_SKIP),	// TYPE-A Port
				[6]  = USB2_PORT_SHORT(OC_SKIP),	// TYPE-A Port
				[7]  = USB2_PORT_SHORT(OC_SKIP),	// mPCIe slot
			}"

			register "usb3_ports" = "{
				[0] = USB3_PORT_DEFAULT(OC_SKIP),	// TYPE-A Port
				[1] = USB3_PORT_DEFAULT(OC_SKIP),	// TYPE-A Port
				[2] = USB3_PORT_DEFAULT(OC_SKIP),	// TYPE-A Port
				[3] = USB3_PORT_DEFAULT(OC_SKIP),	// TYPE-A Port
			}"
		end
		device ref heci1	on  end
		device ref sata		on
			register "SataPortsEnable" = "{
				[0] = 1,
				[1] = 1,
			}"
		end
		device ref pcie_rp1	on  end
		device ref pcie_rp2	on  end
		device ref pcie_rp3	on  end
		device ref pcie_rp4	on  end
		device ref pcie_rp5	on  end
		device ref pcie_rp6	on  end
		device ref pcie_rp9	on
			# WIFI
			smbios_slot_desc
				"SlotTypePciExpressMini52pinWithoutBSKO"
				"SlotLengthShort" "WIFI1" "SlotDataBusWidth1X"
		end
		device ref lpc_espi	on
			register "gen1_dec" = "0x00fc0201"
			register "gen2_dec" = "0x007c0a01"
			register "gen3_dec" = "0x000c03e1"
			register "gen4_dec" = "0x001c02e1"
			chip superio/ite/it8772f
				register "TMPIN1.mode" = "THERMAL_RESISTOR"
				register "TMPIN2.mode" = "THERMAL_RESISTOR"
				register "TMPIN3.mode" = "THERMAL_PECI"
				# FAN2 available on fan header but unused
				device pnp 2e.0 off end # FDC
				device pnp 2e.1 on # Serial Port 1
					io 0x60 = 0x3f8
					irq 0x70 = 4
				end
				device pnp 2e.4 on # Environment Controller
					io 0x60 = 0xa40
					io 0x62 = 0xa30
					irq 0x70 = 9
				end
				device pnp 2e.5 off end # Keyboard
				device pnp 2e.6 off end # Mouse
				device pnp 2e.7 off end # GPIO
				device pnp 2e.a off end # IR
			end
		end
		device ref smbus	on  end
	end
	chip drivers/crb
		device mmio 0xfed40000 on end
	end
end