skl mainboards/dt: Move usb{2,3}_ports settings into XHCI device scope
Change-Id: I22ba991a9d559b0ecc7b3ceddcfd099890dd6c3a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb
index f57f978..6148196 100644
--- a/src/mainboard/protectli/vault_kbl/devicetree.cb
+++ b/src/mainboard/protectli/vault_kbl/devicetree.cb
@@ -152,23 +152,6 @@
# RP 9 shares CLKSRC5# with RP 6
register "PcieRpClkSrcNumber[8]" = "5"
-
- # USB 2.0 enable ports 1-8, disable ports 9-12
- register "usb2_ports[0]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port
- register "usb2_ports[1]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port
- register "usb2_ports[2]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port
- register "usb2_ports[3]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port
- register "usb2_ports[4]" = "USB2_PORT_SHORT(OC_SKIP)" # Type-A Port
- register "usb2_ports[5]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port
- register "usb2_ports[6]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port
- register "usb2_ports[7]" = "USB2_PORT_SHORT(OC_SKIP)" # mPCIe slot
-
- # USB 3.0 enable ports 1-4, disable ports 5-6
- register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port
- register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port
- register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port
- register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port
-
register "SerialIoDevMode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoDisabled,
[PchSerialIoIndexI2C1] = PchSerialIoDisabled,
@@ -185,7 +168,25 @@
device domain 0 on
device ref igpu on end
- device ref south_xhci on end
+ device ref south_xhci on
+ register "usb2_ports" = "{
+ [0] = USB2_PORT_SHORT(OC_SKIP), // TYPE-A Port
+ [1] = USB2_PORT_SHORT(OC_SKIP), // TYPE-A Port
+ [2] = USB2_PORT_SHORT(OC_SKIP), // TYPE-A Port
+ [3] = USB2_PORT_SHORT(OC_SKIP), // TYPE-A Port
+ [4] = USB2_PORT_SHORT(OC_SKIP), // Type-A Port
+ [5] = USB2_PORT_SHORT(OC_SKIP), // TYPE-A Port
+ [6] = USB2_PORT_SHORT(OC_SKIP), // TYPE-A Port
+ [7] = USB2_PORT_SHORT(OC_SKIP), // mPCIe slot
+ }"
+
+ register "usb3_ports" = "{
+ [0] = USB3_PORT_DEFAULT(OC_SKIP), // TYPE-A Port
+ [1] = USB3_PORT_DEFAULT(OC_SKIP), // TYPE-A Port
+ [2] = USB3_PORT_DEFAULT(OC_SKIP), // TYPE-A Port
+ [3] = USB3_PORT_DEFAULT(OC_SKIP), // TYPE-A Port
+ }"
+ end
device ref heci1 on end
device ref sata on end
device ref pcie_rp1 on end