blob: a67cc1aeb5d10aed9bfd6fce43bd7878c765f8c4 [file] [log] [blame]
Damien Zammit62477932015-05-03 21:34:38 +10001#include <arch/io.h>
2#define PCIEXBAR 0x60
Damien Zammit2cfab902016-01-18 16:39:51 +11003#define MMCONF_256_BUSSES 16
4#define ENABLE 1
Damien Zammit62477932015-05-03 21:34:38 +10005
6static void bootblock_northbridge_init(void)
7{
8 pci_io_write_config32(PCI_DEV(0,0,0), PCIEXBAR,
Damien Zammit2cfab902016-01-18 16:39:51 +11009 CONFIG_MMCONF_BASE_ADDRESS | MMCONF_256_BUSSES | ENABLE);
Damien Zammit62477932015-05-03 21:34:38 +100010}