Gitiles
Code Review Sign In
review.coreboot.org / coreboot / 49af4f7f9197e559b2c7142129441679bb1d24a2 / . / src / vendorcode / amd / agesa / Kconfig
blob: 4bc6a3d569db5bc4947875f91a67600655f3cd19 [file] [log] [blame]
Mike Banon3ee99352020-04-17 14:35:20 +0300[diff] [blame]1# SPDX-License-Identifier: GPL-2.0-only
Mike Banon3ee99352020-04-17 14:35:20 +0300[diff] [blame]2
Angel Pons02d9c852021-05-09 15:07:18 +0200[diff] [blame]3config IDS_OPTIONS_HOOKED_UP
4 bool
5 help
6 to Kconfig options.
7 Historically, IDS configuration was defined in a mainboard-specific
8 `OptionsIds.h` header. Select this on platforms where IDS config is
9 hooked up to Kconfig options instead.
10
11if IDS_OPTIONS_HOOKED_UP
12
13config IDS_ENABLED
14 bool "Enable AGESA IDS (Integrated Debug Services) support"
15 default y
16 help
17 This is the master switch for the IDS sub-system. Use this option to
18 enable or remove the entire IDS feature set. This switch must be TRUE
19 for any of the other options to function.
20
21comment "Warning: IDS options may not work. Enable at your own risk!"
22 depends on IDS_ENABLED
23
24config IDS_CONTROL_ENABLED
25 bool "Enable IDS User Interface controls"
26 depends on IDS_ENABLED
27 help
28 This is the main switch for the IDS configuration controls. This
29 switch must be TRUE for any of the configuration controls to function.
30
31 This seems to allow AGESA to retrieve settings from CMOS.
32
33config IDS_PERF_ANALYSIS
34 bool "Enable IDS performance analysis"
35 depends on IDS_ENABLED
36 help
37 This is the main switch for the IDS performance analysis controls,
38 macros and support code needed to enable time data gathering. This
39 switch must be TRUE for any of the performance analysis features to
40 function.
41
42config IDS_TRACING_ENABLED
43 bool "Enable IDS console"
44 depends on IDS_ENABLED
45 help
46 This is the main switch for the IDS console controls, macros and
47 support code needed to enable tracing of algorithms. This switch
48 must be TRUE for any of the tracing features to function.
49
50config IDS_TRACING_CONSOLE_SERIAL
51 bool "Use serial port as IDS console"
52 depends on IDS_TRACING_ENABLED
53 default DRIVERS_UART_8250IO && CONSOLE_SERIAL
54 help
55 Use an I/O-mapped serial port to output IDS messages.
56
57endif # IDS_OPTIONS_HOOKED_UP
58
Mike Banon3ee99352020-04-17 14:35:20 +0300[diff] [blame]59choice
60 prompt "DDR3 memory profile"
61 default CPU_AMD_AGESA_OPENSOURCE_MEM_JEDEC
62 help
63 Choose the DDR3 memory profile to use for your RAM sticks, e.g. XMP 1.
64 XMP support is experimental, and your PC will fail booting if you choose
65 a profile which does not exist on ANY of your RAM sticks! If in doubt
66 check their SPD Data using a coreboot's great fork of memtest86+ 5.01.
67
68config CPU_AMD_AGESA_OPENSOURCE_MEM_JEDEC
69 bool "JEDEC"
70 help
71 JEDEC memory profile, standard and stable. Is guaranteed to be working.
72
73config CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_1
74 bool "XMP 1"
75 help
76 XMP 1 memory profile. Check that it exists on ALL of your RAM sticks!
77
78config CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_2
79 bool "XMP 2"
80 help
81 XMP 2 memory profile. Check that it exists on ALL of your RAM sticks!
82
Mike Banonf7b410d2020-04-17 14:56:42 +0300[diff] [blame]83config CPU_AMD_AGESA_OPENSOURCE_MEM_CUSTOM
84 bool "CUSTOM"
85 help
86 Custom memory profile. Use the XMP SPD values as the base, if available.
87
Angel Ponsccbbb1b2021-09-16 18:06:40 +0200[diff] [blame]88endchoice
89
Mike Banonf7b410d2020-04-17 14:56:42 +0300[diff] [blame]90if CPU_AMD_AGESA_OPENSOURCE_MEM_CUSTOM
91
92config CUSTOM_SPD_DIVIDENT
93 int "[10]: Medium Timebase (MTB) Dividend"
94 default 1
95 range 1 255
96
97config CUSTOM_SPD_DIVISOR
98 int "[11]: Medium Timebase (MTB) Divisor"
99 default 14
100 range 1 255
101
102config CUSTOM_SPD_TCK
103 int "[12]: SDRAM Minimum Cycle Time, tCK"
104 default 15
105 range 1 255
106
107config CUSTOM_SPD_CASLO
108 int "[14]: CAS Latencies Supported, Lower Byte"
109 default 124
110 range 0 255
111
112config CUSTOM_SPD_CASHI
113 int "[15]: CAS Latencies Supported, Higher Byte"
114 default 0
115 range 0 255
116
117config CUSTOM_SPD_TAA
118 int "[16]: Min CAS Latency Time, tAA"
119 default 132
120 range 1 255
121
122config CUSTOM_SPD_TWR
123 int "[17]: Min Write Recovery Time, tWR"
124 default 210
125 range 1 255
126
127config CUSTOM_SPD_TRCD
128 int "[18]: Min RAS# to CAS# Delay Time, tRCD"
129 default 132
130 range 1 255
131
132config CUSTOM_SPD_TRRD
133 int "[19]: Min Row Active to Row Active Delay Time, tRRD"
134 default 84
135 range 1 255
136
137config CUSTOM_SPD_TRP
138 int "[20]: Min Row Precharge Delay Time, tRP"
139 default 132
140 range 1 255
141
142config CUSTOM_SPD_UPPER_TRC
143 int "[21][7:4]: Min Active to Active/Refresh Delay, UPPER tRC"
144 default 2
145 range 0 16
146
147config CUSTOM_SPD_UPPER_TRAS
148 int "[21][3:0]: Min Active to Precharge Delay Time, UPPER tRAS"
149 default 1
150 range 0 16
151
152config CUSTOM_SPD_TRAS
153 int "[22]: Min Active to Precharge Delay Time, LOWER tRAS"
154 default 138
155 range 1 255
156
157config CUSTOM_SPD_TRC
158 int "[23]: Min Active to Active/Refresh Delay, LOWER tRC"
159 default 181
160 range 1 255
161
Mike Banonf7b410d2020-04-17 14:56:42 +0300[diff] [blame]162config CUSTOM_SPD_TWTR
163 int "[26]: Min Internal Write to Read Command Delay, tWTR"
164 default 105
165 range 1 255
166
167config CUSTOM_SPD_TRTP
168 int "[27]: Min Internal Read to Precharge Command Delay, tRTP"
169 default 105
170 range 1 255
171
172config CUSTOM_SPD_UPPER_TFAW
173 int "[28][3:0]: Min Four Activate Window Delay, UPPER tFAW"
174 default 1
175 range 0 16
176
177config CUSTOM_SPD_TFAW
178 int "[29]: Min Four Activate Window Delay Time, tFAW"
179 default 164
180 range 1 255
181
182endif