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review.coreboot.org / coreboot / 02d9c85e75aabfe46dbe8cce33190b98c17446ea / . / src / vendorcode / amd / agesa / Kconfig
blob: 2b894181bf86dc43a92714201753453c0b21a3e4 [file] [log] [blame]
Mike Banon3ee99352020-04-17 14:35:20 +0300[diff] [blame]1# SPDX-License-Identifier: GPL-2.0-only
Mike Banon3ee99352020-04-17 14:35:20 +0300[diff] [blame]2
Angel Pons02d9c852021-05-09 15:07:18 +0200[diff] [blame^]3config IDS_OPTIONS_HOOKED_UP
4 bool
5 help
6 to Kconfig options.
7 Historically, IDS configuration was defined in a mainboard-specific
8 `OptionsIds.h` header. Select this on platforms where IDS config is
9 hooked up to Kconfig options instead.
10
11if IDS_OPTIONS_HOOKED_UP
12
13config IDS_ENABLED
14 bool "Enable AGESA IDS (Integrated Debug Services) support"
15 default y
16 help
17 This is the master switch for the IDS sub-system. Use this option to
18 enable or remove the entire IDS feature set. This switch must be TRUE
19 for any of the other options to function.
20
21comment "Warning: IDS options may not work. Enable at your own risk!"
22 depends on IDS_ENABLED
23
24config IDS_CONTROL_ENABLED
25 bool "Enable IDS User Interface controls"
26 depends on IDS_ENABLED
27 help
28 This is the main switch for the IDS configuration controls. This
29 switch must be TRUE for any of the configuration controls to function.
30
31 This seems to allow AGESA to retrieve settings from CMOS.
32
33config IDS_PERF_ANALYSIS
34 bool "Enable IDS performance analysis"
35 depends on IDS_ENABLED
36 help
37 This is the main switch for the IDS performance analysis controls,
38 macros and support code needed to enable time data gathering. This
39 switch must be TRUE for any of the performance analysis features to
40 function.
41
42config IDS_TRACING_ENABLED
43 bool "Enable IDS console"
44 depends on IDS_ENABLED
45 help
46 This is the main switch for the IDS console controls, macros and
47 support code needed to enable tracing of algorithms. This switch
48 must be TRUE for any of the tracing features to function.
49
50config IDS_TRACING_CONSOLE_SERIAL
51 bool "Use serial port as IDS console"
52 depends on IDS_TRACING_ENABLED
53 default DRIVERS_UART_8250IO && CONSOLE_SERIAL
54 help
55 Use an I/O-mapped serial port to output IDS messages.
56
57endif # IDS_OPTIONS_HOOKED_UP
58
Mike Banon3ee99352020-04-17 14:35:20 +0300[diff] [blame]59choice
60 prompt "DDR3 memory profile"
61 default CPU_AMD_AGESA_OPENSOURCE_MEM_JEDEC
62 help
63 Choose the DDR3 memory profile to use for your RAM sticks, e.g. XMP 1.
64 XMP support is experimental, and your PC will fail booting if you choose
65 a profile which does not exist on ANY of your RAM sticks! If in doubt
66 check their SPD Data using a coreboot's great fork of memtest86+ 5.01.
67
68config CPU_AMD_AGESA_OPENSOURCE_MEM_JEDEC
69 bool "JEDEC"
70 help
71 JEDEC memory profile, standard and stable. Is guaranteed to be working.
72
73config CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_1
74 bool "XMP 1"
75 help
76 XMP 1 memory profile. Check that it exists on ALL of your RAM sticks!
77
78config CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_2
79 bool "XMP 2"
80 help
81 XMP 2 memory profile. Check that it exists on ALL of your RAM sticks!
82
Mike Banonf7b410d2020-04-17 14:56:42 +0300[diff] [blame]83config CPU_AMD_AGESA_OPENSOURCE_MEM_CUSTOM
84 bool "CUSTOM"
85 help
86 Custom memory profile. Use the XMP SPD values as the base, if available.
87
88if CPU_AMD_AGESA_OPENSOURCE_MEM_CUSTOM
89
90config CUSTOM_SPD_DIVIDENT
91 int "[10]: Medium Timebase (MTB) Dividend"
92 default 1
93 range 1 255
94
95config CUSTOM_SPD_DIVISOR
96 int "[11]: Medium Timebase (MTB) Divisor"
97 default 14
98 range 1 255
99
100config CUSTOM_SPD_TCK
101 int "[12]: SDRAM Minimum Cycle Time, tCK"
102 default 15
103 range 1 255
104
105config CUSTOM_SPD_CASLO
106 int "[14]: CAS Latencies Supported, Lower Byte"
107 default 124
108 range 0 255
109
110config CUSTOM_SPD_CASHI
111 int "[15]: CAS Latencies Supported, Higher Byte"
112 default 0
113 range 0 255
114
115config CUSTOM_SPD_TAA
116 int "[16]: Min CAS Latency Time, tAA"
117 default 132
118 range 1 255
119
120config CUSTOM_SPD_TWR
121 int "[17]: Min Write Recovery Time, tWR"
122 default 210
123 range 1 255
124
125config CUSTOM_SPD_TRCD
126 int "[18]: Min RAS# to CAS# Delay Time, tRCD"
127 default 132
128 range 1 255
129
130config CUSTOM_SPD_TRRD
131 int "[19]: Min Row Active to Row Active Delay Time, tRRD"
132 default 84
133 range 1 255
134
135config CUSTOM_SPD_TRP
136 int "[20]: Min Row Precharge Delay Time, tRP"
137 default 132
138 range 1 255
139
140config CUSTOM_SPD_UPPER_TRC
141 int "[21][7:4]: Min Active to Active/Refresh Delay, UPPER tRC"
142 default 2
143 range 0 16
144
145config CUSTOM_SPD_UPPER_TRAS
146 int "[21][3:0]: Min Active to Precharge Delay Time, UPPER tRAS"
147 default 1
148 range 0 16
149
150config CUSTOM_SPD_TRAS
151 int "[22]: Min Active to Precharge Delay Time, LOWER tRAS"
152 default 138
153 range 1 255
154
155config CUSTOM_SPD_TRC
156 int "[23]: Min Active to Active/Refresh Delay, LOWER tRC"
157 default 181
158 range 1 255
159
160if CPU_AMD_AGESA_FAMILY16_KB
161
162config CUSTOM_SPD_TRFC_LO
163 int "[24]: Min Refresh Recovery Delay Time, LOWER tRFC"
164 default 56
165 range 1 255
166
167config CUSTOM_SPD_TRFC_HI
168 int "[25]: Min Refresh Recovery Delay Time, UPPER tRFC"
169 default 14
170 range 0 255
171
172endif
173
174config CUSTOM_SPD_TWTR
175 int "[26]: Min Internal Write to Read Command Delay, tWTR"
176 default 105
177 range 1 255
178
179config CUSTOM_SPD_TRTP
180 int "[27]: Min Internal Read to Precharge Command Delay, tRTP"
181 default 105
182 range 1 255
183
184config CUSTOM_SPD_UPPER_TFAW
185 int "[28][3:0]: Min Four Activate Window Delay, UPPER tFAW"
186 default 1
187 range 0 16
188
189config CUSTOM_SPD_TFAW
190 int "[29]: Min Four Activate Window Delay Time, tFAW"
191 default 164
192 range 1 255
193
194endif
195
Mike Banon3ee99352020-04-17 14:35:20 +0300[diff] [blame]196endchoice