Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2008-2009 coresystems GmbH |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | #include <console/console.h> |
Kyösti Mälkki | ab56b3b | 2013-11-28 16:44:51 +0200 | [diff] [blame] | 17 | #include <bootmode.h> |
Patrick Georgi | 6444bd4 | 2012-07-06 11:31:39 +0200 | [diff] [blame] | 18 | #include <delay.h> |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 19 | #include <device/device.h> |
| 20 | #include <device/pci.h> |
| 21 | #include <device/pci_ids.h> |
Sven Schnelle | b629d14 | 2011-06-12 14:30:10 +0200 | [diff] [blame] | 22 | #include <pc80/mc146818rtc.h> |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 23 | #include <edid.h> |
| 24 | #include <drivers/intel/gma/edid.h> |
| 25 | #include <drivers/intel/gma/i915.h> |
| 26 | #include <string.h> |
Vladimir Serbinenko | 0092c99 | 2014-08-21 01:06:53 +0200 | [diff] [blame] | 27 | #include <pc80/vga.h> |
| 28 | #include <pc80/vga_io.h> |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 29 | |
Patrick Georgi | ce6e9fe | 2012-07-20 12:37:06 +0200 | [diff] [blame] | 30 | #include "i945.h" |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 31 | #include "chip.h" |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 32 | |
Patrick Georgi | 6444bd4 | 2012-07-06 11:31:39 +0200 | [diff] [blame] | 33 | #define GDRST 0xc0 |
| 34 | |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 35 | #define LVDS_CLOCK_A_POWERUP_ALL (3 << 8) |
| 36 | #define LVDS_CLOCK_B_POWERUP_ALL (3 << 4) |
| 37 | #define LVDS_CLOCK_BOTH_POWERUP_ALL (3 << 2) |
| 38 | #define DISPPLANE_BGRX888 (0x6<<26) |
| 39 | #define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */ |
| 40 | |
| 41 | #define DPLL_INTEGRATED_CRI_CLK_VLV (1<<14) |
| 42 | |
| 43 | #define PGETBL_CTL 0x2020 |
| 44 | #define PGETBL_ENABLED 0x00000001 |
| 45 | |
| 46 | #define BASE_FREQUENCY 120000 |
| 47 | |
| 48 | #if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT |
| 49 | |
Francis Rowe | 71512b2 | 2015-03-16 05:31:40 +0000 | [diff] [blame] | 50 | static int gtt_setup(void *mmiobase) |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 51 | { |
| 52 | unsigned long PGETBL_save; |
Paul Menzel | cc95f18 | 2014-06-05 22:45:35 +0200 | [diff] [blame] | 53 | unsigned long tom; // top of memory |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 54 | |
Paul Menzel | cc95f18 | 2014-06-05 22:45:35 +0200 | [diff] [blame] | 55 | /* |
| 56 | * The Video BIOS places the GTT right below top of memory. |
Denis 'GNUtoo' Carikli | 16110e7 | 2014-10-14 07:33:53 +0200 | [diff] [blame] | 57 | */ |
Paul Menzel | cc95f18 | 2014-06-05 22:45:35 +0200 | [diff] [blame] | 58 | tom = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), TOLUD) << 24; |
| 59 | PGETBL_save = tom - 256 * KiB; |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 60 | PGETBL_save |= PGETBL_ENABLED; |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 61 | PGETBL_save |= 2; /* set GTT to 256kb */ |
| 62 | |
| 63 | write32(mmiobase + GFX_FLSH_CNTL, 0); |
| 64 | |
| 65 | write32(mmiobase + PGETBL_CTL, PGETBL_save); |
| 66 | |
| 67 | /* verify */ |
| 68 | if (read32(mmiobase + PGETBL_CTL) & PGETBL_ENABLED) { |
| 69 | printk(BIOS_DEBUG, "gtt_setup is enabled.\n"); |
| 70 | } else { |
| 71 | printk(BIOS_DEBUG, "gtt_setup failed!!!\n"); |
| 72 | return 1; |
| 73 | } |
| 74 | write32(mmiobase + GFX_FLSH_CNTL, 0); |
| 75 | |
| 76 | return 0; |
| 77 | } |
| 78 | |
| 79 | static int intel_gma_init(struct northbridge_intel_i945_config *conf, |
| 80 | unsigned int pphysbase, unsigned int piobase, |
Francis Rowe | 71512b2 | 2015-03-16 05:31:40 +0000 | [diff] [blame] | 81 | void *pmmio, unsigned int pgfx) |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 82 | { |
| 83 | struct edid edid; |
Mono | 2e4f83b | 2015-09-07 21:15:26 +0200 | [diff] [blame] | 84 | struct edid_mode *mode; |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 85 | u8 edid_data[128]; |
| 86 | unsigned long temp; |
| 87 | int hpolarity, vpolarity; |
| 88 | u32 candp1, candn; |
| 89 | u32 best_delta = 0xffffffff; |
| 90 | u32 target_frequency; |
| 91 | u32 pixel_p1 = 1; |
| 92 | u32 pixel_n = 1; |
| 93 | u32 pixel_m1 = 1; |
| 94 | u32 pixel_m2 = 1; |
| 95 | u32 hactive, vactive, right_border, bottom_border; |
| 96 | u32 vsync, hsync, vblank, hblank, hfront_porch, vfront_porch; |
| 97 | u32 i, j; |
| 98 | u32 uma_size; |
| 99 | u16 reg16; |
| 100 | |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 101 | printk(BIOS_SPEW, |
Francis Rowe | 71512b2 | 2015-03-16 05:31:40 +0000 | [diff] [blame] | 102 | "i915lightup: graphics %p mmio %p addrport %04x physbase %08x\n", |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 103 | (void *)pgfx, pmmio, piobase, pphysbase); |
| 104 | |
| 105 | intel_gmbus_read_edid(pmmio + GMBUS0, 3, 0x50, edid_data, 128); |
| 106 | decode_edid(edid_data, sizeof(edid_data), &edid); |
Mono | 2e4f83b | 2015-09-07 21:15:26 +0200 | [diff] [blame] | 107 | mode = &edid.mode; |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 108 | |
Mono | 2e4f83b | 2015-09-07 21:15:26 +0200 | [diff] [blame] | 109 | hpolarity = (mode->phsync == '-'); |
| 110 | vpolarity = (mode->pvsync == '-'); |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 111 | hactive = edid.x_resolution; |
| 112 | vactive = edid.y_resolution; |
Mono | 2e4f83b | 2015-09-07 21:15:26 +0200 | [diff] [blame] | 113 | right_border = mode->hborder; |
| 114 | bottom_border = mode->vborder; |
| 115 | vblank = mode->vbl; |
| 116 | hblank = mode->hbl; |
| 117 | vsync = mode->vspw; |
| 118 | hsync = mode->hspw; |
| 119 | hfront_porch = mode->hso; |
| 120 | vfront_porch = mode->vso; |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 121 | |
| 122 | for (i = 0; i < 2; i++) |
| 123 | for (j = 0; j < 0x100; j++) |
Elyes HAOUAS | 0a15fe9 | 2016-09-17 19:12:27 +0200 | [diff] [blame] | 124 | /* R = j, G = j, B = j. */ |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 125 | write32(pmmio + PALETTE(i) + 4 * j, 0x10101 * j); |
| 126 | |
| 127 | write32(pmmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS |
| 128 | | (read32(pmmio + PCH_PP_CONTROL) & ~PANEL_UNLOCK_MASK)); |
| 129 | |
| 130 | write32(pmmio + MI_ARB_STATE, MI_ARB_C3_LP_WRITE_ENABLE | (1 << 27)); |
| 131 | /* Clean registers. */ |
| 132 | for (i = 0; i < 0x20; i += 4) |
| 133 | write32(pmmio + RENDER_RING_BASE + i, 0); |
| 134 | for (i = 0; i < 0x20; i += 4) |
| 135 | write32(pmmio + FENCE_REG_965_0 + i, 0); |
| 136 | write32(pmmio + PP_ON_DELAYS, 0); |
| 137 | write32(pmmio + PP_OFF_DELAYS, 0); |
| 138 | |
| 139 | /* Disable VGA. */ |
| 140 | write32(pmmio + VGACNTRL, VGA_DISP_DISABLE); |
| 141 | |
| 142 | /* Disable pipes. */ |
| 143 | write32(pmmio + PIPECONF(0), 0); |
| 144 | write32(pmmio + PIPECONF(1), 0); |
| 145 | |
| 146 | /* Init PRB0. */ |
| 147 | write32(pmmio + HWS_PGA, 0x352d2000); |
| 148 | write32(pmmio + PRB0_CTL, 0); |
| 149 | write32(pmmio + PRB0_HEAD, 0); |
| 150 | write32(pmmio + PRB0_TAIL, 0); |
| 151 | write32(pmmio + PRB0_START, 0); |
| 152 | write32(pmmio + PRB0_CTL, 0x0001f001); |
| 153 | |
| 154 | write32(pmmio + D_STATE, DSTATE_PLL_D3_OFF |
| 155 | | DSTATE_GFX_CLOCK_GATING | DSTATE_DOT_CLOCK_GATING); |
| 156 | write32(pmmio + ECOSKPD, 0x00010000); |
| 157 | write32(pmmio + HWSTAM, 0xeffe); |
| 158 | write32(pmmio + PORT_HOTPLUG_EN, conf->gpu_hotplug); |
| 159 | write32(pmmio + INSTPM, 0x08000000 | INSTPM_AGPBUSY_DIS); |
| 160 | |
Vladimir Serbinenko | 551cff0 | 2015-10-10 23:58:08 +0200 | [diff] [blame] | 161 | target_frequency = mode->lvds_dual_channel ? mode->pixel_clock |
Mono | 2e4f83b | 2015-09-07 21:15:26 +0200 | [diff] [blame] | 162 | : (2 * mode->pixel_clock); |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 163 | |
| 164 | /* Find suitable divisors. */ |
| 165 | for (candp1 = 1; candp1 <= 8; candp1++) { |
| 166 | for (candn = 5; candn <= 10; candn++) { |
| 167 | u32 cur_frequency; |
| 168 | u32 m; /* 77 - 131. */ |
| 169 | u32 denom; /* 35 - 560. */ |
| 170 | u32 current_delta; |
| 171 | |
| 172 | denom = candn * candp1 * 7; |
| 173 | /* Doesnt overflow for up to |
| 174 | 5000000 kHz = 5 GHz. */ |
| 175 | m = (target_frequency * denom |
| 176 | + BASE_FREQUENCY / 2) / BASE_FREQUENCY; |
| 177 | |
| 178 | if (m < 77 || m > 131) |
| 179 | continue; |
| 180 | |
| 181 | cur_frequency = (BASE_FREQUENCY * m) / denom; |
| 182 | if (target_frequency > cur_frequency) |
| 183 | current_delta = target_frequency - cur_frequency; |
| 184 | else |
| 185 | current_delta = cur_frequency - target_frequency; |
| 186 | |
| 187 | if (best_delta > current_delta) { |
| 188 | best_delta = current_delta; |
| 189 | pixel_n = candn; |
| 190 | pixel_p1 = candp1; |
| 191 | pixel_m2 = ((m + 3) % 5) + 7; |
| 192 | pixel_m1 = (m - pixel_m2) / 5; |
| 193 | } |
| 194 | } |
| 195 | } |
| 196 | |
| 197 | if (best_delta == 0xffffffff) { |
| 198 | printk (BIOS_ERR, "Couldn't find GFX clock divisors\n"); |
| 199 | return -1; |
| 200 | } |
| 201 | |
| 202 | printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", |
| 203 | hactive, vactive); |
| 204 | printk(BIOS_DEBUG, "Borders %d x %d\n", right_border, bottom_border); |
| 205 | printk(BIOS_DEBUG, "Blank %d x %d\n", hblank, vblank); |
| 206 | printk(BIOS_DEBUG, "Sync %d x %d\n", hsync, vsync); |
| 207 | printk(BIOS_DEBUG, "Front porch %d x %d\n", hfront_porch, vfront_porch); |
| 208 | printk(BIOS_DEBUG, (conf->gpu_lvds_use_spread_spectrum_clock |
| 209 | ? "Spread spectrum clock\n" |
| 210 | : "DREF clock\n")); |
Vladimir Serbinenko | 551cff0 | 2015-10-10 23:58:08 +0200 | [diff] [blame] | 211 | printk(BIOS_DEBUG, (mode->lvds_dual_channel |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 212 | ? "Dual channel\n" |
| 213 | : "Single channel\n")); |
| 214 | printk(BIOS_DEBUG, "Polarities %d, %d\n", |
| 215 | hpolarity, vpolarity); |
| 216 | printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n", |
| 217 | pixel_n, pixel_m1, pixel_m2, pixel_p1); |
| 218 | printk(BIOS_DEBUG, "Pixel clock %d kHz\n", |
| 219 | BASE_FREQUENCY * (5 * pixel_m1 + pixel_m2) / pixel_n |
| 220 | / (pixel_p1 * 7)); |
| 221 | |
Vladimir Serbinenko | 0092c99 | 2014-08-21 01:06:53 +0200 | [diff] [blame] | 222 | #if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) |
| 223 | write32(pmmio + PF_WIN_SZ(0), vactive | (hactive << 16)); |
| 224 | write32(pmmio + PF_WIN_POS(0), 0); |
| 225 | write32(pmmio + PF_CTL(0),PF_ENABLE | PF_FILTER_MED_3x3); |
| 226 | write32(pmmio + PFIT_CONTROL, PFIT_ENABLE | (1 << PFIT_PIPE_SHIFT) | HORIZ_AUTO_SCALE | VERT_AUTO_SCALE); |
| 227 | #else |
| 228 | /* Disable panel fitter (we're in native resolution). */ |
| 229 | write32(pmmio + PF_CTL(0), 0); |
| 230 | write32(pmmio + PF_WIN_SZ(0), 0); |
| 231 | write32(pmmio + PF_WIN_POS(0), 0); |
| 232 | write32(pmmio + PFIT_PGM_RATIOS, 0); |
| 233 | write32(pmmio + PFIT_CONTROL, 0); |
| 234 | #endif |
| 235 | |
| 236 | mdelay(1); |
| 237 | |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 238 | write32(pmmio + DSPCNTR(0), DISPPLANE_BGRX888 |
| 239 | | DISPPLANE_SEL_PIPE_B | DISPPLANE_GAMMA_ENABLE); |
| 240 | |
| 241 | mdelay(1); |
| 242 | write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS |
| 243 | | (read32(pmmio + PP_CONTROL) & ~PANEL_UNLOCK_MASK)); |
| 244 | write32(pmmio + FP0(1), |
| 245 | ((pixel_n - 2) << 16) |
| 246 | | ((pixel_m1 - 2) << 8) | pixel_m2); |
| 247 | write32(pmmio + DPLL(1), |
| 248 | DPLL_VGA_MODE_DIS | |
| 249 | DPLL_VCO_ENABLE | DPLLB_MODE_LVDS |
Vladimir Serbinenko | 551cff0 | 2015-10-10 23:58:08 +0200 | [diff] [blame] | 250 | | (mode->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 251 | : DPLLB_LVDS_P2_CLOCK_DIV_14) |
| 252 | | (conf->gpu_lvds_use_spread_spectrum_clock |
| 253 | ? DPLL_INTEGRATED_CLOCK_VLV | DPLL_INTEGRATED_CRI_CLK_VLV |
| 254 | : 0) |
| 255 | | (pixel_p1 << 16) |
| 256 | | (pixel_p1)); |
| 257 | mdelay(1); |
| 258 | write32(pmmio + DPLL(1), |
| 259 | DPLL_VGA_MODE_DIS | |
| 260 | DPLL_VCO_ENABLE | DPLLB_MODE_LVDS |
Vladimir Serbinenko | 551cff0 | 2015-10-10 23:58:08 +0200 | [diff] [blame] | 261 | | (mode->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 262 | : DPLLB_LVDS_P2_CLOCK_DIV_14) |
| 263 | | ((conf->gpu_lvds_use_spread_spectrum_clock ? 3 : 0) << 13) |
| 264 | | (pixel_p1 << 16) |
| 265 | | (pixel_p1)); |
| 266 | mdelay(1); |
| 267 | write32(pmmio + HTOTAL(1), |
| 268 | ((hactive + right_border + hblank - 1) << 16) |
| 269 | | (hactive - 1)); |
| 270 | write32(pmmio + HBLANK(1), |
| 271 | ((hactive + right_border + hblank - 1) << 16) |
| 272 | | (hactive + right_border - 1)); |
| 273 | write32(pmmio + HSYNC(1), |
| 274 | ((hactive + right_border + hfront_porch + hsync - 1) << 16) |
| 275 | | (hactive + right_border + hfront_porch - 1)); |
| 276 | |
| 277 | write32(pmmio + VTOTAL(1), ((vactive + bottom_border + vblank - 1) << 16) |
| 278 | | (vactive - 1)); |
| 279 | write32(pmmio + VBLANK(1), ((vactive + bottom_border + vblank - 1) << 16) |
| 280 | | (vactive + bottom_border - 1)); |
| 281 | write32(pmmio + VSYNC(1), |
| 282 | (vactive + bottom_border + vfront_porch + vsync - 1) |
| 283 | | (vactive + bottom_border + vfront_porch - 1)); |
| 284 | |
Vladimir Serbinenko | 0092c99 | 2014-08-21 01:06:53 +0200 | [diff] [blame] | 285 | #if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) |
| 286 | write32(pmmio + PIPESRC(1), (639 << 16) | 399); |
| 287 | #else |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 288 | write32(pmmio + PIPESRC(1), ((hactive - 1) << 16) | (vactive - 1)); |
Vladimir Serbinenko | 0092c99 | 2014-08-21 01:06:53 +0200 | [diff] [blame] | 289 | #endif |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 290 | mdelay(1); |
| 291 | |
| 292 | write32(pmmio + DSPSIZE(0), (hactive - 1) | ((vactive - 1) << 16)); |
| 293 | write32(pmmio + DSPPOS(0), 0); |
| 294 | |
| 295 | /* Backlight init. */ |
| 296 | write32(pmmio + FW_BLC_SELF, FW_BLC_SELF_EN_MASK); |
| 297 | write32(pmmio + FW_BLC, 0x011d011a); |
| 298 | write32(pmmio + FW_BLC2, 0x00000102); |
| 299 | write32(pmmio + FW_BLC_SELF, FW_BLC_SELF_EN_MASK); |
| 300 | write32(pmmio + FW_BLC_SELF, 0x0001003f); |
| 301 | write32(pmmio + FW_BLC, 0x011d0109); |
| 302 | write32(pmmio + FW_BLC2, 0x00000102); |
| 303 | write32(pmmio + FW_BLC_SELF, FW_BLC_SELF_EN_MASK); |
| 304 | write32(pmmio + BLC_PWM_CTL, conf->gpu_backlight); |
| 305 | |
| 306 | edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63; |
| 307 | write32(pmmio + DSPADDR(0), 0); |
| 308 | write32(pmmio + DSPSURF(0), 0); |
| 309 | write32(pmmio + DSPSTRIDE(0), edid.bytes_per_line); |
| 310 | write32(pmmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888 |
| 311 | | DISPPLANE_SEL_PIPE_B | DISPPLANE_GAMMA_ENABLE); |
| 312 | mdelay(1); |
| 313 | |
| 314 | write32(pmmio + PIPECONF(1), PIPECONF_ENABLE); |
| 315 | write32(pmmio + LVDS, LVDS_ON |
| 316 | | (hpolarity << 20) | (vpolarity << 21) |
Vladimir Serbinenko | 551cff0 | 2015-10-10 23:58:08 +0200 | [diff] [blame] | 317 | | (mode->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 318 | | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) |
| 319 | | LVDS_CLOCK_A_POWERUP_ALL |
| 320 | | LVDS_PIPE(1)); |
| 321 | |
| 322 | write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_OFF); |
| 323 | write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_RESET); |
| 324 | mdelay(1); |
| 325 | write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS |
| 326 | | PANEL_POWER_ON | PANEL_POWER_RESET); |
| 327 | |
| 328 | printk (BIOS_DEBUG, "waiting for panel powerup\n"); |
| 329 | while (1) { |
| 330 | u32 reg32; |
| 331 | reg32 = read32(pmmio + PP_STATUS); |
| 332 | if ((reg32 & PP_SEQUENCE_MASK) == PP_SEQUENCE_NONE) |
| 333 | break; |
| 334 | } |
| 335 | printk (BIOS_DEBUG, "panel powered up\n"); |
| 336 | |
| 337 | write32(pmmio + PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET); |
| 338 | |
| 339 | /* Clear interrupts. */ |
| 340 | write32(pmmio + DEIIR, 0xffffffff); |
| 341 | write32(pmmio + SDEIIR, 0xffffffff); |
| 342 | write32(pmmio + IIR, 0xffffffff); |
| 343 | write32(pmmio + IMR, 0xffffffff); |
| 344 | write32(pmmio + EIR, 0xffffffff); |
| 345 | |
| 346 | if (gtt_setup(pmmio)) { |
| 347 | printk(BIOS_ERR, "ERROR: GTT Setup Failed!!!\n"); |
| 348 | return 0; |
| 349 | } |
| 350 | |
| 351 | /* Setup GTT. */ |
| 352 | |
| 353 | reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)), GGC); |
| 354 | uma_size = 0; |
| 355 | if (!(reg16 & 2)) { |
Arthur Heymans | 874a8f9 | 2016-05-19 16:06:09 +0200 | [diff] [blame] | 356 | uma_size = decode_igd_memory_size((reg16 >> 4) & 7); |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 357 | printk(BIOS_DEBUG, "%dM UMA\n", uma_size >> 10); |
| 358 | } |
| 359 | |
Vladimir Serbinenko | 055fe03 | 2014-08-19 23:59:27 +0200 | [diff] [blame] | 360 | for (i = 0; i < (uma_size - 256) / 4; i++) |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 361 | { |
| 362 | outl((i << 2) | 1, piobase); |
| 363 | outl(pphysbase + (i << 12) + 1, piobase + 4); |
| 364 | } |
| 365 | |
| 366 | temp = read32(pmmio + PGETBL_CTL); |
| 367 | printk(BIOS_INFO, "GTT PGETBL_CTL register: 0x%lx\n", temp); |
| 368 | |
| 369 | if (temp & 1) |
| 370 | printk(BIOS_INFO, "GTT Enabled\n"); |
| 371 | else |
| 372 | printk(BIOS_ERR, "ERROR: GTT is still Disabled!!!\n"); |
| 373 | |
Vladimir Serbinenko | 0092c99 | 2014-08-21 01:06:53 +0200 | [diff] [blame] | 374 | #if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) |
| 375 | vga_misc_write(0x67); |
| 376 | |
| 377 | write32(pmmio + DSPCNTR(0), DISPPLANE_SEL_PIPE_B); |
| 378 | |
| 379 | write32(pmmio + VGACNTRL, 0x02c4008e | VGA_PIPE_B_SELECT); |
| 380 | |
| 381 | vga_textmode_init(); |
| 382 | #else |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 383 | printk(BIOS_SPEW, "memset %p to 0x00 for %d bytes\n", |
| 384 | (void *)pgfx, hactive * vactive * 4); |
| 385 | memset((void *)pgfx, 0x00, hactive * vactive * 4); |
| 386 | |
| 387 | set_vbe_mode_info_valid(&edid, pgfx); |
Vladimir Serbinenko | 0092c99 | 2014-08-21 01:06:53 +0200 | [diff] [blame] | 388 | #endif |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 389 | return 0; |
| 390 | } |
| 391 | #endif |
| 392 | |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 393 | static void gma_func0_init(struct device *dev) |
| 394 | { |
| 395 | u32 reg32; |
| 396 | |
Patrick Georgi | 6444bd4 | 2012-07-06 11:31:39 +0200 | [diff] [blame] | 397 | /* Unconditionally reset graphics */ |
| 398 | pci_write_config8(dev, GDRST, 1); |
| 399 | udelay(50); |
| 400 | pci_write_config8(dev, GDRST, 0); |
| 401 | /* wait for device to finish */ |
| 402 | while (pci_read_config8(dev, GDRST) & 1) { }; |
| 403 | |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 404 | /* IGD needs to be Bus Master */ |
| 405 | reg32 = pci_read_config32(dev, PCI_COMMAND); |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 406 | pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER |
| 407 | | PCI_COMMAND_IO | PCI_COMMAND_MEMORY); |
Denis 'GNUtoo' Carikli | ed7e29e | 2013-02-24 12:01:44 +0100 | [diff] [blame] | 408 | |
| 409 | #if !CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT |
| 410 | /* PCI Init, will run VBIOS */ |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 411 | pci_dev_init(dev); |
Denis 'GNUtoo' Carikli | ed7e29e | 2013-02-24 12:01:44 +0100 | [diff] [blame] | 412 | #endif |
| 413 | |
| 414 | |
| 415 | #if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT |
| 416 | /* This should probably run before post VBIOS init. */ |
| 417 | printk(BIOS_SPEW, "Initializing VGA without OPROM.\n"); |
Francis Rowe | 71512b2 | 2015-03-16 05:31:40 +0000 | [diff] [blame] | 418 | void *mmiobase; |
| 419 | u32 iobase, graphics_base; |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 420 | struct northbridge_intel_i945_config *conf = dev->chip_info; |
| 421 | |
Denis 'GNUtoo' Carikli | ed7e29e | 2013-02-24 12:01:44 +0100 | [diff] [blame] | 422 | iobase = dev->resource_list[1].base; |
Francis Rowe | 71512b2 | 2015-03-16 05:31:40 +0000 | [diff] [blame] | 423 | mmiobase = (void *)(uintptr_t)dev->resource_list[0].base; |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 424 | graphics_base = dev->resource_list[2].base; |
Denis 'GNUtoo' Carikli | ed7e29e | 2013-02-24 12:01:44 +0100 | [diff] [blame] | 425 | |
Elyes HAOUAS | 0a15fe9 | 2016-09-17 19:12:27 +0200 | [diff] [blame] | 426 | printk(BIOS_SPEW, "GMADR = 0x%08x GTTADR = 0x%08x\n", |
Paul Menzel | d235da1 | 2014-06-03 00:15:30 +0200 | [diff] [blame] | 427 | pci_read_config32(dev, GMADR), |
| 428 | pci_read_config32(dev, GTTADR) |
Peter Stuge | c6f0997 | 2013-06-08 01:31:44 +0200 | [diff] [blame] | 429 | ); |
| 430 | |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 431 | int err; |
| 432 | err = intel_gma_init(conf, pci_read_config32(dev, 0x5c) & ~0xf, |
| 433 | iobase, mmiobase, graphics_base); |
| 434 | if (err == 0) |
Kyösti Mälkki | ab56b3b | 2013-11-28 16:44:51 +0200 | [diff] [blame] | 435 | gfx_set_init_done(1); |
Arthur Heymans | 333176e | 2016-09-07 22:10:57 +0200 | [diff] [blame] | 436 | /* Linux relies on VBT for panel info. */ |
| 437 | if (CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM) { |
| 438 | generate_fake_intel_oprom(&conf->gfx, dev, |
| 439 | "$VBT CALISTOGA"); |
| 440 | } |
| 441 | if (CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC) { |
| 442 | generate_fake_intel_oprom(&conf->gfx, dev, |
| 443 | "$VBT LAKEPORT-G"); |
| 444 | } |
Denis 'GNUtoo' Carikli | ed7e29e | 2013-02-24 12:01:44 +0100 | [diff] [blame] | 445 | #endif |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 446 | } |
| 447 | |
Patrick Georgi | ce6e9fe | 2012-07-20 12:37:06 +0200 | [diff] [blame] | 448 | /* This doesn't reclaim stolen UMA memory, but IGD could still |
| 449 | be reenabled later. */ |
| 450 | static void gma_func0_disable(struct device *dev) |
| 451 | { |
| 452 | struct device *dev_host = dev_find_slot(0, PCI_DEVFN(0x0, 0)); |
| 453 | |
| 454 | pci_write_config16(dev, GCFC, 0xa00); |
| 455 | pci_write_config16(dev_host, GGC, (1 << 1)); |
| 456 | |
| 457 | unsigned int reg32 = pci_read_config32(dev_host, DEVEN); |
| 458 | reg32 &= ~(DEVEN_D2F0 | DEVEN_D2F1); |
| 459 | pci_write_config32(dev_host, DEVEN, reg32); |
| 460 | |
| 461 | dev->enabled = 0; |
| 462 | } |
| 463 | |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 464 | static void gma_func1_init(struct device *dev) |
| 465 | { |
| 466 | u32 reg32; |
Alexander Couzens | c7a1a3e | 2016-03-09 10:42:58 +0100 | [diff] [blame] | 467 | u8 val; |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 468 | |
| 469 | /* IGD needs to be Bus Master, also enable IO accesss */ |
| 470 | reg32 = pci_read_config32(dev, PCI_COMMAND); |
Stefan Reinauer | 109ab31 | 2009-08-12 16:08:05 +0000 | [diff] [blame] | 471 | pci_write_config32(dev, PCI_COMMAND, reg32 | |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 472 | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); |
Sven Schnelle | b629d14 | 2011-06-12 14:30:10 +0200 | [diff] [blame] | 473 | |
Alexander Couzens | c7a1a3e | 2016-03-09 10:42:58 +0100 | [diff] [blame] | 474 | if (get_option(&val, "tft_brightness") == CB_SUCCESS) |
| 475 | pci_write_config8(dev, 0xf4, val); |
| 476 | else |
| 477 | pci_write_config8(dev, 0xf4, 0xff); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 478 | } |
| 479 | |
| 480 | static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device) |
| 481 | { |
| 482 | if (!vendor || !device) { |
| 483 | pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, |
| 484 | pci_read_config32(dev, PCI_VENDOR_ID)); |
| 485 | } else { |
| 486 | pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, |
| 487 | ((device & 0xffff) << 16) | (vendor & 0xffff)); |
| 488 | } |
| 489 | } |
| 490 | |
Vladimir Serbinenko | dd2bc3f | 2014-10-31 09:16:31 +0100 | [diff] [blame] | 491 | const struct i915_gpu_controller_info * |
| 492 | intel_gma_get_controller_info(void) |
| 493 | { |
| 494 | device_t dev = dev_find_slot(0, PCI_DEVFN(0x2,0)); |
| 495 | if (!dev) { |
| 496 | return NULL; |
| 497 | } |
| 498 | struct northbridge_intel_i945_config *chip = dev->chip_info; |
Patrick Georgi | 54e227e | 2015-08-08 22:02:12 +0200 | [diff] [blame] | 499 | if (!chip) { |
| 500 | return NULL; |
| 501 | } |
Vladimir Serbinenko | dd2bc3f | 2014-10-31 09:16:31 +0100 | [diff] [blame] | 502 | return &chip->gfx; |
| 503 | } |
| 504 | |
Alexander Couzens | 5eea458 | 2015-04-12 22:18:55 +0200 | [diff] [blame] | 505 | static void gma_ssdt(device_t device) |
Vladimir Serbinenko | dd2bc3f | 2014-10-31 09:16:31 +0100 | [diff] [blame] | 506 | { |
| 507 | const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info(); |
| 508 | if (!gfx) { |
| 509 | return; |
| 510 | } |
| 511 | |
| 512 | drivers_intel_gma_displays_ssdt_generate(gfx); |
| 513 | } |
| 514 | |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 515 | static struct pci_operations gma_pci_ops = { |
| 516 | .set_subsystem = gma_set_subsystem, |
| 517 | }; |
| 518 | |
| 519 | static struct device_operations gma_func0_ops = { |
| 520 | .read_resources = pci_dev_read_resources, |
| 521 | .set_resources = pci_dev_set_resources, |
| 522 | .enable_resources = pci_dev_enable_resources, |
| 523 | .init = gma_func0_init, |
Vladimir Serbinenko | dd2bc3f | 2014-10-31 09:16:31 +0100 | [diff] [blame] | 524 | .acpi_fill_ssdt_generator = gma_ssdt, |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 525 | .scan_bus = 0, |
| 526 | .enable = 0, |
Patrick Georgi | ce6e9fe | 2012-07-20 12:37:06 +0200 | [diff] [blame] | 527 | .disable = gma_func0_disable, |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 528 | .ops_pci = &gma_pci_ops, |
| 529 | }; |
| 530 | |
| 531 | |
| 532 | static struct device_operations gma_func1_ops = { |
| 533 | .read_resources = pci_dev_read_resources, |
| 534 | .set_resources = pci_dev_set_resources, |
| 535 | .enable_resources = pci_dev_enable_resources, |
| 536 | .init = gma_func1_init, |
| 537 | .scan_bus = 0, |
| 538 | .enable = 0, |
| 539 | .ops_pci = &gma_pci_ops, |
| 540 | }; |
| 541 | |
Vladimir Serbinenko | 10dd0e3 | 2014-11-17 00:07:12 +0100 | [diff] [blame] | 542 | static const unsigned short pci_device_ids[] = { 0x27a2, 0x27ae, 0 }; |
| 543 | |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 544 | static const struct pci_driver i945_gma_func0_driver __pci_driver = { |
| 545 | .ops = &gma_func0_ops, |
| 546 | .vendor = PCI_VENDOR_ID_INTEL, |
Vladimir Serbinenko | 10dd0e3 | 2014-11-17 00:07:12 +0100 | [diff] [blame] | 547 | .devices = pci_device_ids, |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 548 | }; |
| 549 | |
| 550 | static const struct pci_driver i945_gma_func1_driver __pci_driver = { |
| 551 | .ops = &gma_func1_ops, |
| 552 | .vendor = PCI_VENDOR_ID_INTEL, |
| 553 | .device = 0x27a6, |
| 554 | }; |