Patrick Georgi | 7333a11 | 2020-05-08 20:48:04 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 2 | |
| 3 | /* |
| 4 | * ROMSIG At ROMBASE + 0x20000: |
zbao | c3b0b72 | 2016-02-19 13:47:31 +0800 | [diff] [blame] | 5 | * 0 4 8 C |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 6 | * +------------+---------------+----------------+------------+ |
| 7 | * | 0x55AA55AA |EC ROM Address |GEC ROM Address |USB3 ROM | |
| 8 | * +------------+---------------+----------------+------------+ |
zbao | c3b0b72 | 2016-02-19 13:47:31 +0800 | [diff] [blame] | 9 | * | PSPDIR ADDR|PSPDIR ADDR |<-- Field 0x14 could be either |
| 10 | * +------------+---------------+ 2nd PSP directory or PSP COMBO directory |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 11 | * EC ROM should be 64K aligned. |
| 12 | * |
Zheng Bao | 4fcc9f2 | 2015-11-20 12:29:04 +0800 | [diff] [blame] | 13 | * PSP directory (Where "PSPDIR ADDR" points) |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 14 | * +------------+---------------+----------------+------------+ |
| 15 | * | 'PSP$' | Fletcher | Count | Reserved | |
| 16 | * +------------+---------------+----------------+------------+ |
| 17 | * | 0 | size | Base address | Reserved | Pubkey |
| 18 | * +------------+---------------+----------------+------------+ |
| 19 | * | 1 | size | Base address | Reserved | Bootloader |
| 20 | * +------------+---------------+----------------+------------+ |
| 21 | * | 8 | size | Base address | Reserved | Smu Firmware |
| 22 | * +------------+---------------+----------------+------------+ |
| 23 | * | 3 | size | Base address | Reserved | Recovery Firmware |
| 24 | * +------------+---------------+----------------+------------+ |
| 25 | * | | |
| 26 | * | | |
| 27 | * | Other PSP Firmware | |
| 28 | * | | |
| 29 | * | | |
| 30 | * +------------+---------------+----------------+------------+ |
Zheng Bao | 4fcc9f2 | 2015-11-20 12:29:04 +0800 | [diff] [blame] | 31 | * |
zbao | c3b0b72 | 2016-02-19 13:47:31 +0800 | [diff] [blame] | 32 | * PSP Combo directory |
Zheng Bao | 4fcc9f2 | 2015-11-20 12:29:04 +0800 | [diff] [blame] | 33 | * +------------+---------------+----------------+------------+ |
zbao | 6e2f3d1 | 2016-02-19 13:34:59 +0800 | [diff] [blame] | 34 | * | 'PSP2' | Fletcher | Count |Look up mode| |
Zheng Bao | 4fcc9f2 | 2015-11-20 12:29:04 +0800 | [diff] [blame] | 35 | * +------------+---------------+----------------+------------+ |
zbao | c3a08a9 | 2016-03-02 14:47:27 +0800 | [diff] [blame] | 36 | * | R e s e r v e d | |
| 37 | * +------------+---------------+----------------+------------+ |
zbao | 6e2f3d1 | 2016-02-19 13:34:59 +0800 | [diff] [blame] | 38 | * | ID-Sel | PSP ID | PSPDIR ADDR | | 2nd PSP directory |
Zheng Bao | 4fcc9f2 | 2015-11-20 12:29:04 +0800 | [diff] [blame] | 39 | * +------------+---------------+----------------+------------+ |
zbao | 6e2f3d1 | 2016-02-19 13:34:59 +0800 | [diff] [blame] | 40 | * | ID-Sel | PSP ID | PSPDIR ADDR | | 3rd PSP directory |
Zheng Bao | 4fcc9f2 | 2015-11-20 12:29:04 +0800 | [diff] [blame] | 41 | * +------------+---------------+----------------+------------+ |
| 42 | * | | |
| 43 | * | Other PSP | |
| 44 | * | | |
| 45 | * +------------+---------------+----------------+------------+ |
| 46 | * |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 47 | */ |
| 48 | |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 49 | #include <fcntl.h> |
| 50 | #include <errno.h> |
Martin Roth | 37305e7 | 2020-04-07 14:16:39 -0600 | [diff] [blame] | 51 | #include <stdbool.h> |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 52 | #include <stdio.h> |
| 53 | #include <sys/stat.h> |
| 54 | #include <sys/types.h> |
| 55 | #include <unistd.h> |
| 56 | #include <string.h> |
| 57 | #include <stdlib.h> |
| 58 | #include <getopt.h> |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 59 | #include <libgen.h> |
Idwer Vollering | 93df1d9 | 2020-12-30 00:01:59 +0100 | [diff] [blame] | 60 | #include <stdint.h> |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 61 | |
| 62 | #include "amdfwtool.h" |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 63 | |
Martin Roth | 60f1551 | 2016-11-08 09:55:01 -0700 | [diff] [blame] | 64 | #define AMD_ROMSIG_OFFSET 0x20000 |
| 65 | #define MIN_ROM_KB 256 |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 66 | |
Martin Roth | cd15bc8 | 2016-11-08 11:34:02 -0700 | [diff] [blame] | 67 | #define ALIGN(val, by) (((val) + (by) - 1) & ~((by) - 1)) |
Marshall Dawson | 7c1e142 | 2019-04-11 09:44:43 -0600 | [diff] [blame] | 68 | #define _MAX(A, B) (((A) > (B)) ? (A) : (B)) |
| 69 | #define ERASE_ALIGNMENT 0x1000U |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 70 | #define TABLE_ALIGNMENT 0x1000U |
| 71 | #define BLOB_ALIGNMENT 0x100U |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 72 | #define TABLE_ERASE_ALIGNMENT _MAX(TABLE_ALIGNMENT, ERASE_ALIGNMENT) |
Marshall Dawson | 7c1e142 | 2019-04-11 09:44:43 -0600 | [diff] [blame] | 73 | #define BLOB_ERASE_ALIGNMENT _MAX(BLOB_ALIGNMENT, ERASE_ALIGNMENT) |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 74 | |
Marshall Dawson | ef79fcc | 2019-04-01 10:16:41 -0600 | [diff] [blame] | 75 | #define DEFAULT_SOFT_FUSE_CHAIN "0x1" |
| 76 | |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 77 | /* |
Marshall Dawson | 0e02ce8 | 2019-03-04 16:50:37 -0700 | [diff] [blame] | 78 | * Beginning with Family 15h Models 70h-7F, a.k.a Stoney Ridge, the PSP |
| 79 | * can support an optional "combo" implementation. If the PSP sees the |
| 80 | * PSP2 cookie, it interprets the table as a roadmap to additional PSP |
| 81 | * tables. Using this, support for multiple product generations may be |
| 82 | * built into one image. If the PSP$ cookie is found, the table is a |
| 83 | * normal directory table. |
| 84 | * |
| 85 | * Modern generations supporting the combo directories require the |
| 86 | * pointer to be at offset 0x14 of the Embedded Firmware Structure, |
| 87 | * regardless of the type of directory used. The --combo-capable |
| 88 | * argument enforces this placement. |
| 89 | * |
| 90 | * TODO: Future work may require fully implementing the PSP_COMBO feature. |
zbao | c3b0b72 | 2016-02-19 13:47:31 +0800 | [diff] [blame] | 91 | */ |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 92 | |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 93 | /* |
| 94 | * Creates the OSI Fletcher checksum. See 8473-1, Appendix C, section C.3. |
| 95 | * The checksum field of the passed PDU does not need to be reset to zero. |
| 96 | * |
| 97 | * The "Fletcher Checksum" was proposed in a paper by John G. Fletcher of |
| 98 | * Lawrence Livermore Labs. The Fletcher Checksum was proposed as an |
| 99 | * alternative to cyclical redundancy checks because it provides error- |
| 100 | * detection properties similar to cyclical redundancy checks but at the |
| 101 | * cost of a simple summation technique. Its characteristics were first |
| 102 | * published in IEEE Transactions on Communications in January 1982. One |
| 103 | * version has been adopted by ISO for use in the class-4 transport layer |
| 104 | * of the network protocol. |
| 105 | * |
| 106 | * This program expects: |
| 107 | * stdin: The input file to compute a checksum for. The input file |
| 108 | * not be longer than 256 bytes. |
| 109 | * stdout: Copied from the input file with the Fletcher's Checksum |
| 110 | * inserted 8 bytes after the beginning of the file. |
| 111 | * stderr: Used to print out error messages. |
| 112 | */ |
Marshall Dawson | 8a45a4d | 2019-02-24 07:18:44 -0700 | [diff] [blame] | 113 | static uint32_t fletcher32(const void *data, int length) |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 114 | { |
| 115 | uint32_t c0; |
| 116 | uint32_t c1; |
| 117 | uint32_t checksum; |
| 118 | int index; |
Marshall Dawson | 8a45a4d | 2019-02-24 07:18:44 -0700 | [diff] [blame] | 119 | const uint16_t *pptr = data; |
| 120 | |
| 121 | length /= 2; |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 122 | |
| 123 | c0 = 0xFFFF; |
| 124 | c1 = 0xFFFF; |
| 125 | |
Marshall Dawson | b85ddc5 | 2019-07-23 07:24:30 -0600 | [diff] [blame] | 126 | while (length) { |
| 127 | index = length >= 359 ? 359 : length; |
| 128 | length -= index; |
| 129 | do { |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 130 | c0 += *(pptr++); |
| 131 | c1 += c0; |
Marshall Dawson | b85ddc5 | 2019-07-23 07:24:30 -0600 | [diff] [blame] | 132 | } while (--index); |
| 133 | c0 = (c0 & 0xFFFF) + (c0 >> 16); |
| 134 | c1 = (c1 & 0xFFFF) + (c1 >> 16); |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 135 | } |
| 136 | |
Marshall Dawson | 8a45a4d | 2019-02-24 07:18:44 -0700 | [diff] [blame] | 137 | /* Sums[0,1] mod 64K + overflow */ |
| 138 | c0 = (c0 & 0xFFFF) + (c0 >> 16); |
| 139 | c1 = (c1 & 0xFFFF) + (c1 >> 16); |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 140 | checksum = (c1 << 16) | c0; |
| 141 | |
| 142 | return checksum; |
| 143 | } |
| 144 | |
Martin Roth | 8806f7f | 2016-11-08 10:44:18 -0700 | [diff] [blame] | 145 | static void usage(void) |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 146 | { |
Martin Roth | 0e94062 | 2016-11-08 10:37:53 -0700 | [diff] [blame] | 147 | printf("amdfwtool: Create AMD Firmware combination\n"); |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 148 | printf("Usage: amdfwtool [options] --flashsize <size> --output <filename>\n"); |
| 149 | printf("--xhci <FILE> Add XHCI blob\n"); |
| 150 | printf("--imc <FILE> Add IMC blob\n"); |
| 151 | printf("--gec <FILE> Add GEC blob\n"); |
Martin Roth | 0e94062 | 2016-11-08 10:37:53 -0700 | [diff] [blame] | 152 | |
| 153 | printf("\nPSP options:\n"); |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 154 | printf("--combo-capable Place PSP directory pointer at Embedded\n"); |
| 155 | printf(" Firmware\n"); |
Marshall Dawson | 67d868d | 2019-02-28 11:43:40 -0700 | [diff] [blame] | 156 | printf(" offset able to support combo directory\n"); |
Zheng Bao | 993b43f | 2021-11-10 12:21:46 +0800 | [diff] [blame] | 157 | printf("--use-combo Use the COMBO layout\n"); |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 158 | printf("--multilevel Generate primary and secondary tables\n"); |
| 159 | printf("--nvram <FILE> Add nvram binary\n"); |
| 160 | printf("--soft-fuse Set soft fuse\n"); |
| 161 | printf("--token-unlock Set token unlock\n"); |
| 162 | printf("--whitelist Set if there is a whitelist\n"); |
| 163 | printf("--use-pspsecureos Set if psp secure OS is needed\n"); |
| 164 | printf("--load-mp2-fw Set if load MP2 firmware\n"); |
| 165 | printf("--load-s0i3 Set if load s0i3 firmware\n"); |
| 166 | printf("--verstage <FILE> Add verstage\n"); |
| 167 | printf("--verstage_sig Add verstage signature\n"); |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 168 | printf("--recovery-ab Use the recovery A/B layout\n"); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 169 | printf("\nBIOS options:\n"); |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 170 | printf("--instance <number> Sets instance field for the next BIOS\n"); |
Zheng Bao | 6f0b361 | 2021-04-27 17:19:43 +0800 | [diff] [blame] | 171 | printf(" firmware\n"); |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 172 | printf("--apcb <FILE> Add AGESA PSP customization block\n"); |
| 173 | printf("--apob-base <HEX_VAL> Destination for AGESA PSP output block\n"); |
| 174 | printf("--apob-nv-base <HEX_VAL> Location of S3 resume data\n"); |
| 175 | printf("--apob-nv-size <HEX_VAL> Size of S3 resume data\n"); |
| 176 | printf("--ucode <FILE> Add microcode patch\n"); |
| 177 | printf("--bios-bin <FILE> Add compressed image; auto source address\n"); |
| 178 | printf("--bios-bin-src <HEX_VAL> Address in flash of source if -V not used\n"); |
| 179 | printf("--bios-bin-dest <HEX_VAL> Destination for uncompressed BIOS\n"); |
| 180 | printf("--bios-uncomp-size <HEX> Uncompressed size of BIOS image\n"); |
| 181 | printf("--output <filename> output filename\n"); |
| 182 | printf("--flashsize <HEX_VAL> ROM size in bytes\n"); |
Marshall Dawson | f4b9b41 | 2017-03-17 16:30:51 -0600 | [diff] [blame] | 183 | printf(" size must be larger than %dKB\n", |
Martin Roth | 0e94062 | 2016-11-08 10:37:53 -0700 | [diff] [blame] | 184 | MIN_ROM_KB); |
Marshall Dawson | f4b9b41 | 2017-03-17 16:30:51 -0600 | [diff] [blame] | 185 | printf(" and must a multiple of 1024\n"); |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 186 | printf("--location Location of Directory\n"); |
| 187 | printf("--anywhere Use any 64-byte aligned addr for Directory\n"); |
| 188 | printf("--sharedmem Location of PSP/FW shared memory\n"); |
| 189 | printf("--sharedmem-size Maximum size of the PSP/FW shared memory\n"); |
Zheng Bao | 6f0b361 | 2021-04-27 17:19:43 +0800 | [diff] [blame] | 190 | printf(" area\n"); |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 191 | printf("--soc-name <socname> Specify SOC name. Supported names are\n"); |
Zheng Bao | 6f0b361 | 2021-04-27 17:19:43 +0800 | [diff] [blame] | 192 | printf(" Stoneyridge, Raven, Picasso, Renoir, Cezanne\n"); |
| 193 | printf(" or Lucienne\n"); |
Matt Papageorge | be4376c | 2020-06-15 11:18:15 -0500 | [diff] [blame] | 194 | printf("\nEmbedded Firmware Structure options used by the PSP:\n"); |
| 195 | printf("--spi-speed <HEX_VAL> SPI fast speed to place in EFS Table\n"); |
| 196 | printf(" 0x0 66.66Mhz\n"); |
| 197 | printf(" 0x1 33.33MHz\n"); |
| 198 | printf(" 0x2 22.22MHz\n"); |
| 199 | printf(" 0x3 16.66MHz\n"); |
| 200 | printf(" 0x4 100MHz\n"); |
| 201 | printf(" 0x5 800KHz\n"); |
| 202 | printf("--spi-read-mode <HEX_VAL> SPI read mode to place in EFS Table\n"); |
| 203 | printf(" 0x0 Normal Read (up to 33M)\n"); |
| 204 | printf(" 0x1 Reserved\n"); |
| 205 | printf(" 0x2 Dual IO (1-1-2)\n"); |
| 206 | printf(" 0x3 Quad IO (1-1-4)\n"); |
| 207 | printf(" 0x4 Dual IO (1-2-2)\n"); |
| 208 | printf(" 0x5 Quad IO (1-4-4)\n"); |
| 209 | printf(" 0x6 Normal Read (up to 66M)\n"); |
| 210 | printf(" 0x7 Fast Read\n"); |
| 211 | printf("--spi-micron-flag <HEX_VAL> Micron SPI part support for RV and later SOC\n"); |
| 212 | printf(" 0x0 Micron parts are not used\n"); |
| 213 | printf(" 0x1 Micron parts are always used\n"); |
| 214 | printf(" 0x2 Micron parts optional, this option is only\n"); |
| 215 | printf(" supported with RN/LCN SOC\n"); |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 216 | printf("\nGeneral options:\n"); |
| 217 | printf("-c|--config <config file> Config file\n"); |
| 218 | printf("-d|--debug Print debug message\n"); |
| 219 | printf("-l|--list List out the firmware files\n"); |
| 220 | printf("-h|--help Show this help\n"); |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 221 | } |
| 222 | |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 223 | amd_fw_entry amd_psp_fw_table[] = { |
Zheng Bao | fb9b784 | 2022-02-24 15:15:50 +0800 | [diff] [blame] | 224 | { .type = AMD_FW_PSP_PUBKEY, .level = PSP_BOTH | PSP_LVL2_AB }, |
| 225 | { .type = AMD_FW_PSP_BOOTLOADER, .level = PSP_BOTH | PSP_LVL2_AB }, |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 226 | { .type = AMD_FW_PSP_SMU_FIRMWARE, .subprog = 0, .level = PSP_BOTH | PSP_LVL2_AB }, |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 227 | { .type = AMD_FW_PSP_RECOVERY, .level = PSP_LVL1 }, |
| 228 | { .type = AMD_FW_PSP_RTM_PUBKEY, .level = PSP_BOTH }, |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 229 | { .type = AMD_FW_PSP_SECURED_OS, .level = PSP_LVL2 | PSP_LVL2_AB }, |
| 230 | { .type = AMD_FW_PSP_NVRAM, .level = PSP_LVL2 | PSP_LVL2_AB }, |
| 231 | { .type = AMD_FW_PSP_SMU_FIRMWARE, .subprog = 2, .level = PSP_BOTH | PSP_LVL2_AB }, |
| 232 | { .type = AMD_FW_PSP_SECURED_DEBUG, .level = PSP_LVL2 | PSP_LVL2_AB }, |
| 233 | { .type = AMD_FW_PSP_TRUSTLETS, .level = PSP_LVL2 | PSP_LVL2_AB }, |
| 234 | { .type = AMD_FW_PSP_TRUSTLETKEY, .level = PSP_LVL2 | PSP_LVL2_AB }, |
| 235 | { .type = AMD_FW_PSP_SMU_FIRMWARE2, .subprog = 2, .level = PSP_BOTH | PSP_LVL2_AB }, |
| 236 | { .type = AMD_FW_PSP_SMU_FIRMWARE, .subprog = 1, .level = PSP_BOTH | PSP_LVL2_AB }, |
| 237 | { .type = AMD_FW_PSP_SMU_FIRMWARE2, .subprog = 1, .level = PSP_BOTH | PSP_LVL2_AB }, |
| 238 | { .type = AMD_FW_PSP_SMU_FIRMWARE2, .level = PSP_BOTH | PSP_LVL2_AB }, |
| 239 | { .type = AMD_FW_PSP_SMUSCS, .level = PSP_BOTH }, |
| 240 | { .type = AMD_PSP_FUSE_CHAIN, .level = PSP_LVL2 | PSP_LVL2_AB }, |
| 241 | { .type = AMD_DEBUG_UNLOCK, .level = PSP_LVL2 | PSP_LVL2_AB }, |
| 242 | { .type = AMD_HW_IPCFG, .level = PSP_LVL2 | PSP_LVL2_AB }, |
Zheng Bao | fb9b784 | 2022-02-24 15:15:50 +0800 | [diff] [blame] | 243 | { .type = AMD_WRAPPED_IKEK, .level = PSP_BOTH | PSP_LVL2_AB }, |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 244 | { .type = AMD_TOKEN_UNLOCK, .level = PSP_BOTH | PSP_LVL2_AB }, |
| 245 | { .type = AMD_SEC_GASKET, .subprog = 0, .level = PSP_BOTH | PSP_LVL2_AB }, |
| 246 | { .type = AMD_SEC_GASKET, .subprog = 2, .level = PSP_BOTH | PSP_LVL2_AB }, |
| 247 | { .type = AMD_SEC_GASKET, .subprog = 1, .level = PSP_BOTH | PSP_LVL2_AB }, |
| 248 | { .type = AMD_MP2_FW, .subprog = 2, .level = PSP_LVL2 | PSP_LVL2_AB }, |
| 249 | { .type = AMD_MP2_FW, .subprog = 1, .level = PSP_LVL2 | PSP_LVL2_AB }, |
| 250 | { .type = AMD_MP2_FW, .subprog = 0, .level = PSP_LVL2 | PSP_LVL2_AB }, |
| 251 | { .type = AMD_DRIVER_ENTRIES, .level = PSP_LVL2 | PSP_LVL2_AB }, |
| 252 | { .type = AMD_FW_KVM_IMAGE, .level = PSP_LVL2 | PSP_LVL2_AB }, |
| 253 | { .type = AMD_S0I3_DRIVER, .level = PSP_LVL2 | PSP_LVL2_AB }, |
| 254 | { .type = AMD_VBIOS_BTLOADER, .level = PSP_BOTH | PSP_LVL2_AB }, |
| 255 | { .type = AMD_FW_TOS_SEC_POLICY, .level = PSP_BOTH | PSP_LVL2_AB }, |
| 256 | { .type = AMD_FW_USB_PHY, .level = PSP_LVL2 | PSP_LVL2_AB }, |
| 257 | { .type = AMD_FW_DRTM_TA, .level = PSP_LVL2 | PSP_LVL2_AB }, |
| 258 | { .type = AMD_FW_KEYDB_BL, .level = PSP_BOTH | PSP_LVL2_AB }, |
| 259 | { .type = AMD_FW_KEYDB_TOS, .level = PSP_LVL2 | PSP_LVL2_AB }, |
| 260 | { .type = AMD_FW_SPL, .level = PSP_LVL2 | PSP_LVL2_AB }, |
| 261 | { .type = AMD_FW_DMCU_ERAM, .level = PSP_LVL2 | PSP_LVL2_AB }, |
| 262 | { .type = AMD_FW_DMCU_ISR, .level = PSP_LVL2 | PSP_LVL2_AB }, |
Felix Held | 5f18bb7 | 2022-03-24 02:04:51 +0100 | [diff] [blame] | 263 | { .type = AMD_FW_MSMU, .level = PSP_LVL2 | PSP_LVL2_AB }, |
| 264 | { .type = AMD_FW_DMCUB, .level = PSP_LVL2 | PSP_LVL2_AB }, |
| 265 | { .type = AMD_FW_SPIROM_CFG, .level = PSP_LVL2 | PSP_LVL2_AB }, |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 266 | { .type = AMD_RPMC_NVRAM, .level = PSP_LVL2 | PSP_LVL2_AB }, |
| 267 | { .type = AMD_FW_PSP_BOOTLOADER_AB, .level = PSP_LVL2 | PSP_LVL2_AB }, |
Karthikeyan Ramasubramanian | 0ab04d2 | 2022-05-03 18:16:34 -0600 | [diff] [blame] | 268 | { .type = AMD_TA_IKEK, .level = PSP_BOTH | PSP_LVL2_AB }, |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 269 | { .type = AMD_ABL0, .level = PSP_BOTH | PSP_LVL2_AB }, |
| 270 | { .type = AMD_ABL1, .level = PSP_BOTH | PSP_LVL2_AB }, |
| 271 | { .type = AMD_ABL2, .level = PSP_BOTH | PSP_LVL2_AB }, |
| 272 | { .type = AMD_ABL3, .level = PSP_BOTH | PSP_LVL2_AB }, |
| 273 | { .type = AMD_ABL4, .level = PSP_BOTH | PSP_LVL2_AB }, |
| 274 | { .type = AMD_ABL5, .level = PSP_BOTH | PSP_LVL2_AB }, |
| 275 | { .type = AMD_ABL6, .level = PSP_BOTH | PSP_LVL2_AB }, |
| 276 | { .type = AMD_ABL7, .level = PSP_BOTH | PSP_LVL2_AB }, |
| 277 | { .type = AMD_FW_PSP_SMU_FIRMWARE, .subprog = 1, .level = PSP_BOTH | PSP_LVL2_AB }, |
| 278 | { .type = AMD_FW_PSP_SMU_FIRMWARE2, .subprog = 1, .level = PSP_BOTH | PSP_LVL2_AB }, |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 279 | { .type = AMD_FW_PSP_WHITELIST, .level = PSP_LVL2 }, |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 280 | { .type = AMD_FW_PSP_VERSTAGE, .level = PSP_BOTH | PSP_BOTH_AB }, |
| 281 | { .type = AMD_FW_VERSTAGE_SIG, .level = PSP_BOTH | PSP_BOTH_AB }, |
zbao | c3a08a9 | 2016-03-02 14:47:27 +0800 | [diff] [blame] | 282 | { .type = AMD_FW_INVALID }, |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 283 | }; |
| 284 | |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 285 | amd_fw_entry amd_fw_table[] = { |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 286 | { .type = AMD_FW_XHCI }, |
| 287 | { .type = AMD_FW_IMC }, |
| 288 | { .type = AMD_FW_GEC }, |
zbao | c3a08a9 | 2016-03-02 14:47:27 +0800 | [diff] [blame] | 289 | { .type = AMD_FW_INVALID }, |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 290 | }; |
| 291 | |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 292 | amd_bios_entry amd_bios_table[] = { |
Zheng Bao | bf29a0d | 2020-12-03 23:00:48 +0800 | [diff] [blame] | 293 | { .type = AMD_BIOS_RTM_PUBKEY, .inst = 0, .level = BDT_BOTH }, |
Marshall Dawson | 0581bf6 | 2019-09-25 11:03:53 -0600 | [diff] [blame] | 294 | { .type = AMD_BIOS_APCB, .inst = 0, .level = BDT_BOTH }, |
| 295 | { .type = AMD_BIOS_APCB, .inst = 1, .level = BDT_BOTH }, |
| 296 | { .type = AMD_BIOS_APCB, .inst = 2, .level = BDT_BOTH }, |
| 297 | { .type = AMD_BIOS_APCB, .inst = 3, .level = BDT_BOTH }, |
| 298 | { .type = AMD_BIOS_APCB, .inst = 4, .level = BDT_BOTH }, |
Rob Barnes | 18fd26c | 2020-03-03 10:35:02 -0700 | [diff] [blame] | 299 | { .type = AMD_BIOS_APCB, .inst = 5, .level = BDT_BOTH }, |
| 300 | { .type = AMD_BIOS_APCB, .inst = 6, .level = BDT_BOTH }, |
| 301 | { .type = AMD_BIOS_APCB, .inst = 7, .level = BDT_BOTH }, |
| 302 | { .type = AMD_BIOS_APCB, .inst = 8, .level = BDT_BOTH }, |
| 303 | { .type = AMD_BIOS_APCB, .inst = 9, .level = BDT_BOTH }, |
| 304 | { .type = AMD_BIOS_APCB, .inst = 10, .level = BDT_BOTH }, |
| 305 | { .type = AMD_BIOS_APCB, .inst = 11, .level = BDT_BOTH }, |
| 306 | { .type = AMD_BIOS_APCB, .inst = 12, .level = BDT_BOTH }, |
| 307 | { .type = AMD_BIOS_APCB, .inst = 13, .level = BDT_BOTH }, |
| 308 | { .type = AMD_BIOS_APCB, .inst = 14, .level = BDT_BOTH }, |
| 309 | { .type = AMD_BIOS_APCB, .inst = 15, .level = BDT_BOTH }, |
Marshall Dawson | 2dd3b5c | 2020-01-03 17:57:48 -0700 | [diff] [blame] | 310 | { .type = AMD_BIOS_APCB_BK, .inst = 0, .level = BDT_BOTH }, |
| 311 | { .type = AMD_BIOS_APCB_BK, .inst = 1, .level = BDT_BOTH }, |
| 312 | { .type = AMD_BIOS_APCB_BK, .inst = 2, .level = BDT_BOTH }, |
| 313 | { .type = AMD_BIOS_APCB_BK, .inst = 3, .level = BDT_BOTH }, |
| 314 | { .type = AMD_BIOS_APCB_BK, .inst = 4, .level = BDT_BOTH }, |
Rob Barnes | 18fd26c | 2020-03-03 10:35:02 -0700 | [diff] [blame] | 315 | { .type = AMD_BIOS_APCB_BK, .inst = 5, .level = BDT_BOTH }, |
| 316 | { .type = AMD_BIOS_APCB_BK, .inst = 6, .level = BDT_BOTH }, |
| 317 | { .type = AMD_BIOS_APCB_BK, .inst = 7, .level = BDT_BOTH }, |
| 318 | { .type = AMD_BIOS_APCB_BK, .inst = 8, .level = BDT_BOTH }, |
| 319 | { .type = AMD_BIOS_APCB_BK, .inst = 9, .level = BDT_BOTH }, |
| 320 | { .type = AMD_BIOS_APCB_BK, .inst = 10, .level = BDT_BOTH }, |
| 321 | { .type = AMD_BIOS_APCB_BK, .inst = 11, .level = BDT_BOTH }, |
| 322 | { .type = AMD_BIOS_APCB_BK, .inst = 12, .level = BDT_BOTH }, |
| 323 | { .type = AMD_BIOS_APCB_BK, .inst = 13, .level = BDT_BOTH }, |
| 324 | { .type = AMD_BIOS_APCB_BK, .inst = 14, .level = BDT_BOTH }, |
| 325 | { .type = AMD_BIOS_APCB_BK, .inst = 15, .level = BDT_BOTH }, |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 326 | { .type = AMD_BIOS_APOB, .level = BDT_BOTH }, |
| 327 | { .type = AMD_BIOS_BIN, |
| 328 | .reset = 1, .copy = 1, .zlib = 1, .level = BDT_BOTH }, |
| 329 | { .type = AMD_BIOS_APOB_NV, .level = BDT_LVL2 }, |
| 330 | { .type = AMD_BIOS_PMUI, .inst = 1, .subpr = 0, .level = BDT_BOTH }, |
| 331 | { .type = AMD_BIOS_PMUD, .inst = 1, .subpr = 0, .level = BDT_BOTH }, |
Zheng Bao | e220faa | 2022-02-17 17:22:15 +0800 | [diff] [blame] | 332 | { .type = AMD_BIOS_PMUI, .inst = 2, .subpr = 0, .level = BDT_BOTH }, |
| 333 | { .type = AMD_BIOS_PMUD, .inst = 2, .subpr = 0, .level = BDT_BOTH }, |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 334 | { .type = AMD_BIOS_PMUI, .inst = 4, .subpr = 0, .level = BDT_BOTH }, |
| 335 | { .type = AMD_BIOS_PMUD, .inst = 4, .subpr = 0, .level = BDT_BOTH }, |
| 336 | { .type = AMD_BIOS_PMUI, .inst = 1, .subpr = 1, .level = BDT_BOTH }, |
| 337 | { .type = AMD_BIOS_PMUD, .inst = 1, .subpr = 1, .level = BDT_BOTH }, |
Zheng Bao | e220faa | 2022-02-17 17:22:15 +0800 | [diff] [blame] | 338 | { .type = AMD_BIOS_PMUI, .inst = 2, .subpr = 1, .level = BDT_BOTH }, |
| 339 | { .type = AMD_BIOS_PMUD, .inst = 2, .subpr = 1, .level = BDT_BOTH }, |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 340 | { .type = AMD_BIOS_PMUI, .inst = 4, .subpr = 1, .level = BDT_BOTH }, |
| 341 | { .type = AMD_BIOS_PMUD, .inst = 4, .subpr = 1, .level = BDT_BOTH }, |
| 342 | { .type = AMD_BIOS_UCODE, .inst = 0, .level = BDT_LVL2 }, |
| 343 | { .type = AMD_BIOS_UCODE, .inst = 1, .level = BDT_LVL2 }, |
| 344 | { .type = AMD_BIOS_UCODE, .inst = 2, .level = BDT_LVL2 }, |
| 345 | { .type = AMD_BIOS_MP2_CFG, .level = BDT_LVL2 }, |
Martin Roth | 9455474 | 2020-04-14 14:59:36 -0600 | [diff] [blame] | 346 | { .type = AMD_BIOS_PSP_SHARED_MEM, .inst = 0, .level = BDT_BOTH }, |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 347 | { .type = AMD_BIOS_INVALID }, |
| 348 | }; |
| 349 | |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 350 | |
Martin Roth | 9455474 | 2020-04-14 14:59:36 -0600 | [diff] [blame] | 351 | #define MAX_BIOS_ENTRIES 0x2f |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 352 | |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 353 | typedef struct _context { |
| 354 | char *rom; /* target buffer, size of flash device */ |
| 355 | uint32_t rom_size; /* size of flash device */ |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 356 | uint32_t address_mode; /* 0:abs address; 1:relative to flash; 2: relative to table */ |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 357 | uint32_t current; /* pointer within flash & proxy buffer */ |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 358 | uint32_t current_table; |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 359 | } context; |
| 360 | |
| 361 | #define RUN_BASE(ctx) (0xFFFFFFFF - (ctx).rom_size + 1) |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 362 | #define RUN_OFFSET_MODE(ctx, offset, mode) \ |
Robert Zieba | 29bc79f | 2022-03-14 15:59:12 -0600 | [diff] [blame] | 363 | ((mode) == AMD_ADDR_PHYSICAL ? RUN_BASE(ctx) + (offset) : \ |
| 364 | ((mode) == AMD_ADDR_REL_BIOS ? (offset) : \ |
| 365 | ((mode) == AMD_ADDR_REL_TAB ? (offset) - ctx.current_table : (offset)))) |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 366 | #define RUN_OFFSET(ctx, offset) RUN_OFFSET_MODE((ctx), (offset), (ctx).address_mode) |
Robert Zieba | 29bc79f | 2022-03-14 15:59:12 -0600 | [diff] [blame] | 367 | #define RUN_TO_OFFSET(ctx, run) ((ctx).address_mode == AMD_ADDR_PHYSICAL ? \ |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 368 | (run) - RUN_BASE(ctx) : (run)) /* TODO: */ |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 369 | #define RUN_CURRENT(ctx) RUN_OFFSET((ctx), (ctx).current) |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 370 | /* The mode in entry can not be higher than the header's. |
| 371 | For example, if table mode is 0, all the entry mode will be 0. */ |
| 372 | #define RUN_CURRENT_MODE(ctx, mode) RUN_OFFSET_MODE((ctx), (ctx).current, \ |
| 373 | (ctx).address_mode < (mode) ? (ctx).address_mode : (mode)) |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 374 | #define BUFF_OFFSET(ctx, offset) ((void *)((ctx).rom + (offset))) |
| 375 | #define BUFF_CURRENT(ctx) BUFF_OFFSET((ctx), (ctx).current) |
| 376 | #define BUFF_TO_RUN(ctx, ptr) RUN_OFFSET((ctx), ((char *)(ptr) - (ctx).rom)) |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 377 | #define BUFF_TO_RUN_MODE(ctx, ptr, mode) RUN_OFFSET_MODE((ctx), ((char *)(ptr) - (ctx).rom), \ |
| 378 | (ctx).address_mode < (mode) ? (ctx).address_mode : (mode)) |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 379 | #define BUFF_ROOM(ctx) ((ctx).rom_size - (ctx).current) |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 380 | /* Only set the address mode in entry if the table is mode 2. */ |
| 381 | #define SET_ADDR_MODE(table, mode) \ |
| 382 | ((table)->header.additional_info_fields.address_mode == \ |
Robert Zieba | 29bc79f | 2022-03-14 15:59:12 -0600 | [diff] [blame] | 383 | AMD_ADDR_REL_TAB ? (mode) : 0) |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 384 | #define SET_ADDR_MODE_BY_TABLE(table) \ |
| 385 | SET_ADDR_MODE((table), (table)->header.additional_info_fields.address_mode) |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 386 | |
Zheng Bao | 5164e4b | 2021-10-30 12:09:07 +0800 | [diff] [blame] | 387 | void assert_fw_entry(uint32_t count, uint32_t max, context *ctx) |
| 388 | { |
| 389 | if (count >= max) { |
| 390 | fprintf(stderr, "Error: BIOS entries (%d) exceeds max allowed items " |
| 391 | "(%d)\n", count, max); |
| 392 | free(ctx->rom); |
| 393 | exit(1); |
| 394 | } |
| 395 | } |
| 396 | |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 397 | static void *new_psp_dir(context *ctx, int multi) |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 398 | { |
| 399 | void *ptr; |
| 400 | |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 401 | /* |
| 402 | * Force both onto boundary when multi. Primary table is after |
| 403 | * updatable table, so alignment ensures primary can stay intact |
| 404 | * if secondary is reprogrammed. |
| 405 | */ |
| 406 | if (multi) |
| 407 | ctx->current = ALIGN(ctx->current, TABLE_ERASE_ALIGNMENT); |
| 408 | else |
| 409 | ctx->current = ALIGN(ctx->current, TABLE_ALIGNMENT); |
| 410 | |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 411 | ptr = BUFF_CURRENT(*ctx); |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 412 | ((psp_directory_header *)ptr)->num_entries = 0; |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 413 | ((psp_directory_header *)ptr)->additional_info = 0; |
| 414 | ((psp_directory_header *)ptr)->additional_info_fields.address_mode = ctx->address_mode; |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 415 | ctx->current += sizeof(psp_directory_header) |
| 416 | + MAX_PSP_ENTRIES * sizeof(psp_directory_entry); |
| 417 | return ptr; |
| 418 | } |
| 419 | |
Zheng Bao | fdd47ef | 2021-09-17 13:30:08 +0800 | [diff] [blame] | 420 | static void *new_ish_dir(context *ctx) |
| 421 | { |
| 422 | void *ptr; |
| 423 | ctx->current = ALIGN(ctx->current, TABLE_ALIGNMENT); |
| 424 | ptr = BUFF_CURRENT(*ctx); |
| 425 | ctx->current += TABLE_ALIGNMENT; |
| 426 | return ptr; |
| 427 | } |
| 428 | |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 429 | static void *new_combo_dir(context *ctx) |
| 430 | { |
| 431 | void *ptr; |
| 432 | |
| 433 | ctx->current = ALIGN(ctx->current, TABLE_ALIGNMENT); |
| 434 | ptr = BUFF_CURRENT(*ctx); |
| 435 | ctx->current += sizeof(psp_combo_header) |
| 436 | + MAX_COMBO_ENTRIES * sizeof(psp_combo_entry); |
| 437 | return ptr; |
| 438 | } |
| 439 | |
Zheng Bao | bf29a0d | 2020-12-03 23:00:48 +0800 | [diff] [blame] | 440 | static void fill_dir_header(void *directory, uint32_t count, uint32_t cookie, context *ctx) |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 441 | { |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 442 | psp_combo_directory *cdir = directory; |
| 443 | psp_directory_table *dir = directory; |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 444 | bios_directory_table *bdir = directory; |
Zheng Bao | bf29a0d | 2020-12-03 23:00:48 +0800 | [diff] [blame] | 445 | uint32_t table_size = 0; |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 446 | |
| 447 | if (!count) |
| 448 | return; |
Zheng Bao | b035f58 | 2021-05-27 11:26:12 +0800 | [diff] [blame] | 449 | if (ctx == NULL || directory == NULL) { |
| 450 | fprintf(stderr, "Calling %s with NULL pointers\n", __func__); |
| 451 | return; |
| 452 | } |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 453 | |
Zheng Bao | bf29a0d | 2020-12-03 23:00:48 +0800 | [diff] [blame] | 454 | /* The table size needs to be 0x1000 aligned. So align the end of table. */ |
Zheng Bao | b035f58 | 2021-05-27 11:26:12 +0800 | [diff] [blame] | 455 | ctx->current = ALIGN(ctx->current, TABLE_ALIGNMENT); |
Zheng Bao | bf29a0d | 2020-12-03 23:00:48 +0800 | [diff] [blame] | 456 | |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 457 | switch (cookie) { |
| 458 | case PSP2_COOKIE: |
Marshall Dawson | a378c22 | 2019-03-04 16:52:07 -0700 | [diff] [blame] | 459 | /* caller is responsible for lookup mode */ |
Marshall Dawson | a378c22 | 2019-03-04 16:52:07 -0700 | [diff] [blame] | 460 | cdir->header.cookie = cookie; |
| 461 | cdir->header.num_entries = count; |
| 462 | cdir->header.reserved[0] = 0; |
| 463 | cdir->header.reserved[1] = 0; |
| 464 | /* checksum everything that comes after the Checksum field */ |
| 465 | cdir->header.checksum = fletcher32(&cdir->header.num_entries, |
| 466 | count * sizeof(psp_combo_entry) |
| 467 | + sizeof(cdir->header.num_entries) |
| 468 | + sizeof(cdir->header.lookup) |
| 469 | + 2 * sizeof(cdir->header.reserved[0])); |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 470 | break; |
| 471 | case PSP_COOKIE: |
| 472 | case PSPL2_COOKIE: |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 473 | table_size = ctx->current - ctx->current_table; |
Zheng Bao | bf29a0d | 2020-12-03 23:00:48 +0800 | [diff] [blame] | 474 | if ((table_size % TABLE_ALIGNMENT) != 0) { |
| 475 | fprintf(stderr, "The PSP table size should be 4K aligned\n"); |
| 476 | exit(1); |
| 477 | } |
Marshall Dawson | a378c22 | 2019-03-04 16:52:07 -0700 | [diff] [blame] | 478 | dir->header.cookie = cookie; |
| 479 | dir->header.num_entries = count; |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 480 | dir->header.additional_info_fields.dir_size = table_size / TABLE_ALIGNMENT; |
| 481 | dir->header.additional_info_fields.spi_block_size = 1; |
| 482 | dir->header.additional_info_fields.base_addr = 0; |
Marshall Dawson | a378c22 | 2019-03-04 16:52:07 -0700 | [diff] [blame] | 483 | /* checksum everything that comes after the Checksum field */ |
| 484 | dir->header.checksum = fletcher32(&dir->header.num_entries, |
Marshall Dawson | 8a45a4d | 2019-02-24 07:18:44 -0700 | [diff] [blame] | 485 | count * sizeof(psp_directory_entry) |
Marshall Dawson | a378c22 | 2019-03-04 16:52:07 -0700 | [diff] [blame] | 486 | + sizeof(dir->header.num_entries) |
Zheng Bao | bf29a0d | 2020-12-03 23:00:48 +0800 | [diff] [blame] | 487 | + sizeof(dir->header.additional_info)); |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 488 | break; |
Zheng Bao | 96a3371 | 2021-06-11 15:54:40 +0800 | [diff] [blame] | 489 | case BHD_COOKIE: |
| 490 | case BHDL2_COOKIE: |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 491 | table_size = ctx->current - ctx->current_table; |
Zheng Bao | bf29a0d | 2020-12-03 23:00:48 +0800 | [diff] [blame] | 492 | if ((table_size % TABLE_ALIGNMENT) != 0) { |
| 493 | fprintf(stderr, "The BIOS table size should be 4K aligned\n"); |
| 494 | exit(1); |
| 495 | } |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 496 | bdir->header.cookie = cookie; |
| 497 | bdir->header.num_entries = count; |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 498 | bdir->header.additional_info_fields.dir_size = table_size / TABLE_ALIGNMENT; |
| 499 | bdir->header.additional_info_fields.spi_block_size = 1; |
| 500 | bdir->header.additional_info_fields.base_addr = 0; |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 501 | /* checksum everything that comes after the Checksum field */ |
| 502 | bdir->header.checksum = fletcher32(&bdir->header.num_entries, |
| 503 | count * sizeof(bios_directory_entry) |
| 504 | + sizeof(bdir->header.num_entries) |
Zheng Bao | bf29a0d | 2020-12-03 23:00:48 +0800 | [diff] [blame] | 505 | + sizeof(bdir->header.additional_info)); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 506 | break; |
Marshall Dawson | a378c22 | 2019-03-04 16:52:07 -0700 | [diff] [blame] | 507 | } |
Zheng Bao | bf29a0d | 2020-12-03 23:00:48 +0800 | [diff] [blame] | 508 | |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 509 | } |
| 510 | |
Marshall Dawson | 8e0dca0 | 2019-02-27 18:40:49 -0700 | [diff] [blame] | 511 | static ssize_t copy_blob(void *dest, const char *src_file, size_t room) |
| 512 | { |
| 513 | int fd; |
| 514 | struct stat fd_stat; |
| 515 | ssize_t bytes; |
| 516 | |
| 517 | fd = open(src_file, O_RDONLY); |
| 518 | if (fd < 0) { |
Zheng Bao | 77a2c67 | 2020-10-01 17:05:43 +0800 | [diff] [blame] | 519 | fprintf(stderr, "Error opening file: %s: %s\n", |
Eric Peers | af50567 | 2020-03-05 16:04:15 -0700 | [diff] [blame] | 520 | src_file, strerror(errno)); |
Marshall Dawson | 8e0dca0 | 2019-02-27 18:40:49 -0700 | [diff] [blame] | 521 | return -1; |
| 522 | } |
| 523 | |
| 524 | if (fstat(fd, &fd_stat)) { |
Zheng Bao | 77a2c67 | 2020-10-01 17:05:43 +0800 | [diff] [blame] | 525 | fprintf(stderr, "fstat error: %s\n", strerror(errno)); |
Jacob Garber | 967f862 | 2019-07-02 10:35:10 -0600 | [diff] [blame] | 526 | close(fd); |
Marshall Dawson | 8e0dca0 | 2019-02-27 18:40:49 -0700 | [diff] [blame] | 527 | return -2; |
| 528 | } |
| 529 | |
Zheng Bao | 6d402ac | 2020-10-01 16:16:30 +0800 | [diff] [blame] | 530 | if ((size_t)fd_stat.st_size > room) { |
Zheng Bao | 77a2c67 | 2020-10-01 17:05:43 +0800 | [diff] [blame] | 531 | fprintf(stderr, "Error: %s will not fit. Exiting.\n", src_file); |
Jacob Garber | 967f862 | 2019-07-02 10:35:10 -0600 | [diff] [blame] | 532 | close(fd); |
Marshall Dawson | 8e0dca0 | 2019-02-27 18:40:49 -0700 | [diff] [blame] | 533 | return -3; |
| 534 | } |
| 535 | |
| 536 | bytes = read(fd, dest, (size_t)fd_stat.st_size); |
| 537 | close(fd); |
| 538 | if (bytes != (ssize_t)fd_stat.st_size) { |
Zheng Bao | 77a2c67 | 2020-10-01 17:05:43 +0800 | [diff] [blame] | 539 | fprintf(stderr, "Error while reading %s\n", src_file); |
Marshall Dawson | 8e0dca0 | 2019-02-27 18:40:49 -0700 | [diff] [blame] | 540 | return -4; |
| 541 | } |
| 542 | |
| 543 | return bytes; |
| 544 | } |
| 545 | |
Zheng Bao | eb0404e | 2021-10-14 15:09:09 +0800 | [diff] [blame] | 546 | enum platform { |
| 547 | PLATFORM_UNKNOWN, |
| 548 | PLATFORM_STONEYRIDGE, |
| 549 | PLATFORM_RAVEN, |
| 550 | PLATFORM_PICASSO, |
| 551 | PLATFORM_RENOIR, |
| 552 | PLATFORM_CEZANNE, |
| 553 | PLATFORM_MENDOCINO, |
| 554 | PLATFORM_LUCIENNE, |
Felix Held | b18a4c7 | 2022-03-29 02:34:11 +0200 | [diff] [blame] | 555 | PLATFORM_SABRINA, |
Zheng Bao | eb0404e | 2021-10-14 15:09:09 +0800 | [diff] [blame] | 556 | }; |
| 557 | |
| 558 | static uint32_t get_psp_id(enum platform soc_id) |
| 559 | { |
| 560 | uint32_t psp_id; |
| 561 | switch (soc_id) { |
| 562 | case PLATFORM_RAVEN: |
| 563 | case PLATFORM_PICASSO: |
| 564 | psp_id = 0xBC0A0000; |
| 565 | break; |
| 566 | case PLATFORM_RENOIR: |
| 567 | case PLATFORM_LUCIENNE: |
| 568 | psp_id = 0xBC0C0000; |
| 569 | break; |
| 570 | case PLATFORM_CEZANNE: |
| 571 | psp_id = 0xBC0C0140; |
| 572 | break; |
| 573 | case PLATFORM_MENDOCINO: |
Felix Held | b18a4c7 | 2022-03-29 02:34:11 +0200 | [diff] [blame] | 574 | case PLATFORM_SABRINA: |
Zheng Bao | eb0404e | 2021-10-14 15:09:09 +0800 | [diff] [blame] | 575 | psp_id = 0xBC0D0900; |
| 576 | break; |
| 577 | case PLATFORM_STONEYRIDGE: |
| 578 | psp_id = 0x10220B00; |
| 579 | break; |
| 580 | default: |
| 581 | psp_id = 0; |
| 582 | break; |
| 583 | } |
| 584 | return psp_id; |
| 585 | } |
| 586 | |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 587 | static void integrate_firmwares(context *ctx, |
Marshall Dawson | 239286c | 2019-02-23 16:42:46 -0700 | [diff] [blame] | 588 | embedded_firmware *romsig, |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 589 | amd_fw_entry *fw_table) |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 590 | { |
Richard Spiegel | 137484d | 2018-01-17 10:23:19 -0700 | [diff] [blame] | 591 | ssize_t bytes; |
Zheng Bao | 6d402ac | 2020-10-01 16:16:30 +0800 | [diff] [blame] | 592 | uint32_t i; |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 593 | |
| 594 | ctx->current += sizeof(embedded_firmware); |
| 595 | ctx->current = ALIGN(ctx->current, BLOB_ALIGNMENT); |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 596 | |
Martin Roth | cd15bc8 | 2016-11-08 11:34:02 -0700 | [diff] [blame] | 597 | for (i = 0; fw_table[i].type != AMD_FW_INVALID; i++) { |
zbao | c3a08a9 | 2016-03-02 14:47:27 +0800 | [diff] [blame] | 598 | if (fw_table[i].filename != NULL) { |
zbao | c3a08a9 | 2016-03-02 14:47:27 +0800 | [diff] [blame] | 599 | switch (fw_table[i].type) { |
| 600 | case AMD_FW_IMC: |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 601 | ctx->current = ALIGN(ctx->current, 0x10000U); |
| 602 | romsig->imc_entry = RUN_CURRENT(*ctx); |
zbao | c3a08a9 | 2016-03-02 14:47:27 +0800 | [diff] [blame] | 603 | break; |
| 604 | case AMD_FW_GEC: |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 605 | romsig->gec_entry = RUN_CURRENT(*ctx); |
zbao | c3a08a9 | 2016-03-02 14:47:27 +0800 | [diff] [blame] | 606 | break; |
| 607 | case AMD_FW_XHCI: |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 608 | romsig->xhci_entry = RUN_CURRENT(*ctx); |
zbao | c3a08a9 | 2016-03-02 14:47:27 +0800 | [diff] [blame] | 609 | break; |
| 610 | default: |
| 611 | /* Error */ |
| 612 | break; |
| 613 | } |
| 614 | |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 615 | bytes = copy_blob(BUFF_CURRENT(*ctx), |
| 616 | fw_table[i].filename, BUFF_ROOM(*ctx)); |
Marshall Dawson | 02bd773 | 2019-03-13 14:43:17 -0600 | [diff] [blame] | 617 | if (bytes < 0) { |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 618 | free(ctx->rom); |
Martin Roth | 60f1551 | 2016-11-08 09:55:01 -0700 | [diff] [blame] | 619 | exit(1); |
| 620 | } |
| 621 | |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 622 | ctx->current = ALIGN(ctx->current + bytes, |
| 623 | BLOB_ALIGNMENT); |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 624 | } |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 625 | } |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 626 | } |
| 627 | |
Zheng Bao | 9e90807 | 2020-10-28 11:39:13 +0800 | [diff] [blame] | 628 | /* For debugging */ |
| 629 | static void dump_psp_firmwares(amd_fw_entry *fw_table) |
| 630 | { |
| 631 | amd_fw_entry *index; |
| 632 | |
| 633 | printf("PSP firmware components:"); |
| 634 | for (index = fw_table; index->type != AMD_FW_INVALID; index++) { |
| 635 | if (index->filename) |
Zheng Bao | 826f1c4 | 2021-05-25 16:26:55 +0800 | [diff] [blame] | 636 | printf(" %2x: %s\n", index->type, index->filename); |
Zheng Bao | 9e90807 | 2020-10-28 11:39:13 +0800 | [diff] [blame] | 637 | } |
| 638 | } |
| 639 | |
| 640 | static void dump_bdt_firmwares(amd_bios_entry *fw_table) |
| 641 | { |
| 642 | amd_bios_entry *index; |
| 643 | |
| 644 | printf("BIOS Directory Table (BDT) components:"); |
| 645 | for (index = fw_table; index->type != AMD_BIOS_INVALID; index++) { |
| 646 | if (index->filename) |
Zheng Bao | 826f1c4 | 2021-05-25 16:26:55 +0800 | [diff] [blame] | 647 | printf(" %2x: %s\n", index->type, index->filename); |
Zheng Bao | 9e90807 | 2020-10-28 11:39:13 +0800 | [diff] [blame] | 648 | } |
| 649 | } |
| 650 | |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 651 | static void free_psp_firmware_filenames(amd_fw_entry *fw_table) |
| 652 | { |
| 653 | amd_fw_entry *index; |
| 654 | |
| 655 | for (index = fw_table; index->type != AMD_FW_INVALID; index++) { |
| 656 | if (index->filename && |
| 657 | index->type != AMD_FW_VERSTAGE_SIG && |
| 658 | index->type != AMD_FW_PSP_VERSTAGE && |
Zheng Bao | 6c5ec8e | 2022-02-11 11:51:26 +0800 | [diff] [blame] | 659 | index->type != AMD_FW_SPL && |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 660 | index->type != AMD_FW_PSP_WHITELIST) { |
| 661 | free(index->filename); |
| 662 | } |
| 663 | } |
| 664 | } |
| 665 | |
| 666 | static void free_bdt_firmware_filenames(amd_bios_entry *fw_table) |
| 667 | { |
| 668 | amd_bios_entry *index; |
| 669 | |
| 670 | for (index = fw_table; index->type != AMD_BIOS_INVALID; index++) { |
| 671 | if (index->filename && |
| 672 | index->type != AMD_BIOS_APCB && |
| 673 | index->type != AMD_BIOS_BIN && |
| 674 | index->type != AMD_BIOS_APCB_BK) |
| 675 | free(index->filename); |
| 676 | } |
| 677 | } |
| 678 | |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 679 | static void integrate_psp_ab(context *ctx, psp_directory_table *pspdir, |
Zheng Bao | fdd47ef | 2021-09-17 13:30:08 +0800 | [diff] [blame] | 680 | psp_directory_table *pspdir2, ish_directory_table *ish, |
| 681 | amd_fw_type ab, enum platform soc_id) |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 682 | { |
| 683 | uint32_t count; |
| 684 | uint32_t current_table_save; |
| 685 | |
| 686 | current_table_save = ctx->current_table; |
| 687 | ctx->current_table = (char *)pspdir - ctx->rom; |
| 688 | count = pspdir->header.num_entries; |
| 689 | assert_fw_entry(count, MAX_PSP_ENTRIES, ctx); |
| 690 | pspdir->entries[count].type = (uint8_t)ab; |
| 691 | pspdir->entries[count].subprog = 0; |
| 692 | pspdir->entries[count].rsvd = 0; |
Zheng Bao | fdd47ef | 2021-09-17 13:30:08 +0800 | [diff] [blame] | 693 | if (ish != NULL) { |
Robert Zieba | 29bc79f | 2022-03-14 15:59:12 -0600 | [diff] [blame] | 694 | ish->pl2_location = BUFF_TO_RUN_MODE(*ctx, pspdir2, AMD_ADDR_REL_BIOS); |
Zheng Bao | fdd47ef | 2021-09-17 13:30:08 +0800 | [diff] [blame] | 695 | ish->boot_priority = ab == AMD_FW_RECOVERYAB_A ? 0xFFFFFFFF : 1; |
| 696 | ish->update_retry_count = 2; |
| 697 | ish->glitch_retry_count = 0; |
| 698 | ish->psp_id = get_psp_id(soc_id); |
| 699 | ish->checksum = fletcher32(&ish->boot_priority, |
| 700 | sizeof(ish_directory_table) - sizeof(uint32_t)); |
| 701 | pspdir->entries[count].addr = |
Robert Zieba | 29bc79f | 2022-03-14 15:59:12 -0600 | [diff] [blame] | 702 | BUFF_TO_RUN_MODE(*ctx, ish, AMD_ADDR_REL_BIOS); |
Zheng Bao | fdd47ef | 2021-09-17 13:30:08 +0800 | [diff] [blame] | 703 | pspdir->entries[count].address_mode = |
Robert Zieba | 29bc79f | 2022-03-14 15:59:12 -0600 | [diff] [blame] | 704 | SET_ADDR_MODE(pspdir, AMD_ADDR_REL_BIOS); |
Zheng Bao | fdd47ef | 2021-09-17 13:30:08 +0800 | [diff] [blame] | 705 | pspdir->entries[count].size = TABLE_ALIGNMENT; |
| 706 | } else { |
| 707 | pspdir->entries[count].addr = |
Robert Zieba | 29bc79f | 2022-03-14 15:59:12 -0600 | [diff] [blame] | 708 | BUFF_TO_RUN_MODE(*ctx, pspdir2, AMD_ADDR_REL_BIOS); |
Zheng Bao | fdd47ef | 2021-09-17 13:30:08 +0800 | [diff] [blame] | 709 | pspdir->entries[count].address_mode = |
Robert Zieba | 29bc79f | 2022-03-14 15:59:12 -0600 | [diff] [blame] | 710 | SET_ADDR_MODE(pspdir, AMD_ADDR_REL_BIOS); |
Zheng Bao | fdd47ef | 2021-09-17 13:30:08 +0800 | [diff] [blame] | 711 | pspdir->entries[count].size = pspdir2->header.num_entries * |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 712 | sizeof(psp_directory_entry) + |
| 713 | sizeof(psp_directory_header); |
Zheng Bao | fdd47ef | 2021-09-17 13:30:08 +0800 | [diff] [blame] | 714 | } |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 715 | |
| 716 | count++; |
| 717 | pspdir->header.num_entries = count; |
| 718 | ctx->current_table = current_table_save; |
| 719 | } |
| 720 | |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 721 | static void integrate_psp_firmwares(context *ctx, |
Marshall Dawson | 239286c | 2019-02-23 16:42:46 -0700 | [diff] [blame] | 722 | psp_directory_table *pspdir, |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 723 | psp_directory_table *pspdir2, |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 724 | psp_directory_table *pspdir2_b, |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 725 | amd_fw_entry *fw_table, |
Zheng Bao | 2079589 | 2021-08-20 14:58:22 +0800 | [diff] [blame] | 726 | uint32_t cookie, |
Zheng Bao | fdd47ef | 2021-09-17 13:30:08 +0800 | [diff] [blame] | 727 | enum platform soc_id, |
Zheng Bao | 2079589 | 2021-08-20 14:58:22 +0800 | [diff] [blame] | 728 | amd_cb_config *cb_config) |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 729 | { |
Richard Spiegel | 137484d | 2018-01-17 10:23:19 -0700 | [diff] [blame] | 730 | ssize_t bytes; |
Marshall Dawson | c38c0c9 | 2019-02-23 16:41:35 -0700 | [diff] [blame] | 731 | unsigned int i, count; |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 732 | int level; |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 733 | uint32_t current_table_save; |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 734 | bool recovery_ab = cb_config->recovery_ab; |
Zheng Bao | fdd47ef | 2021-09-17 13:30:08 +0800 | [diff] [blame] | 735 | ish_directory_table *ish_a_dir = NULL, *ish_b_dir = NULL; |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 736 | |
| 737 | /* This function can create a primary table, a secondary table, or a |
| 738 | * flattened table which contains all applicable types. These if-else |
| 739 | * statements infer what the caller intended. If a 2nd-level cookie |
| 740 | * is passed, clearly a 2nd-level table is intended. However, a |
| 741 | * 1st-level cookie may indicate level 1 or flattened. If the caller |
| 742 | * passes a pointer to a 2nd-level table, then assume not flat. |
| 743 | */ |
Zheng Bao | ba3af5e | 2021-11-04 18:56:47 +0800 | [diff] [blame] | 744 | if (!cb_config->multi_level) |
Zheng Bao | 2079589 | 2021-08-20 14:58:22 +0800 | [diff] [blame] | 745 | level = PSP_BOTH; |
| 746 | else if (cookie == PSPL2_COOKIE) |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 747 | level = PSP_LVL2; |
| 748 | else if (pspdir2) |
| 749 | level = PSP_LVL1; |
| 750 | else |
| 751 | level = PSP_BOTH; |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 752 | |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 753 | if (recovery_ab) { |
| 754 | if (cookie == PSPL2_COOKIE) |
| 755 | level = PSP_LVL2_AB; |
| 756 | else if (pspdir2) |
| 757 | level = PSP_LVL1_AB; |
| 758 | else |
| 759 | level = PSP_BOTH_AB; |
| 760 | } |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 761 | current_table_save = ctx->current_table; |
| 762 | ctx->current_table = (char *)pspdir - ctx->rom; |
Zheng Bao | bf29a0d | 2020-12-03 23:00:48 +0800 | [diff] [blame] | 763 | ctx->current = ALIGN(ctx->current, TABLE_ALIGNMENT); |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 764 | |
Marshall Dawson | c38c0c9 | 2019-02-23 16:41:35 -0700 | [diff] [blame] | 765 | for (i = 0, count = 0; fw_table[i].type != AMD_FW_INVALID; i++) { |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 766 | if (!(fw_table[i].level & level)) |
| 767 | continue; |
| 768 | |
Zheng Bao | 5164e4b | 2021-10-30 12:09:07 +0800 | [diff] [blame] | 769 | assert_fw_entry(count, MAX_PSP_ENTRIES, ctx); |
| 770 | |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 771 | if (fw_table[i].type == AMD_TOKEN_UNLOCK) { |
| 772 | if (!fw_table[i].other) |
| 773 | continue; |
| 774 | ctx->current = ALIGN(ctx->current, ERASE_ALIGNMENT); |
| 775 | pspdir->entries[count].type = fw_table[i].type; |
| 776 | pspdir->entries[count].size = 4096; /* TODO: doc? */ |
| 777 | pspdir->entries[count].addr = RUN_CURRENT(*ctx); |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 778 | pspdir->entries[count].address_mode = SET_ADDR_MODE_BY_TABLE(pspdir); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 779 | pspdir->entries[count].subprog = fw_table[i].subprog; |
| 780 | pspdir->entries[count].rsvd = 0; |
| 781 | ctx->current = ALIGN(ctx->current + 4096, 0x100U); |
| 782 | count++; |
| 783 | } else if (fw_table[i].type == AMD_PSP_FUSE_CHAIN) { |
Marshall Dawson | 239286c | 2019-02-23 16:42:46 -0700 | [diff] [blame] | 784 | pspdir->entries[count].type = fw_table[i].type; |
Marshall Dawson | dbae632 | 2019-03-04 10:31:03 -0700 | [diff] [blame] | 785 | pspdir->entries[count].subprog = fw_table[i].subprog; |
| 786 | pspdir->entries[count].rsvd = 0; |
Marshall Dawson | 239286c | 2019-02-23 16:42:46 -0700 | [diff] [blame] | 787 | pspdir->entries[count].size = 0xFFFFFFFF; |
Marshall Dawson | ef79fcc | 2019-04-01 10:16:41 -0600 | [diff] [blame] | 788 | pspdir->entries[count].addr = fw_table[i].other; |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 789 | pspdir->entries[count].address_mode = 0; |
Marshall Dawson | c38c0c9 | 2019-02-23 16:41:35 -0700 | [diff] [blame] | 790 | count++; |
Marshall Dawson | 7c1e142 | 2019-04-11 09:44:43 -0600 | [diff] [blame] | 791 | } else if (fw_table[i].type == AMD_FW_PSP_NVRAM) { |
| 792 | if (fw_table[i].filename == NULL) |
| 793 | continue; |
| 794 | /* TODO: Add a way to reserve for NVRAM without |
| 795 | * requiring a filename. This isn't a feature used |
| 796 | * by coreboot systems, so priority is very low. |
| 797 | */ |
| 798 | ctx->current = ALIGN(ctx->current, ERASE_ALIGNMENT); |
| 799 | bytes = copy_blob(BUFF_CURRENT(*ctx), |
| 800 | fw_table[i].filename, BUFF_ROOM(*ctx)); |
| 801 | if (bytes <= 0) { |
| 802 | free(ctx->rom); |
| 803 | exit(1); |
| 804 | } |
| 805 | |
| 806 | pspdir->entries[count].type = fw_table[i].type; |
| 807 | pspdir->entries[count].subprog = fw_table[i].subprog; |
| 808 | pspdir->entries[count].rsvd = 0; |
| 809 | pspdir->entries[count].size = ALIGN(bytes, |
| 810 | ERASE_ALIGNMENT); |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 811 | pspdir->entries[count].addr = |
Robert Zieba | 29bc79f | 2022-03-14 15:59:12 -0600 | [diff] [blame] | 812 | RUN_CURRENT_MODE(*ctx, AMD_ADDR_REL_BIOS); |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 813 | pspdir->entries[count].address_mode = |
Robert Zieba | 29bc79f | 2022-03-14 15:59:12 -0600 | [diff] [blame] | 814 | SET_ADDR_MODE(pspdir, AMD_ADDR_REL_BIOS); |
Marshall Dawson | 7c1e142 | 2019-04-11 09:44:43 -0600 | [diff] [blame] | 815 | |
| 816 | ctx->current = ALIGN(ctx->current + bytes, |
| 817 | BLOB_ERASE_ALIGNMENT); |
| 818 | count++; |
zbao | c3a08a9 | 2016-03-02 14:47:27 +0800 | [diff] [blame] | 819 | } else if (fw_table[i].filename != NULL) { |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 820 | bytes = copy_blob(BUFF_CURRENT(*ctx), |
| 821 | fw_table[i].filename, BUFF_ROOM(*ctx)); |
Marshall Dawson | 02bd773 | 2019-03-13 14:43:17 -0600 | [diff] [blame] | 822 | if (bytes < 0) { |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 823 | free(ctx->rom); |
Marshall Dawson | 8e0dca0 | 2019-02-27 18:40:49 -0700 | [diff] [blame] | 824 | exit(1); |
| 825 | } |
| 826 | |
Marshall Dawson | 239286c | 2019-02-23 16:42:46 -0700 | [diff] [blame] | 827 | pspdir->entries[count].type = fw_table[i].type; |
Marshall Dawson | dbae632 | 2019-03-04 10:31:03 -0700 | [diff] [blame] | 828 | pspdir->entries[count].subprog = fw_table[i].subprog; |
| 829 | pspdir->entries[count].rsvd = 0; |
Marshall Dawson | 8e0dca0 | 2019-02-27 18:40:49 -0700 | [diff] [blame] | 830 | pspdir->entries[count].size = (uint32_t)bytes; |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 831 | pspdir->entries[count].addr = RUN_CURRENT(*ctx); |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 832 | pspdir->entries[count].address_mode = SET_ADDR_MODE_BY_TABLE(pspdir); |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 833 | |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 834 | ctx->current = ALIGN(ctx->current + bytes, |
| 835 | BLOB_ALIGNMENT); |
Marshall Dawson | c38c0c9 | 2019-02-23 16:41:35 -0700 | [diff] [blame] | 836 | count++; |
zbao | c3a08a9 | 2016-03-02 14:47:27 +0800 | [diff] [blame] | 837 | } else { |
| 838 | /* This APU doesn't have this firmware. */ |
| 839 | } |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 840 | } |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 841 | |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 842 | if (recovery_ab && (pspdir2 != NULL)) { |
Zheng Bao | fdd47ef | 2021-09-17 13:30:08 +0800 | [diff] [blame] | 843 | if (cb_config->need_ish) { /* Need ISH */ |
| 844 | ish_a_dir = new_ish_dir(ctx); |
| 845 | if (pspdir2_b != NULL) |
| 846 | ish_b_dir = new_ish_dir(ctx); |
| 847 | } |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 848 | pspdir->header.num_entries = count; |
Zheng Bao | fdd47ef | 2021-09-17 13:30:08 +0800 | [diff] [blame] | 849 | integrate_psp_ab(ctx, pspdir, pspdir2, ish_a_dir, |
| 850 | AMD_FW_RECOVERYAB_A, soc_id); |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 851 | if (pspdir2_b != NULL) |
Zheng Bao | fdd47ef | 2021-09-17 13:30:08 +0800 | [diff] [blame] | 852 | integrate_psp_ab(ctx, pspdir, pspdir2_b, ish_b_dir, |
| 853 | AMD_FW_RECOVERYAB_B, soc_id); |
Karthikeyan Ramasubramanian | ad06bae | 2022-04-08 14:19:55 -0600 | [diff] [blame] | 854 | else |
| 855 | integrate_psp_ab(ctx, pspdir, pspdir2, ish_b_dir, |
| 856 | AMD_FW_RECOVERYAB_B, soc_id); |
| 857 | |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 858 | count = pspdir->header.num_entries; |
| 859 | } else if (pspdir2 != NULL) { |
Zheng Bao | 5164e4b | 2021-10-30 12:09:07 +0800 | [diff] [blame] | 860 | assert_fw_entry(count, MAX_PSP_ENTRIES, ctx); |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 861 | pspdir->entries[count].type = AMD_FW_L2_PTR; |
| 862 | pspdir->entries[count].subprog = 0; |
| 863 | pspdir->entries[count].rsvd = 0; |
| 864 | pspdir->entries[count].size = sizeof(pspdir2->header) |
| 865 | + pspdir2->header.num_entries |
| 866 | * sizeof(psp_directory_entry); |
| 867 | |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 868 | pspdir->entries[count].addr = |
Robert Zieba | 29bc79f | 2022-03-14 15:59:12 -0600 | [diff] [blame] | 869 | BUFF_TO_RUN_MODE(*ctx, pspdir2, AMD_ADDR_REL_BIOS); |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 870 | pspdir->entries[count].address_mode = |
Robert Zieba | 29bc79f | 2022-03-14 15:59:12 -0600 | [diff] [blame] | 871 | SET_ADDR_MODE(pspdir, AMD_ADDR_REL_BIOS); |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 872 | count++; |
| 873 | } |
| 874 | |
Zheng Bao | bf29a0d | 2020-12-03 23:00:48 +0800 | [diff] [blame] | 875 | fill_dir_header(pspdir, count, cookie, ctx); |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 876 | ctx->current_table = current_table_save; |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 877 | } |
| 878 | |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 879 | static void add_psp_firmware_entry(context *ctx, |
| 880 | psp_directory_table *pspdir, |
| 881 | void *table, amd_fw_type type, uint32_t size) |
| 882 | { |
| 883 | uint32_t count = pspdir->header.num_entries; |
| 884 | uint32_t index; |
| 885 | uint32_t current_table_save; |
| 886 | |
| 887 | current_table_save = ctx->current_table; |
| 888 | ctx->current_table = (char *)pspdir - ctx->rom; |
| 889 | |
| 890 | /* If there is an entry of "type", replace it. */ |
| 891 | for (index = 0; index < count; index++) { |
| 892 | if (pspdir->entries[index].type == (uint8_t)type) |
| 893 | break; |
| 894 | } |
| 895 | |
| 896 | assert_fw_entry(count, MAX_PSP_ENTRIES, ctx); |
| 897 | pspdir->entries[index].type = (uint8_t)type; |
| 898 | pspdir->entries[index].subprog = 0; |
| 899 | pspdir->entries[index].rsvd = 0; |
| 900 | pspdir->entries[index].addr = BUFF_TO_RUN(*ctx, table); |
| 901 | pspdir->entries[index].address_mode = SET_ADDR_MODE_BY_TABLE(pspdir); |
| 902 | pspdir->entries[index].size = size; |
| 903 | if (index == count) |
| 904 | count++; |
| 905 | |
| 906 | pspdir->header.num_entries = count; |
| 907 | pspdir->header.checksum = fletcher32(&pspdir->header.num_entries, |
| 908 | count * sizeof(psp_directory_entry) |
| 909 | + sizeof(pspdir->header.num_entries) |
| 910 | + sizeof(pspdir->header.additional_info)); |
| 911 | |
| 912 | ctx->current_table = current_table_save; |
| 913 | } |
| 914 | |
Zheng Bao | ba3af5e | 2021-11-04 18:56:47 +0800 | [diff] [blame] | 915 | static void *new_bios_dir(context *ctx, bool multi) |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 916 | { |
| 917 | void *ptr; |
| 918 | |
| 919 | /* |
| 920 | * Force both onto boundary when multi. Primary table is after |
| 921 | * updatable table, so alignment ensures primary can stay intact |
| 922 | * if secondary is reprogrammed. |
| 923 | */ |
| 924 | if (multi) |
| 925 | ctx->current = ALIGN(ctx->current, TABLE_ERASE_ALIGNMENT); |
| 926 | else |
| 927 | ctx->current = ALIGN(ctx->current, TABLE_ALIGNMENT); |
| 928 | ptr = BUFF_CURRENT(*ctx); |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 929 | ((bios_directory_hdr *) ptr)->additional_info = 0; |
| 930 | ((bios_directory_hdr *) ptr)->additional_info_fields.address_mode = ctx->address_mode; |
| 931 | ctx->current_table = ctx->current; |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 932 | ctx->current += sizeof(bios_directory_hdr) |
| 933 | + MAX_BIOS_ENTRIES * sizeof(bios_directory_entry); |
| 934 | return ptr; |
| 935 | } |
| 936 | |
| 937 | static int locate_bdt2_bios(bios_directory_table *level2, |
| 938 | uint64_t *source, uint32_t *size) |
| 939 | { |
Zheng Bao | 6d402ac | 2020-10-01 16:16:30 +0800 | [diff] [blame] | 940 | uint32_t i; |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 941 | |
| 942 | *source = 0; |
| 943 | *size = 0; |
| 944 | if (!level2) |
| 945 | return 0; |
| 946 | |
| 947 | for (i = 0 ; i < level2->header.num_entries ; i++) { |
| 948 | if (level2->entries[i].type == AMD_BIOS_BIN) { |
| 949 | *source = level2->entries[i].source; |
| 950 | *size = level2->entries[i].size; |
| 951 | return 1; |
| 952 | } |
| 953 | } |
| 954 | return 0; |
| 955 | } |
| 956 | |
| 957 | static int have_bios_tables(amd_bios_entry *table) |
| 958 | { |
| 959 | int i; |
| 960 | |
| 961 | for (i = 0 ; table[i].type != AMD_BIOS_INVALID; i++) { |
| 962 | if (table[i].level & BDT_LVL1 && table[i].filename) |
| 963 | return 1; |
| 964 | } |
| 965 | return 0; |
| 966 | } |
| 967 | |
Marshall Dawson | c4a8c48 | 2020-01-21 17:17:59 -0700 | [diff] [blame] | 968 | static int find_bios_entry(amd_bios_type type) |
| 969 | { |
| 970 | int i; |
| 971 | |
| 972 | for (i = 0; amd_bios_table[i].type != AMD_BIOS_INVALID; i++) { |
| 973 | if (amd_bios_table[i].type == type) |
| 974 | return i; |
| 975 | } |
| 976 | return -1; |
| 977 | } |
| 978 | |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 979 | static void integrate_bios_firmwares(context *ctx, |
| 980 | bios_directory_table *biosdir, |
| 981 | bios_directory_table *biosdir2, |
| 982 | amd_bios_entry *fw_table, |
Zheng Bao | 2079589 | 2021-08-20 14:58:22 +0800 | [diff] [blame] | 983 | uint32_t cookie, |
| 984 | amd_cb_config *cb_config) |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 985 | { |
| 986 | ssize_t bytes; |
Martin Roth | ec93313 | 2019-07-13 20:03:34 -0600 | [diff] [blame] | 987 | unsigned int i, count; |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 988 | int level; |
Marshall Dawson | c4a8c48 | 2020-01-21 17:17:59 -0700 | [diff] [blame] | 989 | int apob_idx; |
Martin Roth | eca423b | 2020-09-01 10:54:11 -0600 | [diff] [blame] | 990 | uint32_t size; |
| 991 | uint64_t source; |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 992 | |
| 993 | /* This function can create a primary table, a secondary table, or a |
| 994 | * flattened table which contains all applicable types. These if-else |
| 995 | * statements infer what the caller intended. If a 2nd-level cookie |
| 996 | * is passed, clearly a 2nd-level table is intended. However, a |
| 997 | * 1st-level cookie may indicate level 1 or flattened. If the caller |
| 998 | * passes a pointer to a 2nd-level table, then assume not flat. |
| 999 | */ |
Zheng Bao | ba3af5e | 2021-11-04 18:56:47 +0800 | [diff] [blame] | 1000 | if (!cb_config->multi_level) |
Zheng Bao | 2079589 | 2021-08-20 14:58:22 +0800 | [diff] [blame] | 1001 | level = BDT_BOTH; |
Zheng Bao | 96a3371 | 2021-06-11 15:54:40 +0800 | [diff] [blame] | 1002 | else if (cookie == BHDL2_COOKIE) |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1003 | level = BDT_LVL2; |
| 1004 | else if (biosdir2) |
| 1005 | level = BDT_LVL1; |
| 1006 | else |
| 1007 | level = BDT_BOTH; |
| 1008 | |
Zheng Bao | bf29a0d | 2020-12-03 23:00:48 +0800 | [diff] [blame] | 1009 | ctx->current = ALIGN(ctx->current, TABLE_ALIGNMENT); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1010 | |
| 1011 | for (i = 0, count = 0; fw_table[i].type != AMD_BIOS_INVALID; i++) { |
| 1012 | if (!(fw_table[i].level & level)) |
| 1013 | continue; |
| 1014 | if (fw_table[i].filename == NULL && ( |
| 1015 | fw_table[i].type != AMD_BIOS_APOB && |
| 1016 | fw_table[i].type != AMD_BIOS_APOB_NV && |
| 1017 | fw_table[i].type != AMD_BIOS_L2_PTR && |
Martin Roth | 9455474 | 2020-04-14 14:59:36 -0600 | [diff] [blame] | 1018 | fw_table[i].type != AMD_BIOS_BIN && |
| 1019 | fw_table[i].type != AMD_BIOS_PSP_SHARED_MEM)) |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1020 | continue; |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1021 | |
| 1022 | /* BIOS Directory items may have additional requirements */ |
| 1023 | |
Martin Roth | 48dd9fe | 2020-07-29 16:32:25 -0600 | [diff] [blame] | 1024 | /* Check APOB_NV requirements */ |
| 1025 | if (fw_table[i].type == AMD_BIOS_APOB_NV) { |
| 1026 | if (!fw_table[i].size && !fw_table[i].src) |
| 1027 | continue; /* APOB_NV not used */ |
| 1028 | if (fw_table[i].src && !fw_table[i].size) { |
Zheng Bao | 77a2c67 | 2020-10-01 17:05:43 +0800 | [diff] [blame] | 1029 | fprintf(stderr, "Error: APOB NV address provided, but no size\n"); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1030 | free(ctx->rom); |
| 1031 | exit(1); |
| 1032 | } |
Martin Roth | 48dd9fe | 2020-07-29 16:32:25 -0600 | [diff] [blame] | 1033 | /* If the APOB isn't used, APOB_NV isn't used either */ |
Marshall Dawson | c4a8c48 | 2020-01-21 17:17:59 -0700 | [diff] [blame] | 1034 | apob_idx = find_bios_entry(AMD_BIOS_APOB); |
Martin Roth | 48dd9fe | 2020-07-29 16:32:25 -0600 | [diff] [blame] | 1035 | if (apob_idx < 0 || !fw_table[apob_idx].dest) |
| 1036 | continue; /* APOV NV not supported */ |
Marshall Dawson | c4a8c48 | 2020-01-21 17:17:59 -0700 | [diff] [blame] | 1037 | } |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1038 | |
| 1039 | /* APOB_DATA needs destination */ |
| 1040 | if (fw_table[i].type == AMD_BIOS_APOB && !fw_table[i].dest) { |
Zheng Bao | 77a2c67 | 2020-10-01 17:05:43 +0800 | [diff] [blame] | 1041 | fprintf(stderr, "Error: APOB destination not provided\n"); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1042 | free(ctx->rom); |
| 1043 | exit(1); |
| 1044 | } |
| 1045 | |
| 1046 | /* BIOS binary must have destination and uncompressed size. If |
| 1047 | * no filename given, then user must provide a source address. |
| 1048 | */ |
| 1049 | if (fw_table[i].type == AMD_BIOS_BIN) { |
| 1050 | if (!fw_table[i].dest || !fw_table[i].size) { |
Zheng Bao | 77a2c67 | 2020-10-01 17:05:43 +0800 | [diff] [blame] | 1051 | fprintf(stderr, "Error: BIOS binary destination and uncompressed size are required\n"); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1052 | free(ctx->rom); |
| 1053 | exit(1); |
| 1054 | } |
| 1055 | if (!fw_table[i].filename && !fw_table[i].src) { |
Zheng Bao | 77a2c67 | 2020-10-01 17:05:43 +0800 | [diff] [blame] | 1056 | fprintf(stderr, "Error: BIOS binary assumed outside amdfw.rom but no source address given\n"); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1057 | free(ctx->rom); |
| 1058 | exit(1); |
| 1059 | } |
| 1060 | } |
| 1061 | |
Martin Roth | 9455474 | 2020-04-14 14:59:36 -0600 | [diff] [blame] | 1062 | /* PSP_SHARED_MEM needs a destination and size */ |
| 1063 | if (fw_table[i].type == AMD_BIOS_PSP_SHARED_MEM && |
| 1064 | (!fw_table[i].dest || !fw_table[i].size)) |
| 1065 | continue; |
Zheng Bao | 5164e4b | 2021-10-30 12:09:07 +0800 | [diff] [blame] | 1066 | assert_fw_entry(count, MAX_BIOS_ENTRIES, ctx); |
Martin Roth | 9455474 | 2020-04-14 14:59:36 -0600 | [diff] [blame] | 1067 | |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1068 | biosdir->entries[count].type = fw_table[i].type; |
| 1069 | biosdir->entries[count].region_type = fw_table[i].region_type; |
| 1070 | biosdir->entries[count].dest = fw_table[i].dest ? |
| 1071 | fw_table[i].dest : (uint64_t)-1; |
| 1072 | biosdir->entries[count].reset = fw_table[i].reset; |
| 1073 | biosdir->entries[count].copy = fw_table[i].copy; |
| 1074 | biosdir->entries[count].ro = fw_table[i].ro; |
| 1075 | biosdir->entries[count].compressed = fw_table[i].zlib; |
| 1076 | biosdir->entries[count].inst = fw_table[i].inst; |
| 1077 | biosdir->entries[count].subprog = fw_table[i].subpr; |
| 1078 | |
| 1079 | switch (fw_table[i].type) { |
| 1080 | case AMD_BIOS_APOB: |
| 1081 | biosdir->entries[count].size = fw_table[i].size; |
| 1082 | biosdir->entries[count].source = fw_table[i].src; |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 1083 | biosdir->entries[count].address_mode = SET_ADDR_MODE_BY_TABLE(biosdir); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1084 | break; |
| 1085 | case AMD_BIOS_APOB_NV: |
| 1086 | if (fw_table[i].src) { |
| 1087 | /* If source is given, use that and its size */ |
| 1088 | biosdir->entries[count].source = fw_table[i].src; |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 1089 | biosdir->entries[count].address_mode = |
Robert Zieba | 29bc79f | 2022-03-14 15:59:12 -0600 | [diff] [blame] | 1090 | SET_ADDR_MODE(biosdir, AMD_ADDR_REL_BIOS); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1091 | biosdir->entries[count].size = fw_table[i].size; |
| 1092 | } else { |
| 1093 | /* Else reserve size bytes within amdfw.rom */ |
| 1094 | ctx->current = ALIGN(ctx->current, ERASE_ALIGNMENT); |
| 1095 | biosdir->entries[count].source = RUN_CURRENT(*ctx); |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 1096 | biosdir->entries[count].address_mode = |
Robert Zieba | 29bc79f | 2022-03-14 15:59:12 -0600 | [diff] [blame] | 1097 | SET_ADDR_MODE(biosdir, AMD_ADDR_REL_BIOS); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1098 | biosdir->entries[count].size = ALIGN( |
| 1099 | fw_table[i].size, ERASE_ALIGNMENT); |
| 1100 | memset(BUFF_CURRENT(*ctx), 0xff, |
| 1101 | biosdir->entries[count].size); |
| 1102 | ctx->current = ctx->current |
| 1103 | + biosdir->entries[count].size; |
| 1104 | } |
| 1105 | break; |
| 1106 | case AMD_BIOS_BIN: |
| 1107 | /* Don't make a 2nd copy, point to the same one */ |
Martin Roth | eca423b | 2020-09-01 10:54:11 -0600 | [diff] [blame] | 1108 | if (level == BDT_LVL1 && locate_bdt2_bios(biosdir2, &source, &size)) { |
| 1109 | biosdir->entries[count].source = source; |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 1110 | biosdir->entries[count].address_mode = |
Robert Zieba | 29bc79f | 2022-03-14 15:59:12 -0600 | [diff] [blame] | 1111 | SET_ADDR_MODE(biosdir, AMD_ADDR_REL_BIOS); |
Martin Roth | eca423b | 2020-09-01 10:54:11 -0600 | [diff] [blame] | 1112 | biosdir->entries[count].size = size; |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1113 | break; |
Martin Roth | eca423b | 2020-09-01 10:54:11 -0600 | [diff] [blame] | 1114 | } |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1115 | |
| 1116 | /* level 2, or level 1 and no copy found in level 2 */ |
| 1117 | biosdir->entries[count].source = fw_table[i].src; |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 1118 | biosdir->entries[count].address_mode = |
Robert Zieba | 29bc79f | 2022-03-14 15:59:12 -0600 | [diff] [blame] | 1119 | SET_ADDR_MODE(biosdir, AMD_ADDR_REL_BIOS); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1120 | biosdir->entries[count].dest = fw_table[i].dest; |
| 1121 | biosdir->entries[count].size = fw_table[i].size; |
| 1122 | |
| 1123 | if (!fw_table[i].filename) |
| 1124 | break; |
| 1125 | |
| 1126 | bytes = copy_blob(BUFF_CURRENT(*ctx), |
| 1127 | fw_table[i].filename, BUFF_ROOM(*ctx)); |
| 1128 | if (bytes <= 0) { |
| 1129 | free(ctx->rom); |
| 1130 | exit(1); |
| 1131 | } |
| 1132 | |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 1133 | biosdir->entries[count].source = |
Robert Zieba | 29bc79f | 2022-03-14 15:59:12 -0600 | [diff] [blame] | 1134 | RUN_CURRENT_MODE(*ctx, AMD_ADDR_REL_BIOS); |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 1135 | biosdir->entries[count].address_mode = |
Robert Zieba | 29bc79f | 2022-03-14 15:59:12 -0600 | [diff] [blame] | 1136 | SET_ADDR_MODE(biosdir, AMD_ADDR_REL_BIOS); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1137 | |
| 1138 | ctx->current = ALIGN(ctx->current + bytes, 0x100U); |
| 1139 | break; |
Martin Roth | 9455474 | 2020-04-14 14:59:36 -0600 | [diff] [blame] | 1140 | case AMD_BIOS_PSP_SHARED_MEM: |
| 1141 | biosdir->entries[count].dest = fw_table[i].dest; |
| 1142 | biosdir->entries[count].size = fw_table[i].size; |
| 1143 | break; |
| 1144 | |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1145 | default: /* everything else is copied from input */ |
| 1146 | if (fw_table[i].type == AMD_BIOS_APCB || |
| 1147 | fw_table[i].type == AMD_BIOS_APCB_BK) |
| 1148 | ctx->current = ALIGN( |
| 1149 | ctx->current, ERASE_ALIGNMENT); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1150 | bytes = copy_blob(BUFF_CURRENT(*ctx), |
| 1151 | fw_table[i].filename, BUFF_ROOM(*ctx)); |
| 1152 | if (bytes <= 0) { |
| 1153 | free(ctx->rom); |
| 1154 | exit(1); |
| 1155 | } |
| 1156 | |
| 1157 | biosdir->entries[count].size = (uint32_t)bytes; |
| 1158 | biosdir->entries[count].source = RUN_CURRENT(*ctx); |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 1159 | biosdir->entries[count].address_mode = SET_ADDR_MODE_BY_TABLE(biosdir); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1160 | |
| 1161 | ctx->current = ALIGN(ctx->current + bytes, 0x100U); |
| 1162 | break; |
| 1163 | } |
| 1164 | |
| 1165 | count++; |
| 1166 | } |
| 1167 | |
| 1168 | if (biosdir2) { |
Zheng Bao | 5164e4b | 2021-10-30 12:09:07 +0800 | [diff] [blame] | 1169 | assert_fw_entry(count, MAX_BIOS_ENTRIES, ctx); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1170 | biosdir->entries[count].type = AMD_BIOS_L2_PTR; |
Zheng Bao | e8e6043 | 2021-05-24 16:11:12 +0800 | [diff] [blame] | 1171 | biosdir->entries[count].region_type = 0; |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1172 | biosdir->entries[count].size = |
| 1173 | + MAX_BIOS_ENTRIES |
| 1174 | * sizeof(bios_directory_entry); |
| 1175 | biosdir->entries[count].source = |
| 1176 | BUFF_TO_RUN(*ctx, biosdir2); |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 1177 | biosdir->entries[count].address_mode = |
Robert Zieba | 29bc79f | 2022-03-14 15:59:12 -0600 | [diff] [blame] | 1178 | SET_ADDR_MODE(biosdir, AMD_ADDR_REL_BIOS); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1179 | biosdir->entries[count].subprog = 0; |
| 1180 | biosdir->entries[count].inst = 0; |
| 1181 | biosdir->entries[count].copy = 0; |
| 1182 | biosdir->entries[count].compressed = 0; |
| 1183 | biosdir->entries[count].dest = -1; |
| 1184 | biosdir->entries[count].reset = 0; |
| 1185 | biosdir->entries[count].ro = 0; |
| 1186 | count++; |
| 1187 | } |
| 1188 | |
Zheng Bao | bf29a0d | 2020-12-03 23:00:48 +0800 | [diff] [blame] | 1189 | fill_dir_header(biosdir, count, cookie, ctx); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1190 | } |
Matt Papageorge | be4376c | 2020-06-15 11:18:15 -0500 | [diff] [blame] | 1191 | |
| 1192 | enum { |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1193 | AMDFW_OPT_CONFIG = 'c', |
| 1194 | AMDFW_OPT_DEBUG = 'd', |
| 1195 | AMDFW_OPT_HELP = 'h', |
| 1196 | AMDFW_OPT_LIST_DEPEND = 'l', |
| 1197 | |
| 1198 | AMDFW_OPT_XHCI = 128, |
| 1199 | AMDFW_OPT_IMC, |
| 1200 | AMDFW_OPT_GEC, |
| 1201 | AMDFW_OPT_COMBO, |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 1202 | AMDFW_OPT_RECOVERY_AB, |
Karthikeyan Ramasubramanian | ad06bae | 2022-04-08 14:19:55 -0600 | [diff] [blame] | 1203 | AMDFW_OPT_RECOVERY_AB_SINGLE_COPY, |
Zheng Bao | 993b43f | 2021-11-10 12:21:46 +0800 | [diff] [blame] | 1204 | AMDFW_OPT_USE_COMBO, |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1205 | AMDFW_OPT_MULTILEVEL, |
| 1206 | AMDFW_OPT_NVRAM, |
| 1207 | |
| 1208 | AMDFW_OPT_FUSE, |
| 1209 | AMDFW_OPT_UNLOCK, |
| 1210 | AMDFW_OPT_WHITELIST, |
| 1211 | AMDFW_OPT_USE_PSPSECUREOS, |
| 1212 | AMDFW_OPT_LOAD_MP2FW, |
| 1213 | AMDFW_OPT_LOAD_S0I3, |
Zheng Bao | 6c5ec8e | 2022-02-11 11:51:26 +0800 | [diff] [blame] | 1214 | AMDFW_OPT_SPL_TABLE, |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1215 | AMDFW_OPT_VERSTAGE, |
| 1216 | AMDFW_OPT_VERSTAGE_SIG, |
| 1217 | |
| 1218 | AMDFW_OPT_INSTANCE, |
| 1219 | AMDFW_OPT_APCB, |
| 1220 | AMDFW_OPT_APOBBASE, |
| 1221 | AMDFW_OPT_BIOSBIN, |
| 1222 | AMDFW_OPT_BIOSBIN_SOURCE, |
| 1223 | AMDFW_OPT_BIOSBIN_DEST, |
| 1224 | AMDFW_OPT_BIOS_UNCOMP_SIZE, |
| 1225 | AMDFW_OPT_UCODE, |
| 1226 | AMDFW_OPT_APOB_NVBASE, |
| 1227 | AMDFW_OPT_APOB_NVSIZE, |
| 1228 | |
| 1229 | AMDFW_OPT_OUTPUT, |
| 1230 | AMDFW_OPT_FLASHSIZE, |
| 1231 | AMDFW_OPT_LOCATION, |
| 1232 | AMDFW_OPT_ANYWHERE, |
| 1233 | AMDFW_OPT_SHAREDMEM, |
| 1234 | AMDFW_OPT_SHAREDMEM_SIZE, |
| 1235 | AMDFW_OPT_SOC_NAME, |
Matt Papageorge | be4376c | 2020-06-15 11:18:15 -0500 | [diff] [blame] | 1236 | /* begin after ASCII characters */ |
| 1237 | LONGOPT_SPI_READ_MODE = 256, |
| 1238 | LONGOPT_SPI_SPEED = 257, |
| 1239 | LONGOPT_SPI_MICRON_FLAG = 258, |
| 1240 | }; |
| 1241 | |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1242 | static char const optstring[] = {AMDFW_OPT_CONFIG, ':', |
| 1243 | AMDFW_OPT_DEBUG, AMDFW_OPT_HELP, AMDFW_OPT_LIST_DEPEND |
| 1244 | }; |
Marc Jones | 90099b6 | 2016-09-20 21:05:45 -0600 | [diff] [blame] | 1245 | |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1246 | static struct option long_options[] = { |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1247 | {"xhci", required_argument, 0, AMDFW_OPT_XHCI }, |
| 1248 | {"imc", required_argument, 0, AMDFW_OPT_IMC }, |
| 1249 | {"gec", required_argument, 0, AMDFW_OPT_GEC }, |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1250 | /* PSP Directory Table items */ |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1251 | {"combo-capable", no_argument, 0, AMDFW_OPT_COMBO }, |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 1252 | {"recovery-ab", no_argument, 0, AMDFW_OPT_RECOVERY_AB }, |
Karthikeyan Ramasubramanian | ad06bae | 2022-04-08 14:19:55 -0600 | [diff] [blame] | 1253 | {"recovery-ab-single-copy", no_argument, 0, AMDFW_OPT_RECOVERY_AB_SINGLE_COPY }, |
Zheng Bao | 993b43f | 2021-11-10 12:21:46 +0800 | [diff] [blame] | 1254 | {"use-combo", no_argument, 0, AMDFW_OPT_USE_COMBO }, |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1255 | {"multilevel", no_argument, 0, AMDFW_OPT_MULTILEVEL }, |
| 1256 | {"nvram", required_argument, 0, AMDFW_OPT_NVRAM }, |
| 1257 | {"soft-fuse", required_argument, 0, AMDFW_OPT_FUSE }, |
| 1258 | {"token-unlock", no_argument, 0, AMDFW_OPT_UNLOCK }, |
| 1259 | {"whitelist", required_argument, 0, AMDFW_OPT_WHITELIST }, |
| 1260 | {"use-pspsecureos", no_argument, 0, AMDFW_OPT_USE_PSPSECUREOS }, |
| 1261 | {"load-mp2-fw", no_argument, 0, AMDFW_OPT_LOAD_MP2FW }, |
| 1262 | {"load-s0i3", no_argument, 0, AMDFW_OPT_LOAD_S0I3 }, |
Zheng Bao | 6c5ec8e | 2022-02-11 11:51:26 +0800 | [diff] [blame] | 1263 | {"spl-table", required_argument, 0, AMDFW_OPT_SPL_TABLE }, |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1264 | {"verstage", required_argument, 0, AMDFW_OPT_VERSTAGE }, |
| 1265 | {"verstage_sig", required_argument, 0, AMDFW_OPT_VERSTAGE_SIG }, |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1266 | /* BIOS Directory Table items */ |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1267 | {"instance", required_argument, 0, AMDFW_OPT_INSTANCE }, |
| 1268 | {"apcb", required_argument, 0, AMDFW_OPT_APCB }, |
| 1269 | {"apob-base", required_argument, 0, AMDFW_OPT_APOBBASE }, |
| 1270 | {"bios-bin", required_argument, 0, AMDFW_OPT_BIOSBIN }, |
| 1271 | {"bios-bin-src", required_argument, 0, AMDFW_OPT_BIOSBIN_SOURCE }, |
| 1272 | {"bios-bin-dest", required_argument, 0, AMDFW_OPT_BIOSBIN_DEST }, |
| 1273 | {"bios-uncomp-size", required_argument, 0, AMDFW_OPT_BIOS_UNCOMP_SIZE }, |
| 1274 | {"ucode", required_argument, 0, AMDFW_OPT_UCODE }, |
| 1275 | {"apob-nv-base", required_argument, 0, AMDFW_OPT_APOB_NVBASE }, |
| 1276 | {"apob-nv-size", required_argument, 0, AMDFW_OPT_APOB_NVSIZE }, |
Matt Papageorge | be4376c | 2020-06-15 11:18:15 -0500 | [diff] [blame] | 1277 | /* Embedded Firmware Structure items*/ |
| 1278 | {"spi-read-mode", required_argument, 0, LONGOPT_SPI_READ_MODE }, |
| 1279 | {"spi-speed", required_argument, 0, LONGOPT_SPI_SPEED }, |
| 1280 | {"spi-micron-flag", required_argument, 0, LONGOPT_SPI_MICRON_FLAG }, |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1281 | /* other */ |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1282 | {"output", required_argument, 0, AMDFW_OPT_OUTPUT }, |
| 1283 | {"flashsize", required_argument, 0, AMDFW_OPT_FLASHSIZE }, |
| 1284 | {"location", required_argument, 0, AMDFW_OPT_LOCATION }, |
| 1285 | {"anywhere", no_argument, 0, AMDFW_OPT_ANYWHERE }, |
| 1286 | {"sharedmem", required_argument, 0, AMDFW_OPT_SHAREDMEM }, |
| 1287 | {"sharedmem-size", required_argument, 0, AMDFW_OPT_SHAREDMEM_SIZE }, |
| 1288 | {"soc-name", required_argument, 0, AMDFW_OPT_SOC_NAME }, |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 1289 | |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1290 | {"config", required_argument, 0, AMDFW_OPT_CONFIG }, |
| 1291 | {"debug", no_argument, 0, AMDFW_OPT_DEBUG }, |
| 1292 | {"help", no_argument, 0, AMDFW_OPT_HELP }, |
| 1293 | {"list", no_argument, 0, AMDFW_OPT_LIST_DEPEND }, |
Marshall Dawson | f4b9b41 | 2017-03-17 16:30:51 -0600 | [diff] [blame] | 1294 | {NULL, 0, 0, 0 } |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1295 | }; |
| 1296 | |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 1297 | void register_fw_fuse(char *str) |
Marshall Dawson | ef79fcc | 2019-04-01 10:16:41 -0600 | [diff] [blame] | 1298 | { |
Zheng Bao | 6d402ac | 2020-10-01 16:16:30 +0800 | [diff] [blame] | 1299 | uint32_t i; |
Marshall Dawson | ef79fcc | 2019-04-01 10:16:41 -0600 | [diff] [blame] | 1300 | |
| 1301 | for (i = 0; i < sizeof(amd_psp_fw_table) / sizeof(amd_fw_entry); i++) { |
| 1302 | if (amd_psp_fw_table[i].type != AMD_PSP_FUSE_CHAIN) |
| 1303 | continue; |
| 1304 | |
| 1305 | amd_psp_fw_table[i].other = strtoull(str, NULL, 16); |
| 1306 | return; |
| 1307 | } |
| 1308 | } |
| 1309 | |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1310 | static void register_fw_token_unlock(void) |
| 1311 | { |
Zheng Bao | 6d402ac | 2020-10-01 16:16:30 +0800 | [diff] [blame] | 1312 | uint32_t i; |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1313 | |
| 1314 | for (i = 0; i < sizeof(amd_psp_fw_table) / sizeof(amd_fw_entry); i++) { |
| 1315 | if (amd_psp_fw_table[i].type != AMD_TOKEN_UNLOCK) |
| 1316 | continue; |
| 1317 | |
| 1318 | amd_psp_fw_table[i].other = 1; |
| 1319 | return; |
| 1320 | } |
| 1321 | } |
| 1322 | |
Marshall Dawson | dbae632 | 2019-03-04 10:31:03 -0700 | [diff] [blame] | 1323 | static void register_fw_filename(amd_fw_type type, uint8_t sub, char filename[]) |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1324 | { |
Martin Roth | 8806f7f | 2016-11-08 10:44:18 -0700 | [diff] [blame] | 1325 | unsigned int i; |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1326 | |
Martin Roth | cd15bc8 | 2016-11-08 11:34:02 -0700 | [diff] [blame] | 1327 | for (i = 0; i < sizeof(amd_fw_table) / sizeof(amd_fw_entry); i++) { |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1328 | if (amd_fw_table[i].type == type) { |
| 1329 | amd_fw_table[i].filename = filename; |
| 1330 | return; |
| 1331 | } |
| 1332 | } |
| 1333 | |
Marshall Dawson | 0e02ce8 | 2019-03-04 16:50:37 -0700 | [diff] [blame] | 1334 | for (i = 0; i < sizeof(amd_psp_fw_table) / sizeof(amd_fw_entry); i++) { |
Marshall Dawson | dbae632 | 2019-03-04 10:31:03 -0700 | [diff] [blame] | 1335 | if (amd_psp_fw_table[i].type != type) |
| 1336 | continue; |
| 1337 | |
| 1338 | if (amd_psp_fw_table[i].subprog == sub) { |
Marshall Dawson | 0e02ce8 | 2019-03-04 16:50:37 -0700 | [diff] [blame] | 1339 | amd_psp_fw_table[i].filename = filename; |
| 1340 | return; |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1341 | } |
| 1342 | } |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1343 | } |
| 1344 | |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1345 | static void register_bdt_data(amd_bios_type type, int sub, int ins, char name[]) |
| 1346 | { |
Zheng Bao | 6d402ac | 2020-10-01 16:16:30 +0800 | [diff] [blame] | 1347 | uint32_t i; |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1348 | |
| 1349 | for (i = 0; i < sizeof(amd_bios_table) / sizeof(amd_bios_entry); i++) { |
| 1350 | if (amd_bios_table[i].type == type |
| 1351 | && amd_bios_table[i].inst == ins |
| 1352 | && amd_bios_table[i].subpr == sub) { |
| 1353 | amd_bios_table[i].filename = name; |
| 1354 | return; |
| 1355 | } |
| 1356 | } |
| 1357 | } |
| 1358 | |
Martin Roth | ec93313 | 2019-07-13 20:03:34 -0600 | [diff] [blame] | 1359 | static void register_fw_addr(amd_bios_type type, char *src_str, |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1360 | char *dst_str, char *size_str) |
| 1361 | { |
Zheng Bao | 6d402ac | 2020-10-01 16:16:30 +0800 | [diff] [blame] | 1362 | uint32_t i; |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1363 | for (i = 0; i < sizeof(amd_bios_table) / sizeof(amd_bios_entry); i++) { |
| 1364 | if (amd_bios_table[i].type != type) |
| 1365 | continue; |
| 1366 | |
| 1367 | if (src_str) |
| 1368 | amd_bios_table[i].src = strtoull(src_str, NULL, 16); |
| 1369 | if (dst_str) |
| 1370 | amd_bios_table[i].dest = strtoull(dst_str, NULL, 16); |
| 1371 | if (size_str) |
| 1372 | amd_bios_table[i].size = strtoul(size_str, NULL, 16); |
| 1373 | |
| 1374 | return; |
| 1375 | } |
| 1376 | } |
| 1377 | |
Zheng Bao | c3007f3 | 2022-04-03 12:53:51 +0800 | [diff] [blame] | 1378 | static int set_efs_table(uint8_t soc_id, amd_cb_config *cb_config, |
| 1379 | embedded_firmware *amd_romsig, uint8_t efs_spi_readmode, |
| 1380 | uint8_t efs_spi_speed, uint8_t efs_spi_micron_flag) |
Matt Papageorge | be4376c | 2020-06-15 11:18:15 -0500 | [diff] [blame] | 1381 | { |
| 1382 | if ((efs_spi_readmode == 0xFF) || (efs_spi_speed == 0xFF)) { |
Zheng Bao | 77a2c67 | 2020-10-01 17:05:43 +0800 | [diff] [blame] | 1383 | fprintf(stderr, "Error: EFS read mode and SPI speed must be set\n"); |
Matt Papageorge | be4376c | 2020-06-15 11:18:15 -0500 | [diff] [blame] | 1384 | return 1; |
| 1385 | } |
Zheng Bao | c3007f3 | 2022-04-03 12:53:51 +0800 | [diff] [blame] | 1386 | |
| 1387 | /* amd_romsig->efs_gen introduced after RAVEN/PICASSO. |
| 1388 | * Leave as 0xffffffff for first gen */ |
| 1389 | if (cb_config->second_gen) { |
| 1390 | amd_romsig->efs_gen.gen = EFS_SECOND_GEN; |
| 1391 | amd_romsig->efs_gen.reserved = 0; |
| 1392 | } else { |
Zheng Bao | 487d045 | 2022-04-03 12:50:07 +0800 | [diff] [blame] | 1393 | amd_romsig->efs_gen.gen = EFS_BEFORE_SECOND_GEN; |
| 1394 | amd_romsig->efs_gen.reserved = ~0; |
Zheng Bao | c3007f3 | 2022-04-03 12:53:51 +0800 | [diff] [blame] | 1395 | } |
| 1396 | |
| 1397 | switch (soc_id) { |
| 1398 | case PLATFORM_STONEYRIDGE: |
Matt Papageorge | be4376c | 2020-06-15 11:18:15 -0500 | [diff] [blame] | 1399 | amd_romsig->spi_readmode_f15_mod_60_6f = efs_spi_readmode; |
| 1400 | amd_romsig->fast_speed_new_f15_mod_60_6f = efs_spi_speed; |
| 1401 | break; |
| 1402 | case PLATFORM_RAVEN: |
| 1403 | case PLATFORM_PICASSO: |
Matt Papageorge | be4376c | 2020-06-15 11:18:15 -0500 | [diff] [blame] | 1404 | amd_romsig->spi_readmode_f17_mod_00_2f = efs_spi_readmode; |
| 1405 | amd_romsig->spi_fastspeed_f17_mod_00_2f = efs_spi_speed; |
| 1406 | switch (efs_spi_micron_flag) { |
| 1407 | case 0: |
| 1408 | amd_romsig->qpr_dummy_cycle_f17_mod_00_2f = 0xff; |
| 1409 | break; |
| 1410 | case 1: |
| 1411 | amd_romsig->qpr_dummy_cycle_f17_mod_00_2f = 0xa; |
| 1412 | break; |
| 1413 | default: |
Zheng Bao | 77a2c67 | 2020-10-01 17:05:43 +0800 | [diff] [blame] | 1414 | fprintf(stderr, "Error: EFS Micron flag must be correctly set.\n\n"); |
Matt Papageorge | be4376c | 2020-06-15 11:18:15 -0500 | [diff] [blame] | 1415 | return 1; |
| 1416 | } |
| 1417 | break; |
| 1418 | case PLATFORM_RENOIR: |
| 1419 | case PLATFORM_LUCIENNE: |
Zheng Bao | bf29a0d | 2020-12-03 23:00:48 +0800 | [diff] [blame] | 1420 | case PLATFORM_CEZANNE: |
Zheng Bao | 535ec53 | 2021-08-12 16:30:19 +0800 | [diff] [blame] | 1421 | case PLATFORM_MENDOCINO: |
Felix Held | b18a4c7 | 2022-03-29 02:34:11 +0200 | [diff] [blame] | 1422 | case PLATFORM_SABRINA: |
Matt Papageorge | be4376c | 2020-06-15 11:18:15 -0500 | [diff] [blame] | 1423 | amd_romsig->spi_readmode_f17_mod_30_3f = efs_spi_readmode; |
| 1424 | amd_romsig->spi_fastspeed_f17_mod_30_3f = efs_spi_speed; |
| 1425 | switch (efs_spi_micron_flag) { |
| 1426 | case 0: |
| 1427 | amd_romsig->micron_detect_f17_mod_30_3f = 0xff; |
| 1428 | break; |
| 1429 | case 1: |
| 1430 | amd_romsig->micron_detect_f17_mod_30_3f = 0xaa; |
| 1431 | break; |
| 1432 | case 2: |
| 1433 | amd_romsig->micron_detect_f17_mod_30_3f = 0x55; |
| 1434 | break; |
| 1435 | default: |
Zheng Bao | 77a2c67 | 2020-10-01 17:05:43 +0800 | [diff] [blame] | 1436 | fprintf(stderr, "Error: EFS Micron flag must be correctly set.\n\n"); |
Matt Papageorge | be4376c | 2020-06-15 11:18:15 -0500 | [diff] [blame] | 1437 | return 1; |
| 1438 | } |
| 1439 | break; |
| 1440 | case PLATFORM_UNKNOWN: |
| 1441 | default: |
Zheng Bao | 77a2c67 | 2020-10-01 17:05:43 +0800 | [diff] [blame] | 1442 | fprintf(stderr, "Error: Invalid SOC name.\n\n"); |
Matt Papageorge | be4376c | 2020-06-15 11:18:15 -0500 | [diff] [blame] | 1443 | return 1; |
| 1444 | } |
| 1445 | return 0; |
| 1446 | } |
| 1447 | |
| 1448 | static int identify_platform(char *soc_name) |
| 1449 | { |
| 1450 | if (!strcasecmp(soc_name, "Stoneyridge")) |
| 1451 | return PLATFORM_STONEYRIDGE; |
| 1452 | else if (!strcasecmp(soc_name, "Raven")) |
| 1453 | return PLATFORM_RAVEN; |
| 1454 | else if (!strcasecmp(soc_name, "Picasso")) |
| 1455 | return PLATFORM_PICASSO; |
Zheng Bao | bf29a0d | 2020-12-03 23:00:48 +0800 | [diff] [blame] | 1456 | else if (!strcasecmp(soc_name, "Cezanne")) |
| 1457 | return PLATFORM_CEZANNE; |
Zheng Bao | 535ec53 | 2021-08-12 16:30:19 +0800 | [diff] [blame] | 1458 | else if (!strcasecmp(soc_name, "Mendocino")) |
| 1459 | return PLATFORM_MENDOCINO; |
Matt Papageorge | be4376c | 2020-06-15 11:18:15 -0500 | [diff] [blame] | 1460 | else if (!strcasecmp(soc_name, "Renoir")) |
| 1461 | return PLATFORM_RENOIR; |
| 1462 | else if (!strcasecmp(soc_name, "Lucienne")) |
| 1463 | return PLATFORM_LUCIENNE; |
Felix Held | b18a4c7 | 2022-03-29 02:34:11 +0200 | [diff] [blame] | 1464 | else if (!strcasecmp(soc_name, "Sabrina")) |
| 1465 | return PLATFORM_SABRINA; |
Matt Papageorge | be4376c | 2020-06-15 11:18:15 -0500 | [diff] [blame] | 1466 | else |
| 1467 | return PLATFORM_UNKNOWN; |
| 1468 | |
| 1469 | } |
| 1470 | |
Felix Held | f8e2e47 | 2022-03-29 23:28:49 +0200 | [diff] [blame] | 1471 | static bool needs_ish(enum platform platform_type) |
| 1472 | { |
| 1473 | if (platform_type == PLATFORM_SABRINA) |
| 1474 | return true; |
| 1475 | else |
| 1476 | return false; |
| 1477 | } |
| 1478 | |
Zheng Bao | c3007f3 | 2022-04-03 12:53:51 +0800 | [diff] [blame] | 1479 | static bool is_second_gen(enum platform platform_type) |
| 1480 | { |
| 1481 | switch (platform_type) { |
| 1482 | case PLATFORM_STONEYRIDGE: |
| 1483 | case PLATFORM_RAVEN: |
| 1484 | case PLATFORM_PICASSO: |
| 1485 | return false; |
| 1486 | case PLATFORM_RENOIR: |
| 1487 | case PLATFORM_LUCIENNE: |
| 1488 | case PLATFORM_CEZANNE: |
| 1489 | case PLATFORM_SABRINA: |
| 1490 | return true; |
| 1491 | case PLATFORM_UNKNOWN: |
| 1492 | default: |
| 1493 | fprintf(stderr, "Error: Invalid SOC name.\n\n"); |
| 1494 | return false; |
| 1495 | } |
| 1496 | } |
| 1497 | |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1498 | int main(int argc, char **argv) |
| 1499 | { |
Marshall Dawson | 0e02ce8 | 2019-03-04 16:50:37 -0700 | [diff] [blame] | 1500 | int c; |
Martin Roth | 31d95a2 | 2016-11-08 11:22:12 -0700 | [diff] [blame] | 1501 | int retval = 0; |
Martin Roth | 60f1551 | 2016-11-08 09:55:01 -0700 | [diff] [blame] | 1502 | char *tmp; |
Martin Roth | 8806f7f | 2016-11-08 10:44:18 -0700 | [diff] [blame] | 1503 | char *rom = NULL; |
Marshall Dawson | 239286c | 2019-02-23 16:42:46 -0700 | [diff] [blame] | 1504 | embedded_firmware *amd_romsig; |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 1505 | psp_directory_table *pspdir = NULL; |
| 1506 | psp_directory_table *pspdir2 = NULL; |
| 1507 | psp_directory_table *pspdir2_b = NULL; |
Zheng Bao | 6e2c5a3 | 2021-11-10 14:09:06 +0800 | [diff] [blame] | 1508 | bool comboable = false; |
Marshall Dawson | ef79fcc | 2019-04-01 10:16:41 -0600 | [diff] [blame] | 1509 | int fuse_defined = 0; |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1510 | int targetfd; |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 1511 | char *output = NULL, *config = NULL; |
| 1512 | FILE *config_handle; |
Zheng Bao | 9c8ce3e | 2020-09-28 10:36:29 +0800 | [diff] [blame] | 1513 | context ctx = { 0 }; |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1514 | /* Values cleared after each firmware or parameter, regardless if N/A */ |
| 1515 | uint8_t sub = 0, instance = 0; |
Martin Roth | 0d3b118 | 2017-10-03 14:16:04 -0600 | [diff] [blame] | 1516 | uint32_t dir_location = 0; |
Martin Roth | 37305e7 | 2020-04-07 14:16:39 -0600 | [diff] [blame] | 1517 | bool any_location = 0; |
Martin Roth | 0d3b118 | 2017-10-03 14:16:04 -0600 | [diff] [blame] | 1518 | uint32_t romsig_offset; |
Martin Roth | 60f1551 | 2016-11-08 09:55:01 -0700 | [diff] [blame] | 1519 | uint32_t rom_base_address; |
Matt Papageorge | be4376c | 2020-06-15 11:18:15 -0500 | [diff] [blame] | 1520 | uint8_t soc_id = PLATFORM_UNKNOWN; |
| 1521 | uint8_t efs_spi_readmode = 0xff; |
| 1522 | uint8_t efs_spi_speed = 0xff; |
| 1523 | uint8_t efs_spi_micron_flag = 0xff; |
| 1524 | |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 1525 | amd_cb_config cb_config; |
Zheng Bao | 9e90807 | 2020-10-28 11:39:13 +0800 | [diff] [blame] | 1526 | int debug = 0; |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 1527 | int list_deps = 0; |
| 1528 | |
Zheng Bao | ba3af5e | 2021-11-04 18:56:47 +0800 | [diff] [blame] | 1529 | cb_config.have_whitelist = false; |
| 1530 | cb_config.unlock_secure = false; |
| 1531 | cb_config.use_secureos = false; |
| 1532 | cb_config.load_mp2_fw = false; |
| 1533 | cb_config.s0i3 = false; |
| 1534 | cb_config.multi_level = false; |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 1535 | cb_config.recovery_ab = false; |
Zheng Bao | fdd47ef | 2021-09-17 13:30:08 +0800 | [diff] [blame] | 1536 | cb_config.need_ish = false; |
Karthikeyan Ramasubramanian | ad06bae | 2022-04-08 14:19:55 -0600 | [diff] [blame] | 1537 | cb_config.recovery_ab_single_copy = false; |
Zheng Bao | 993b43f | 2021-11-10 12:21:46 +0800 | [diff] [blame] | 1538 | cb_config.use_combo = false; |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1539 | |
| 1540 | while (1) { |
| 1541 | int optindex = 0; |
| 1542 | |
| 1543 | c = getopt_long(argc, argv, optstring, long_options, &optindex); |
| 1544 | |
| 1545 | if (c == -1) |
| 1546 | break; |
| 1547 | |
| 1548 | switch (c) { |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1549 | case AMDFW_OPT_XHCI: |
Marshall Dawson | dbae632 | 2019-03-04 10:31:03 -0700 | [diff] [blame] | 1550 | register_fw_filename(AMD_FW_XHCI, sub, optarg); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1551 | sub = instance = 0; |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1552 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1553 | case AMDFW_OPT_IMC: |
Marshall Dawson | dbae632 | 2019-03-04 10:31:03 -0700 | [diff] [blame] | 1554 | register_fw_filename(AMD_FW_IMC, sub, optarg); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1555 | sub = instance = 0; |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1556 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1557 | case AMDFW_OPT_GEC: |
Marshall Dawson | dbae632 | 2019-03-04 10:31:03 -0700 | [diff] [blame] | 1558 | register_fw_filename(AMD_FW_GEC, sub, optarg); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1559 | sub = instance = 0; |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1560 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1561 | case AMDFW_OPT_COMBO: |
Zheng Bao | ba3af5e | 2021-11-04 18:56:47 +0800 | [diff] [blame] | 1562 | comboable = true; |
Marshall Dawson | 67d868d | 2019-02-28 11:43:40 -0700 | [diff] [blame] | 1563 | break; |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 1564 | case AMDFW_OPT_RECOVERY_AB: |
| 1565 | cb_config.recovery_ab = true; |
| 1566 | break; |
Karthikeyan Ramasubramanian | ad06bae | 2022-04-08 14:19:55 -0600 | [diff] [blame] | 1567 | case AMDFW_OPT_RECOVERY_AB_SINGLE_COPY: |
| 1568 | cb_config.recovery_ab = true; |
| 1569 | cb_config.recovery_ab_single_copy = true; |
| 1570 | break; |
Zheng Bao | 993b43f | 2021-11-10 12:21:46 +0800 | [diff] [blame] | 1571 | case AMDFW_OPT_USE_COMBO: |
| 1572 | cb_config.use_combo = true; |
| 1573 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1574 | case AMDFW_OPT_MULTILEVEL: |
Zheng Bao | ba3af5e | 2021-11-04 18:56:47 +0800 | [diff] [blame] | 1575 | cb_config.multi_level = true; |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 1576 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1577 | case AMDFW_OPT_UNLOCK: |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1578 | register_fw_token_unlock(); |
Zheng Bao | ba3af5e | 2021-11-04 18:56:47 +0800 | [diff] [blame] | 1579 | cb_config.unlock_secure = true; |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1580 | sub = instance = 0; |
| 1581 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1582 | case AMDFW_OPT_USE_PSPSECUREOS: |
Zheng Bao | ba3af5e | 2021-11-04 18:56:47 +0800 | [diff] [blame] | 1583 | cb_config.use_secureos = true; |
Marshall Dawson | dbae632 | 2019-03-04 10:31:03 -0700 | [diff] [blame] | 1584 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1585 | case AMDFW_OPT_INSTANCE: |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1586 | instance = strtoul(optarg, &tmp, 16); |
| 1587 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1588 | case AMDFW_OPT_LOAD_MP2FW: |
Zheng Bao | ba3af5e | 2021-11-04 18:56:47 +0800 | [diff] [blame] | 1589 | cb_config.load_mp2_fw = true; |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1590 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1591 | case AMDFW_OPT_NVRAM: |
Marshall Dawson | dbae632 | 2019-03-04 10:31:03 -0700 | [diff] [blame] | 1592 | register_fw_filename(AMD_FW_PSP_NVRAM, sub, optarg); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1593 | sub = instance = 0; |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1594 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1595 | case AMDFW_OPT_FUSE: |
Marshall Dawson | ef79fcc | 2019-04-01 10:16:41 -0600 | [diff] [blame] | 1596 | register_fw_fuse(optarg); |
| 1597 | fuse_defined = 1; |
| 1598 | sub = 0; |
| 1599 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1600 | case AMDFW_OPT_APCB: |
Zheng Bao | 5caca94 | 2020-12-04 16:39:38 +0800 | [diff] [blame] | 1601 | if ((instance & 0xF0) == 0) |
| 1602 | register_bdt_data(AMD_BIOS_APCB, sub, instance & 0xF, optarg); |
| 1603 | else |
| 1604 | register_bdt_data(AMD_BIOS_APCB_BK, sub, |
| 1605 | instance & 0xF, optarg); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1606 | sub = instance = 0; |
| 1607 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1608 | case AMDFW_OPT_APOBBASE: |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1609 | /* APOB destination */ |
| 1610 | register_fw_addr(AMD_BIOS_APOB, 0, optarg, 0); |
| 1611 | sub = instance = 0; |
| 1612 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1613 | case AMDFW_OPT_APOB_NVBASE: |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1614 | /* APOB NV source */ |
| 1615 | register_fw_addr(AMD_BIOS_APOB_NV, optarg, 0, 0); |
| 1616 | sub = instance = 0; |
| 1617 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1618 | case AMDFW_OPT_APOB_NVSIZE: |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1619 | /* APOB NV size */ |
| 1620 | register_fw_addr(AMD_BIOS_APOB_NV, 0, 0, optarg); |
| 1621 | sub = instance = 0; |
| 1622 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1623 | case AMDFW_OPT_BIOSBIN: |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1624 | register_bdt_data(AMD_BIOS_BIN, sub, instance, optarg); |
| 1625 | sub = instance = 0; |
| 1626 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1627 | case AMDFW_OPT_BIOSBIN_SOURCE: |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1628 | /* BIOS source */ |
| 1629 | register_fw_addr(AMD_BIOS_BIN, optarg, 0, 0); |
| 1630 | sub = instance = 0; |
| 1631 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1632 | case AMDFW_OPT_BIOSBIN_DEST: |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1633 | /* BIOS destination */ |
| 1634 | register_fw_addr(AMD_BIOS_BIN, 0, optarg, 0); |
| 1635 | sub = instance = 0; |
| 1636 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1637 | case AMDFW_OPT_BIOS_UNCOMP_SIZE: |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1638 | /* BIOS destination size */ |
| 1639 | register_fw_addr(AMD_BIOS_BIN, 0, 0, optarg); |
| 1640 | sub = instance = 0; |
| 1641 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1642 | case AMDFW_OPT_UCODE: |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1643 | register_bdt_data(AMD_BIOS_UCODE, sub, |
| 1644 | instance, optarg); |
| 1645 | sub = instance = 0; |
| 1646 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1647 | case AMDFW_OPT_LOAD_S0I3: |
Zheng Bao | ba3af5e | 2021-11-04 18:56:47 +0800 | [diff] [blame] | 1648 | cb_config.s0i3 = true; |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1649 | break; |
Zheng Bao | 6c5ec8e | 2022-02-11 11:51:26 +0800 | [diff] [blame] | 1650 | case AMDFW_OPT_SPL_TABLE: |
| 1651 | register_fw_filename(AMD_FW_SPL, sub, optarg); |
| 1652 | sub = instance = 0; |
| 1653 | cb_config.have_mb_spl = true; |
| 1654 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1655 | case AMDFW_OPT_WHITELIST: |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1656 | register_fw_filename(AMD_FW_PSP_WHITELIST, sub, optarg); |
| 1657 | sub = instance = 0; |
Zheng Bao | ba3af5e | 2021-11-04 18:56:47 +0800 | [diff] [blame] | 1658 | cb_config.have_whitelist = true; |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1659 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1660 | case AMDFW_OPT_VERSTAGE: |
Martin Roth | d3ce8c8 | 2019-07-13 20:13:07 -0600 | [diff] [blame] | 1661 | register_fw_filename(AMD_FW_PSP_VERSTAGE, sub, optarg); |
| 1662 | sub = instance = 0; |
| 1663 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1664 | case AMDFW_OPT_VERSTAGE_SIG: |
Martin Roth | b1f648f | 2020-09-01 09:36:59 -0600 | [diff] [blame] | 1665 | register_fw_filename(AMD_FW_VERSTAGE_SIG, sub, optarg); |
| 1666 | sub = instance = 0; |
| 1667 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1668 | case AMDFW_OPT_SOC_NAME: |
Matt Papageorge | be4376c | 2020-06-15 11:18:15 -0500 | [diff] [blame] | 1669 | soc_id = identify_platform(optarg); |
| 1670 | if (soc_id == PLATFORM_UNKNOWN) { |
Zheng Bao | 77a2c67 | 2020-10-01 17:05:43 +0800 | [diff] [blame] | 1671 | fprintf(stderr, "Error: Invalid SOC name specified\n\n"); |
Matt Papageorge | be4376c | 2020-06-15 11:18:15 -0500 | [diff] [blame] | 1672 | retval = 1; |
| 1673 | } |
| 1674 | sub = instance = 0; |
| 1675 | break; |
| 1676 | case LONGOPT_SPI_READ_MODE: |
| 1677 | efs_spi_readmode = strtoull(optarg, NULL, 16); |
| 1678 | sub = instance = 0; |
| 1679 | break; |
| 1680 | case LONGOPT_SPI_SPEED: |
| 1681 | efs_spi_speed = strtoull(optarg, NULL, 16); |
| 1682 | sub = instance = 0; |
| 1683 | break; |
| 1684 | case LONGOPT_SPI_MICRON_FLAG: |
| 1685 | efs_spi_micron_flag = strtoull(optarg, NULL, 16); |
| 1686 | sub = instance = 0; |
| 1687 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1688 | case AMDFW_OPT_OUTPUT: |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1689 | output = optarg; |
| 1690 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1691 | case AMDFW_OPT_FLASHSIZE: |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 1692 | ctx.rom_size = (uint32_t)strtoul(optarg, &tmp, 16); |
Martin Roth | 60f1551 | 2016-11-08 09:55:01 -0700 | [diff] [blame] | 1693 | if (*tmp != '\0') { |
Zheng Bao | 77a2c67 | 2020-10-01 17:05:43 +0800 | [diff] [blame] | 1694 | fprintf(stderr, "Error: ROM size specified" |
Martin Roth | 60f1551 | 2016-11-08 09:55:01 -0700 | [diff] [blame] | 1695 | " incorrectly (%s)\n\n", optarg); |
Martin Roth | 31d95a2 | 2016-11-08 11:22:12 -0700 | [diff] [blame] | 1696 | retval = 1; |
Martin Roth | 60f1551 | 2016-11-08 09:55:01 -0700 | [diff] [blame] | 1697 | } |
| 1698 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1699 | case AMDFW_OPT_LOCATION: |
Martin Roth | 0d3b118 | 2017-10-03 14:16:04 -0600 | [diff] [blame] | 1700 | dir_location = (uint32_t)strtoul(optarg, &tmp, 16); |
| 1701 | if (*tmp != '\0') { |
Zheng Bao | 77a2c67 | 2020-10-01 17:05:43 +0800 | [diff] [blame] | 1702 | fprintf(stderr, "Error: Directory Location specified" |
Martin Roth | 0d3b118 | 2017-10-03 14:16:04 -0600 | [diff] [blame] | 1703 | " incorrectly (%s)\n\n", optarg); |
| 1704 | retval = 1; |
| 1705 | } |
| 1706 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1707 | case AMDFW_OPT_ANYWHERE: |
Martin Roth | 37305e7 | 2020-04-07 14:16:39 -0600 | [diff] [blame] | 1708 | any_location = 1; |
| 1709 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1710 | case AMDFW_OPT_SHAREDMEM: |
Martin Roth | 9455474 | 2020-04-14 14:59:36 -0600 | [diff] [blame] | 1711 | /* shared memory destination */ |
| 1712 | register_fw_addr(AMD_BIOS_PSP_SHARED_MEM, 0, optarg, 0); |
| 1713 | sub = instance = 0; |
| 1714 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1715 | case AMDFW_OPT_SHAREDMEM_SIZE: |
Martin Roth | 9455474 | 2020-04-14 14:59:36 -0600 | [diff] [blame] | 1716 | /* shared memory size */ |
| 1717 | register_fw_addr(AMD_BIOS_PSP_SHARED_MEM, NULL, NULL, optarg); |
| 1718 | sub = instance = 0; |
| 1719 | break; |
Martin Roth | 0d3b118 | 2017-10-03 14:16:04 -0600 | [diff] [blame] | 1720 | |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1721 | case AMDFW_OPT_CONFIG: |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 1722 | config = optarg; |
| 1723 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1724 | case AMDFW_OPT_DEBUG: |
Zheng Bao | 9e90807 | 2020-10-28 11:39:13 +0800 | [diff] [blame] | 1725 | debug = 1; |
| 1726 | break; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1727 | case AMDFW_OPT_HELP: |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1728 | usage(); |
Martin Roth | 31d95a2 | 2016-11-08 11:22:12 -0700 | [diff] [blame] | 1729 | return 0; |
Zheng Bao | 806892a | 2021-04-27 17:21:54 +0800 | [diff] [blame] | 1730 | case AMDFW_OPT_LIST_DEPEND: |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 1731 | list_deps = 1; |
| 1732 | break; |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1733 | default: |
| 1734 | break; |
| 1735 | } |
| 1736 | } |
| 1737 | |
Zheng Bao | c3007f3 | 2022-04-03 12:53:51 +0800 | [diff] [blame] | 1738 | cb_config.second_gen = is_second_gen(soc_id); |
| 1739 | |
Felix Held | f8e2e47 | 2022-03-29 23:28:49 +0200 | [diff] [blame] | 1740 | if (needs_ish(soc_id)) |
| 1741 | cb_config.need_ish = true; |
| 1742 | |
Felix Held | 830add6 | 2022-03-29 23:28:10 +0200 | [diff] [blame] | 1743 | if (cb_config.need_ish) |
| 1744 | cb_config.recovery_ab = true; |
| 1745 | |
| 1746 | if (cb_config.recovery_ab) |
| 1747 | cb_config.multi_level = true; |
| 1748 | |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 1749 | if (config) { |
| 1750 | config_handle = fopen(config, "r"); |
| 1751 | if (config_handle == NULL) { |
| 1752 | fprintf(stderr, "Can not open file %s for reading: %s\n", |
| 1753 | config, strerror(errno)); |
| 1754 | exit(1); |
| 1755 | } |
| 1756 | if (process_config(config_handle, &cb_config, list_deps) == 0) { |
| 1757 | fprintf(stderr, "Configuration file %s parsing error\n", config); |
| 1758 | fclose(config_handle); |
| 1759 | exit(1); |
| 1760 | } |
| 1761 | fclose(config_handle); |
| 1762 | } |
Zheng Bao | 9e90807 | 2020-10-28 11:39:13 +0800 | [diff] [blame] | 1763 | /* For debug. */ |
| 1764 | if (debug) { |
| 1765 | dump_psp_firmwares(amd_psp_fw_table); |
| 1766 | dump_bdt_firmwares(amd_bios_table); |
| 1767 | } |
| 1768 | |
Marshall Dawson | ef79fcc | 2019-04-01 10:16:41 -0600 | [diff] [blame] | 1769 | if (!fuse_defined) |
| 1770 | register_fw_fuse(DEFAULT_SOFT_FUSE_CHAIN); |
| 1771 | |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 1772 | if (!output && !list_deps) { |
| 1773 | fprintf(stderr, "Error: Output value is not specified.\n\n"); |
Martin Roth | 31d95a2 | 2016-11-08 11:22:12 -0700 | [diff] [blame] | 1774 | retval = 1; |
| 1775 | } |
| 1776 | |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 1777 | if ((ctx.rom_size % 1024 != 0) && !list_deps) { |
| 1778 | fprintf(stderr, "Error: ROM Size (%d bytes) should be a multiple of" |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 1779 | " 1024 bytes.\n\n", ctx.rom_size); |
Martin Roth | 31d95a2 | 2016-11-08 11:22:12 -0700 | [diff] [blame] | 1780 | retval = 1; |
Martin Roth | 60f1551 | 2016-11-08 09:55:01 -0700 | [diff] [blame] | 1781 | } |
| 1782 | |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 1783 | if ((ctx.rom_size < MIN_ROM_KB * 1024) && !list_deps) { |
| 1784 | fprintf(stderr, "Error: ROM Size (%dKB) must be at least %dKB.\n\n", |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 1785 | ctx.rom_size / 1024, MIN_ROM_KB); |
Martin Roth | 31d95a2 | 2016-11-08 11:22:12 -0700 | [diff] [blame] | 1786 | retval = 1; |
| 1787 | } |
| 1788 | |
| 1789 | if (retval) { |
| 1790 | usage(); |
| 1791 | return retval; |
Martin Roth | 60f1551 | 2016-11-08 09:55:01 -0700 | [diff] [blame] | 1792 | } |
| 1793 | |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 1794 | if (list_deps) { |
| 1795 | return retval; |
| 1796 | } |
| 1797 | |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 1798 | printf(" AMDFWTOOL Using ROM size of %dKB\n", ctx.rom_size / 1024); |
Martin Roth | 60f1551 | 2016-11-08 09:55:01 -0700 | [diff] [blame] | 1799 | |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 1800 | rom_base_address = 0xFFFFFFFF - ctx.rom_size + 1; |
Martin Roth | 0d3b118 | 2017-10-03 14:16:04 -0600 | [diff] [blame] | 1801 | if (dir_location && (dir_location < rom_base_address)) { |
Zheng Bao | 77a2c67 | 2020-10-01 17:05:43 +0800 | [diff] [blame] | 1802 | fprintf(stderr, "Error: Directory location outside of ROM.\n\n"); |
Martin Roth | 0d3b118 | 2017-10-03 14:16:04 -0600 | [diff] [blame] | 1803 | return 1; |
| 1804 | } |
| 1805 | |
Martin Roth | 37305e7 | 2020-04-07 14:16:39 -0600 | [diff] [blame] | 1806 | if (any_location) { |
| 1807 | if (dir_location & 0x3f) { |
Zheng Bao | 77a2c67 | 2020-10-01 17:05:43 +0800 | [diff] [blame] | 1808 | fprintf(stderr, "Error: Invalid Directory location.\n"); |
| 1809 | fprintf(stderr, " Valid locations are 64-byte aligned\n"); |
Martin Roth | 37305e7 | 2020-04-07 14:16:39 -0600 | [diff] [blame] | 1810 | return 1; |
| 1811 | } |
| 1812 | } else { |
| 1813 | switch (dir_location) { |
| 1814 | case 0: /* Fall through */ |
| 1815 | case 0xFFFA0000: /* Fall through */ |
| 1816 | case 0xFFF20000: /* Fall through */ |
| 1817 | case 0xFFE20000: /* Fall through */ |
| 1818 | case 0xFFC20000: /* Fall through */ |
| 1819 | case 0xFF820000: /* Fall through */ |
| 1820 | case 0xFF020000: /* Fall through */ |
| 1821 | break; |
| 1822 | default: |
Zheng Bao | 77a2c67 | 2020-10-01 17:05:43 +0800 | [diff] [blame] | 1823 | fprintf(stderr, "Error: Invalid Directory location.\n"); |
| 1824 | fprintf(stderr, " Valid locations are 0xFFFA0000, 0xFFF20000,\n"); |
| 1825 | fprintf(stderr, " 0xFFE20000, 0xFFC20000, 0xFF820000, 0xFF020000\n"); |
Martin Roth | 37305e7 | 2020-04-07 14:16:39 -0600 | [diff] [blame] | 1826 | return 1; |
| 1827 | } |
Martin Roth | 0d3b118 | 2017-10-03 14:16:04 -0600 | [diff] [blame] | 1828 | } |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 1829 | ctx.rom = malloc(ctx.rom_size); |
| 1830 | if (!ctx.rom) { |
Zheng Bao | 77a2c67 | 2020-10-01 17:05:43 +0800 | [diff] [blame] | 1831 | fprintf(stderr, "Error: Failed to allocate memory\n"); |
Martin Roth | 31d95a2 | 2016-11-08 11:22:12 -0700 | [diff] [blame] | 1832 | return 1; |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 1833 | } |
| 1834 | memset(ctx.rom, 0xFF, ctx.rom_size); |
Martin Roth | 60f1551 | 2016-11-08 09:55:01 -0700 | [diff] [blame] | 1835 | |
Martin Roth | 0d3b118 | 2017-10-03 14:16:04 -0600 | [diff] [blame] | 1836 | if (dir_location) |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 1837 | romsig_offset = ctx.current = dir_location - rom_base_address; |
Martin Roth | 0d3b118 | 2017-10-03 14:16:04 -0600 | [diff] [blame] | 1838 | else |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 1839 | romsig_offset = ctx.current = AMD_ROMSIG_OFFSET; |
Martin Roth | 0d3b118 | 2017-10-03 14:16:04 -0600 | [diff] [blame] | 1840 | |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 1841 | amd_romsig = BUFF_OFFSET(ctx, romsig_offset); |
Marshall Dawson | 239286c | 2019-02-23 16:42:46 -0700 | [diff] [blame] | 1842 | amd_romsig->signature = EMBEDDED_FW_SIGNATURE; |
| 1843 | amd_romsig->imc_entry = 0; |
| 1844 | amd_romsig->gec_entry = 0; |
| 1845 | amd_romsig->xhci_entry = 0; |
Martin Roth | 60f1551 | 2016-11-08 09:55:01 -0700 | [diff] [blame] | 1846 | |
Matt Papageorge | be4376c | 2020-06-15 11:18:15 -0500 | [diff] [blame] | 1847 | if (soc_id != PLATFORM_UNKNOWN) { |
Zheng Bao | c3007f3 | 2022-04-03 12:53:51 +0800 | [diff] [blame] | 1848 | retval = set_efs_table(soc_id, &cb_config, amd_romsig, efs_spi_readmode, |
Zheng Bao | 570645d | 2021-11-03 10:25:03 +0800 | [diff] [blame] | 1849 | efs_spi_speed, efs_spi_micron_flag); |
| 1850 | if (retval) { |
| 1851 | fprintf(stderr, "ERROR: Failed to initialize EFS table!\n"); |
| 1852 | return retval; |
Matt Papageorge | be4376c | 2020-06-15 11:18:15 -0500 | [diff] [blame] | 1853 | } |
| 1854 | } else { |
Zheng Bao | 77a2c67 | 2020-10-01 17:05:43 +0800 | [diff] [blame] | 1855 | fprintf(stderr, "WARNING: No SOC name specified.\n"); |
Matt Papageorge | be4376c | 2020-06-15 11:18:15 -0500 | [diff] [blame] | 1856 | } |
| 1857 | |
Felix Held | 21a8e38 | 2022-03-29 23:10:45 +0200 | [diff] [blame] | 1858 | if (cb_config.need_ish) |
Robert Zieba | 29bc79f | 2022-03-14 15:59:12 -0600 | [diff] [blame] | 1859 | ctx.address_mode = AMD_ADDR_REL_TAB; |
Zheng Bao | c3007f3 | 2022-04-03 12:53:51 +0800 | [diff] [blame] | 1860 | else if (cb_config.second_gen) |
Robert Zieba | 29bc79f | 2022-03-14 15:59:12 -0600 | [diff] [blame] | 1861 | ctx.address_mode = AMD_ADDR_REL_BIOS; |
Zheng Bao | da83d2c | 2021-06-04 19:03:10 +0800 | [diff] [blame] | 1862 | else |
Robert Zieba | 29bc79f | 2022-03-14 15:59:12 -0600 | [diff] [blame] | 1863 | ctx.address_mode = AMD_ADDR_PHYSICAL; |
Zheng Bao | da83d2c | 2021-06-04 19:03:10 +0800 | [diff] [blame] | 1864 | printf(" AMDFWTOOL Using firmware directory location of %s address: 0x%08x\n", |
Robert Zieba | 29bc79f | 2022-03-14 15:59:12 -0600 | [diff] [blame] | 1865 | ctx.address_mode == AMD_ADDR_PHYSICAL ? "absolute" : "relative", |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 1866 | RUN_CURRENT(ctx)); |
Zheng Bao | da83d2c | 2021-06-04 19:03:10 +0800 | [diff] [blame] | 1867 | |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 1868 | integrate_firmwares(&ctx, amd_romsig, amd_fw_table); |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1869 | |
Patrick Georgi | 900a254 | 2020-02-17 16:52:40 +0100 | [diff] [blame] | 1870 | ctx.current = ALIGN(ctx.current, 0x10000U); /* TODO: is it necessary? */ |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 1871 | ctx.current_table = 0; |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 1872 | |
Zheng Bao | 481661e | 2021-08-20 14:47:46 +0800 | [diff] [blame] | 1873 | if (cb_config.multi_level) { |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 1874 | /* Do 2nd PSP directory followed by 1st */ |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 1875 | pspdir2 = new_psp_dir(&ctx, cb_config.multi_level); |
| 1876 | integrate_psp_firmwares(&ctx, pspdir2, NULL, NULL, |
Zheng Bao | fdd47ef | 2021-09-17 13:30:08 +0800 | [diff] [blame] | 1877 | amd_psp_fw_table, PSPL2_COOKIE, soc_id, &cb_config); |
Karthikeyan Ramasubramanian | ad06bae | 2022-04-08 14:19:55 -0600 | [diff] [blame] | 1878 | if (cb_config.recovery_ab && !cb_config.recovery_ab_single_copy) { |
| 1879 | /* Create a copy of PSP Directory 2 in the backup slot B. |
| 1880 | Related biosdir2_b copy will be created later. */ |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 1881 | pspdir2_b = new_psp_dir(&ctx, cb_config.multi_level); |
| 1882 | integrate_psp_firmwares(&ctx, pspdir2_b, NULL, NULL, |
Zheng Bao | fdd47ef | 2021-09-17 13:30:08 +0800 | [diff] [blame] | 1883 | amd_psp_fw_table, PSPL2_COOKIE, soc_id, &cb_config); |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 1884 | } else { |
Karthikeyan Ramasubramanian | ad06bae | 2022-04-08 14:19:55 -0600 | [diff] [blame] | 1885 | /* |
| 1886 | * Either the platform is using only one slot or B is same as above |
| 1887 | * directories for A. Skip creating pspdir2_b here to save flash space. |
| 1888 | * Related biosdir2_b will be skipped automatically. |
| 1889 | */ |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 1890 | pspdir2_b = NULL; /* More explicitly */ |
| 1891 | } |
Zheng Bao | 481661e | 2021-08-20 14:47:46 +0800 | [diff] [blame] | 1892 | pspdir = new_psp_dir(&ctx, cb_config.multi_level); |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 1893 | integrate_psp_firmwares(&ctx, pspdir, pspdir2, pspdir2_b, |
Zheng Bao | fdd47ef | 2021-09-17 13:30:08 +0800 | [diff] [blame] | 1894 | amd_psp_fw_table, PSP_COOKIE, soc_id, &cb_config); |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 1895 | } else { |
| 1896 | /* flat: PSP 1 cookie and no pointer to 2nd table */ |
Zheng Bao | 481661e | 2021-08-20 14:47:46 +0800 | [diff] [blame] | 1897 | pspdir = new_psp_dir(&ctx, cb_config.multi_level); |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 1898 | integrate_psp_firmwares(&ctx, pspdir, NULL, NULL, |
Zheng Bao | fdd47ef | 2021-09-17 13:30:08 +0800 | [diff] [blame] | 1899 | amd_psp_fw_table, PSP_COOKIE, soc_id, &cb_config); |
Marshall Dawson | 24f73d4 | 2019-04-01 10:48:43 -0600 | [diff] [blame] | 1900 | } |
Marshall Dawson | 2794a86 | 2019-03-04 16:53:15 -0700 | [diff] [blame] | 1901 | |
Marshall Dawson | 0e02ce8 | 2019-03-04 16:50:37 -0700 | [diff] [blame] | 1902 | if (comboable) |
Zheng Bao | b749d3f | 2021-10-23 20:20:21 +0800 | [diff] [blame] | 1903 | amd_romsig->new_psp_directory = BUFF_TO_RUN(ctx, pspdir); |
Marshall Dawson | 67d868d | 2019-02-28 11:43:40 -0700 | [diff] [blame] | 1904 | else |
Felix Held | ad68b07 | 2021-10-18 14:00:35 +0200 | [diff] [blame] | 1905 | amd_romsig->psp_directory = BUFF_TO_RUN(ctx, pspdir); |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1906 | |
Zheng Bao | 993b43f | 2021-11-10 12:21:46 +0800 | [diff] [blame] | 1907 | if (cb_config.use_combo) { |
| 1908 | psp_combo_directory *combo_dir = new_combo_dir(&ctx); |
| 1909 | amd_romsig->combo_psp_directory = BUFF_TO_RUN(ctx, combo_dir); |
| 1910 | /* 0 -Compare PSP ID, 1 -Compare chip family ID */ |
| 1911 | combo_dir->entries[0].id_sel = 0; |
| 1912 | combo_dir->entries[0].id = get_psp_id(soc_id); |
| 1913 | combo_dir->entries[0].lvl2_addr = BUFF_TO_RUN(ctx, pspdir); |
Zheng Bao | 4fcc9f2 | 2015-11-20 12:29:04 +0800 | [diff] [blame] | 1914 | |
Zheng Bao | 993b43f | 2021-11-10 12:21:46 +0800 | [diff] [blame] | 1915 | combo_dir->header.lookup = 1; |
| 1916 | fill_dir_header(combo_dir, 1, PSP2_COOKIE, &ctx); |
| 1917 | } |
Zheng Bao | 4fcc9f2 | 2015-11-20 12:29:04 +0800 | [diff] [blame] | 1918 | |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1919 | if (have_bios_tables(amd_bios_table)) { |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 1920 | bios_directory_table *biosdir = NULL; |
Zheng Bao | 481661e | 2021-08-20 14:47:46 +0800 | [diff] [blame] | 1921 | if (cb_config.multi_level) { |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1922 | /* Do 2nd level BIOS directory followed by 1st */ |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 1923 | bios_directory_table *biosdir2 = NULL; |
| 1924 | bios_directory_table *biosdir2_b = NULL; |
| 1925 | |
| 1926 | biosdir2 = new_bios_dir(&ctx, cb_config.multi_level); |
| 1927 | |
Zheng Bao | edd1e36 | 2021-11-04 17:47:07 +0800 | [diff] [blame] | 1928 | integrate_bios_firmwares(&ctx, biosdir2, NULL, |
Zheng Bao | 96a3371 | 2021-06-11 15:54:40 +0800 | [diff] [blame] | 1929 | amd_bios_table, BHDL2_COOKIE, &cb_config); |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 1930 | if (cb_config.recovery_ab) { |
| 1931 | if (pspdir2_b != NULL) { |
| 1932 | biosdir2_b = new_bios_dir(&ctx, cb_config.multi_level); |
| 1933 | integrate_bios_firmwares(&ctx, biosdir2_b, NULL, |
Zheng Bao | 96a3371 | 2021-06-11 15:54:40 +0800 | [diff] [blame] | 1934 | amd_bios_table, BHDL2_COOKIE, &cb_config); |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 1935 | } |
| 1936 | add_psp_firmware_entry(&ctx, pspdir2, biosdir2, |
| 1937 | AMD_FW_BIOS_TABLE, TABLE_ALIGNMENT); |
| 1938 | if (pspdir2_b != NULL) |
| 1939 | add_psp_firmware_entry(&ctx, pspdir2_b, biosdir2_b, |
| 1940 | AMD_FW_BIOS_TABLE, TABLE_ALIGNMENT); |
| 1941 | } else { |
| 1942 | biosdir = new_bios_dir(&ctx, cb_config.multi_level); |
| 1943 | integrate_bios_firmwares(&ctx, biosdir, biosdir2, |
Zheng Bao | 96a3371 | 2021-06-11 15:54:40 +0800 | [diff] [blame] | 1944 | amd_bios_table, BHD_COOKIE, &cb_config); |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 1945 | } |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1946 | } else { |
Zheng Bao | 96a3371 | 2021-06-11 15:54:40 +0800 | [diff] [blame] | 1947 | /* flat: BHD1 cookie and no pointer to 2nd table */ |
Zheng Bao | 481661e | 2021-08-20 14:47:46 +0800 | [diff] [blame] | 1948 | biosdir = new_bios_dir(&ctx, cb_config.multi_level); |
Zheng Bao | edd1e36 | 2021-11-04 17:47:07 +0800 | [diff] [blame] | 1949 | integrate_bios_firmwares(&ctx, biosdir, NULL, |
Zheng Bao | 96a3371 | 2021-06-11 15:54:40 +0800 | [diff] [blame] | 1950 | amd_bios_table, BHD_COOKIE, &cb_config); |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1951 | } |
Zheng Bao | bf29a0d | 2020-12-03 23:00:48 +0800 | [diff] [blame] | 1952 | switch (soc_id) { |
| 1953 | case PLATFORM_RENOIR: |
| 1954 | case PLATFORM_LUCIENNE: |
| 1955 | case PLATFORM_CEZANNE: |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 1956 | if (!cb_config.recovery_ab) |
| 1957 | amd_romsig->bios3_entry = BUFF_TO_RUN(ctx, biosdir); |
Zheng Bao | bf29a0d | 2020-12-03 23:00:48 +0800 | [diff] [blame] | 1958 | break; |
Zheng Bao | 535ec53 | 2021-08-12 16:30:19 +0800 | [diff] [blame] | 1959 | case PLATFORM_MENDOCINO: |
Felix Held | b18a4c7 | 2022-03-29 02:34:11 +0200 | [diff] [blame] | 1960 | case PLATFORM_SABRINA: |
Zheng Bao | 535ec53 | 2021-08-12 16:30:19 +0800 | [diff] [blame] | 1961 | break; |
Zheng Bao | bf29a0d | 2020-12-03 23:00:48 +0800 | [diff] [blame] | 1962 | case PLATFORM_STONEYRIDGE: |
| 1963 | case PLATFORM_RAVEN: |
| 1964 | case PLATFORM_PICASSO: |
| 1965 | default: |
| 1966 | amd_romsig->bios1_entry = BUFF_TO_RUN(ctx, biosdir); |
| 1967 | break; |
| 1968 | } |
Marshall Dawson | ce2b2ba | 2019-03-19 14:45:31 -0600 | [diff] [blame] | 1969 | } |
| 1970 | |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 1971 | /* Free the filename. */ |
| 1972 | free_psp_firmware_filenames(amd_psp_fw_table); |
| 1973 | free_bdt_firmware_filenames(amd_bios_table); |
| 1974 | |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1975 | targetfd = open(output, O_RDWR | O_CREAT | O_TRUNC, 0666); |
Martin Roth | 31d95a2 | 2016-11-08 11:22:12 -0700 | [diff] [blame] | 1976 | if (targetfd >= 0) { |
Zheng Bao | 4739691 | 2020-09-29 17:33:17 +0800 | [diff] [blame] | 1977 | ssize_t bytes; |
| 1978 | bytes = write(targetfd, amd_romsig, ctx.current - romsig_offset); |
| 1979 | if (bytes != ctx.current - romsig_offset) { |
| 1980 | fprintf(stderr, "Error: Writing to file %s failed\n", output); |
| 1981 | retval = 1; |
| 1982 | } |
Martin Roth | 31d95a2 | 2016-11-08 11:22:12 -0700 | [diff] [blame] | 1983 | close(targetfd); |
| 1984 | } else { |
Zheng Bao | 77a2c67 | 2020-10-01 17:05:43 +0800 | [diff] [blame] | 1985 | fprintf(stderr, "Error: could not open file: %s\n", output); |
Martin Roth | 31d95a2 | 2016-11-08 11:22:12 -0700 | [diff] [blame] | 1986 | retval = 1; |
| 1987 | } |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1988 | |
Martin Roth | 31d95a2 | 2016-11-08 11:22:12 -0700 | [diff] [blame] | 1989 | free(rom); |
| 1990 | return retval; |
Zheng Bao | 9c7ff7b | 2015-11-17 22:57:39 +0800 | [diff] [blame] | 1991 | } |