Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2013 Google Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | #include <stddef.h> |
| 17 | #include <arch/cpu.h> |
| 18 | #include <arch/io.h> |
Kyösti Mälkki | c641f7e | 2018-12-28 16:54:54 +0200 | [diff] [blame] | 19 | #include <bootblock_common.h> |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 20 | #include <console/console.h> |
| 21 | #include <cbmem.h> |
| 22 | #include <cpu/x86/mtrr.h> |
Martin Roth | e6ff159 | 2017-06-24 21:34:29 -0600 | [diff] [blame] | 23 | #if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) |
Aaron Durbin | 3e0eea1 | 2013-10-28 11:20:35 -0500 | [diff] [blame] | 24 | #include <ec/google/chromeec/ec.h> |
| 25 | #endif |
Aaron Durbin | a8e9b63 | 2013-10-30 15:46:07 -0500 | [diff] [blame] | 26 | #include <elog.h> |
Kyösti Mälkki | 65e8f64 | 2016-06-27 11:27:56 +0300 | [diff] [blame] | 27 | #include <program_loading.h> |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 28 | #include <romstage_handoff.h> |
Aaron Durbin | bd74a4b | 2015-03-06 23:17:33 -0600 | [diff] [blame] | 29 | #include <stage_cache.h> |
Aaron Durbin | afe8aee | 2016-11-29 21:37:42 -0600 | [diff] [blame] | 30 | #include <string.h> |
Aaron Durbin | 794bddf | 2013-09-27 11:38:36 -0500 | [diff] [blame] | 31 | #include <timestamp.h> |
Aaron Durbin | ebf7ec5 | 2013-11-14 13:47:08 -0600 | [diff] [blame] | 32 | #include <vendorcode/google/chromeos/chromeos.h> |
Julius Werner | 18ea2d3 | 2014-10-07 16:42:17 -0700 | [diff] [blame] | 33 | #include <soc/gpio.h> |
| 34 | #include <soc/iomap.h> |
| 35 | #include <soc/lpc.h> |
| 36 | #include <soc/pci_devs.h> |
| 37 | #include <soc/pmc.h> |
Julius Werner | 18ea2d3 | 2014-10-07 16:42:17 -0700 | [diff] [blame] | 38 | #include <soc/romstage.h> |
| 39 | #include <soc/smm.h> |
| 40 | #include <soc/spi.h> |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 41 | |
| 42 | /* The cache-as-ram assembly file calls romstage_main() after setting up |
| 43 | * cache-as-ram. romstage_main() will then call the mainboards's |
| 44 | * mainboard_romstage_entry() function. That function then calls |
| 45 | * romstage_common() below. The reason for the back and forth is to provide |
| 46 | * common entry point from cache-as-ram while still allowing for code sharing. |
| 47 | * Because we can't use global variables the stack is used for allocations -- |
| 48 | * thus the need to call back and forth. */ |
| 49 | |
Arthur Heymans | d5d20d0 | 2018-11-29 14:16:49 +0100 | [diff] [blame] | 50 | static void platform_enter_postcar(void); |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 51 | |
| 52 | static void program_base_addresses(void) |
| 53 | { |
| 54 | uint32_t reg; |
| 55 | const uint32_t lpc_dev = PCI_DEV(0, LPC_DEV, LPC_FUNC); |
| 56 | |
| 57 | /* Memory Mapped IO registers. */ |
| 58 | reg = PMC_BASE_ADDRESS | 2; |
| 59 | pci_write_config32(lpc_dev, PBASE, reg); |
| 60 | reg = IO_BASE_ADDRESS | 2; |
| 61 | pci_write_config32(lpc_dev, IOBASE, reg); |
| 62 | reg = ILB_BASE_ADDRESS | 2; |
| 63 | pci_write_config32(lpc_dev, IBASE, reg); |
| 64 | reg = SPI_BASE_ADDRESS | 2; |
| 65 | pci_write_config32(lpc_dev, SBASE, reg); |
| 66 | reg = MPHY_BASE_ADDRESS | 2; |
| 67 | pci_write_config32(lpc_dev, MPBASE, reg); |
Aaron Durbin | a64ef62 | 2013-10-03 12:56:37 -0500 | [diff] [blame] | 68 | reg = PUNIT_BASE_ADDRESS | 2; |
| 69 | pci_write_config32(lpc_dev, PUBASE, reg); |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 70 | reg = RCBA_BASE_ADDRESS | 1; |
| 71 | pci_write_config32(lpc_dev, RCBA, reg); |
| 72 | |
| 73 | /* IO Port Registers. */ |
| 74 | reg = ACPI_BASE_ADDRESS | 2; |
| 75 | pci_write_config32(lpc_dev, ABASE, reg); |
| 76 | reg = GPIO_BASE_ADDRESS | 2; |
| 77 | pci_write_config32(lpc_dev, GBASE, reg); |
| 78 | } |
| 79 | |
Aaron Durbin | 6f9947a | 2013-11-18 11:16:20 -0600 | [diff] [blame] | 80 | static void spi_init(void) |
| 81 | { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 82 | u32 *scs = (u32 *)(SPI_BASE_ADDRESS + SCS); |
| 83 | u32 *bcr = (u32 *)(SPI_BASE_ADDRESS + BCR); |
Aaron Durbin | 4177db5 | 2014-02-05 14:55:26 -0600 | [diff] [blame] | 84 | uint32_t reg; |
| 85 | |
| 86 | /* Disable generating SMI when setting WPD bit. */ |
| 87 | write32(scs, read32(scs) & ~SMIWPEN); |
| 88 | /* |
| 89 | * Enable caching and prefetching in the SPI controller. Disable |
| 90 | * the SMM-only BIOS write and set WPD bit. |
| 91 | */ |
| 92 | reg = (read32(bcr) & ~SRC_MASK) | SRC_CACHE_PREFETCH | BCR_WPD; |
| 93 | reg &= ~EISS; |
| 94 | write32(bcr, reg); |
Aaron Durbin | 6f9947a | 2013-11-18 11:16:20 -0600 | [diff] [blame] | 95 | } |
| 96 | |
Aaron Durbin | 794bddf | 2013-09-27 11:38:36 -0500 | [diff] [blame] | 97 | /* Entry from cache-as-ram.inc. */ |
Kyösti Mälkki | c641f7e | 2018-12-28 16:54:54 +0200 | [diff] [blame] | 98 | static void romstage_main(uint64_t tsc, uint32_t bist) |
Aaron Durbin | 794bddf | 2013-09-27 11:38:36 -0500 | [diff] [blame] | 99 | { |
| 100 | struct romstage_params rp = { |
| 101 | .bist = bist, |
| 102 | .mrc_params = NULL, |
| 103 | }; |
| 104 | |
| 105 | /* Save initial timestamp from bootblock. */ |
Kyösti Mälkki | c641f7e | 2018-12-28 16:54:54 +0200 | [diff] [blame] | 106 | timestamp_init(tsc); |
Kyösti Mälkki | 4175927 | 2014-12-31 21:11:51 +0200 | [diff] [blame] | 107 | |
Aaron Durbin | 794bddf | 2013-09-27 11:38:36 -0500 | [diff] [blame] | 108 | /* Save romstage begin */ |
Kyösti Mälkki | 4175927 | 2014-12-31 21:11:51 +0200 | [diff] [blame] | 109 | timestamp_add_now(TS_START_ROMSTAGE); |
Aaron Durbin | 794bddf | 2013-09-27 11:38:36 -0500 | [diff] [blame] | 110 | |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 111 | program_base_addresses(); |
| 112 | |
Aaron Durbin | fd039f7 | 2013-10-04 11:11:52 -0500 | [diff] [blame] | 113 | tco_disable(); |
| 114 | |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 115 | byt_config_com1_and_enable(); |
| 116 | |
| 117 | console_init(); |
| 118 | |
Aaron Durbin | 6f9947a | 2013-11-18 11:16:20 -0600 | [diff] [blame] | 119 | spi_init(); |
| 120 | |
Aaron Durbin | bb3ee83 | 2013-10-07 17:12:20 -0500 | [diff] [blame] | 121 | set_max_freq(); |
| 122 | |
Aaron Durbin | 189aa3e | 2013-10-04 11:17:45 -0500 | [diff] [blame] | 123 | punit_init(); |
| 124 | |
Aaron Durbin | ecf9086 | 2013-09-24 12:36:14 -0500 | [diff] [blame] | 125 | gfx_init(); |
| 126 | |
Aaron Durbin | 5f8ad56 | 2013-10-08 16:54:18 -0500 | [diff] [blame] | 127 | /* Call into mainboard. */ |
| 128 | mainboard_romstage_entry(&rp); |
| 129 | |
Arthur Heymans | d5d20d0 | 2018-11-29 14:16:49 +0100 | [diff] [blame] | 130 | platform_enter_postcar(); |
| 131 | |
| 132 | /* We don't return here */ |
Kyösti Mälkki | c641f7e | 2018-12-28 16:54:54 +0200 | [diff] [blame] | 133 | } |
| 134 | |
| 135 | /* This wrapper enables easy transition towards C_ENVIRONMENT_BOOTBLOCK, |
| 136 | * keeping changes in cache_as_ram.S easy to manage. |
| 137 | */ |
| 138 | asmlinkage void bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist) |
| 139 | { |
| 140 | romstage_main(base_timestamp, bist); |
Aaron Durbin | 5f8ad56 | 2013-10-08 16:54:18 -0500 | [diff] [blame] | 141 | } |
| 142 | |
Arthur Heymans | e228678 | 2018-12-29 14:01:12 +0100 | [diff] [blame] | 143 | static struct chipset_power_state power_state; |
Aaron Durbin | 00bf3db | 2014-01-09 10:33:23 -0600 | [diff] [blame] | 144 | |
Aaron Durbin | 41607a4 | 2015-06-09 13:54:10 -0500 | [diff] [blame] | 145 | static void migrate_power_state(int is_recovery) |
Aaron Durbin | 6e32893 | 2013-11-06 12:04:50 -0600 | [diff] [blame] | 146 | { |
Aaron Durbin | 00bf3db | 2014-01-09 10:33:23 -0600 | [diff] [blame] | 147 | struct chipset_power_state *ps_cbmem; |
| 148 | struct chipset_power_state *ps_car; |
| 149 | |
Arthur Heymans | e228678 | 2018-12-29 14:01:12 +0100 | [diff] [blame] | 150 | ps_car = &power_state; |
Aaron Durbin | 00bf3db | 2014-01-09 10:33:23 -0600 | [diff] [blame] | 151 | ps_cbmem = cbmem_add(CBMEM_ID_POWER_STATE, sizeof(*ps_cbmem)); |
| 152 | |
| 153 | if (ps_cbmem == NULL) { |
| 154 | printk(BIOS_DEBUG, "Not adding power state to cbmem!\n"); |
| 155 | return; |
| 156 | } |
| 157 | memcpy(ps_cbmem, ps_car, sizeof(*ps_cbmem)); |
| 158 | } |
Kyösti Mälkki | 4fbac46 | 2015-01-07 04:48:43 +0200 | [diff] [blame] | 159 | ROMSTAGE_CBMEM_INIT_HOOK(migrate_power_state) |
Aaron Durbin | 00bf3db | 2014-01-09 10:33:23 -0600 | [diff] [blame] | 160 | |
| 161 | static struct chipset_power_state *fill_power_state(void) |
| 162 | { |
Arthur Heymans | e228678 | 2018-12-29 14:01:12 +0100 | [diff] [blame] | 163 | struct chipset_power_state *ps = &power_state; |
Aaron Durbin | 00bf3db | 2014-01-09 10:33:23 -0600 | [diff] [blame] | 164 | |
| 165 | ps->pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS); |
| 166 | ps->pm1_en = inw(ACPI_BASE_ADDRESS + PM1_EN); |
| 167 | ps->pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT); |
| 168 | ps->gpe0_sts = inl(ACPI_BASE_ADDRESS + GPE0_STS); |
| 169 | ps->gpe0_en = inl(ACPI_BASE_ADDRESS + GPE0_EN); |
| 170 | ps->tco_sts = inl(ACPI_BASE_ADDRESS + TCO_STS); |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 171 | ps->prsts = read32((u32 *)(PMC_BASE_ADDRESS + PRSTS)); |
| 172 | ps->gen_pmcon1 = read32((u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1)); |
| 173 | ps->gen_pmcon2 = read32((u32 *)(PMC_BASE_ADDRESS + GEN_PMCON2)); |
Aaron Durbin | 00bf3db | 2014-01-09 10:33:23 -0600 | [diff] [blame] | 174 | |
| 175 | printk(BIOS_DEBUG, "pm1_sts: %04x pm1_en: %04x pm1_cnt: %08x\n", |
| 176 | ps->pm1_sts, ps->pm1_en, ps->pm1_cnt); |
| 177 | printk(BIOS_DEBUG, "gpe0_sts: %08x gpe0_en: %08x tco_sts: %08x\n", |
| 178 | ps->gpe0_sts, ps->gpe0_en, ps->tco_sts); |
| 179 | printk(BIOS_DEBUG, "prsts: %08x gen_pmcon1: %08x gen_pmcon2: %08x\n", |
| 180 | ps->prsts, ps->gen_pmcon1, ps->gen_pmcon2); |
| 181 | |
| 182 | return ps; |
| 183 | } |
| 184 | |
| 185 | /* Return 0, 3, or 5 to indicate the previous sleep state. */ |
| 186 | static int chipset_prev_sleep_state(struct chipset_power_state *ps) |
| 187 | { |
Aaron Durbin | 6e32893 | 2013-11-06 12:04:50 -0600 | [diff] [blame] | 188 | /* Default to S0. */ |
Aaron Durbin | f5cfaa3 | 2016-07-13 23:20:07 -0500 | [diff] [blame] | 189 | int prev_sleep_state = ACPI_S0; |
Aaron Durbin | 6e32893 | 2013-11-06 12:04:50 -0600 | [diff] [blame] | 190 | |
Aaron Durbin | 00bf3db | 2014-01-09 10:33:23 -0600 | [diff] [blame] | 191 | if (ps->pm1_sts & WAK_STS) { |
Aaron Durbin | f5cfaa3 | 2016-07-13 23:20:07 -0500 | [diff] [blame] | 192 | switch (acpi_sleep_from_pm1(ps->pm1_cnt)) { |
| 193 | case ACPI_S3: |
| 194 | if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)) |
| 195 | prev_sleep_state = ACPI_S3; |
Aaron Durbin | 6e32893 | 2013-11-06 12:04:50 -0600 | [diff] [blame] | 196 | break; |
Aaron Durbin | f5cfaa3 | 2016-07-13 23:20:07 -0500 | [diff] [blame] | 197 | case ACPI_S5: |
| 198 | prev_sleep_state = ACPI_S5; |
Aaron Durbin | 00bf3db | 2014-01-09 10:33:23 -0600 | [diff] [blame] | 199 | break; |
Aaron Durbin | 6e32893 | 2013-11-06 12:04:50 -0600 | [diff] [blame] | 200 | } |
| 201 | /* Clear SLP_TYP. */ |
Aaron Durbin | 00bf3db | 2014-01-09 10:33:23 -0600 | [diff] [blame] | 202 | outl(ps->pm1_cnt & ~(SLP_TYP), ACPI_BASE_ADDRESS + PM1_CNT); |
Aaron Durbin | 6e32893 | 2013-11-06 12:04:50 -0600 | [diff] [blame] | 203 | } |
| 204 | |
Aaron Durbin | 00bf3db | 2014-01-09 10:33:23 -0600 | [diff] [blame] | 205 | if (ps->gen_pmcon1 & (PWR_FLR | SUS_PWR_FLR)) { |
Aaron Durbin | f5cfaa3 | 2016-07-13 23:20:07 -0500 | [diff] [blame] | 206 | prev_sleep_state = ACPI_S5; |
Aaron Durbin | 6e32893 | 2013-11-06 12:04:50 -0600 | [diff] [blame] | 207 | } |
| 208 | |
Aaron Durbin | 6e32893 | 2013-11-06 12:04:50 -0600 | [diff] [blame] | 209 | return prev_sleep_state; |
| 210 | } |
| 211 | |
Aaron Durbin | 5f8ad56 | 2013-10-08 16:54:18 -0500 | [diff] [blame] | 212 | /* Entry from the mainboard. */ |
| 213 | void romstage_common(struct romstage_params *params) |
| 214 | { |
Aaron Durbin | 00bf3db | 2014-01-09 10:33:23 -0600 | [diff] [blame] | 215 | struct chipset_power_state *ps; |
Aaron Durbin | 6e32893 | 2013-11-06 12:04:50 -0600 | [diff] [blame] | 216 | int prev_sleep_state; |
Aaron Durbin | 5f8ad56 | 2013-10-08 16:54:18 -0500 | [diff] [blame] | 217 | |
Kyösti Mälkki | 4175927 | 2014-12-31 21:11:51 +0200 | [diff] [blame] | 218 | timestamp_add_now(TS_BEFORE_INITRAM); |
Aaron Durbin | 794bddf | 2013-09-27 11:38:36 -0500 | [diff] [blame] | 219 | |
Aaron Durbin | 00bf3db | 2014-01-09 10:33:23 -0600 | [diff] [blame] | 220 | ps = fill_power_state(); |
| 221 | prev_sleep_state = chipset_prev_sleep_state(ps); |
Aaron Durbin | 6e32893 | 2013-11-06 12:04:50 -0600 | [diff] [blame] | 222 | |
| 223 | printk(BIOS_DEBUG, "prev_sleep_state = S%d\n", prev_sleep_state); |
| 224 | |
Martin Roth | e6ff159 | 2017-06-24 21:34:29 -0600 | [diff] [blame] | 225 | #if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT) |
Aaron Durbin | f5cfaa3 | 2016-07-13 23:20:07 -0500 | [diff] [blame] | 226 | if (prev_sleep_state != ACPI_S3) |
Aaron Durbin | 4177db5 | 2014-02-05 14:55:26 -0600 | [diff] [blame] | 227 | boot_count_increment(); |
| 228 | #endif |
| 229 | |
| 230 | |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 231 | /* Initialize RAM */ |
Aaron Durbin | 6e32893 | 2013-11-06 12:04:50 -0600 | [diff] [blame] | 232 | raminit(params->mrc_params, prev_sleep_state); |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 233 | |
Kyösti Mälkki | 4175927 | 2014-12-31 21:11:51 +0200 | [diff] [blame] | 234 | timestamp_add_now(TS_AFTER_INITRAM); |
Aaron Durbin | 794bddf | 2013-09-27 11:38:36 -0500 | [diff] [blame] | 235 | |
Aaron Durbin | 77e1399 | 2016-11-29 17:43:04 -0600 | [diff] [blame] | 236 | romstage_handoff_init(prev_sleep_state == ACPI_S3); |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 237 | } |
| 238 | |
Arthur Heymans | f6cfbf3 | 2018-11-29 14:08:15 +0100 | [diff] [blame] | 239 | #define ROMSTAGE_RAM_STACK_SIZE 0x5000 |
| 240 | |
Elyes HAOUAS | bc8762e | 2018-04-25 15:50:27 +0200 | [diff] [blame] | 241 | /* setup_stack_and_mtrrs() determines the stack to use after |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 242 | * cache-as-ram is torn down as well as the MTRR settings to use. */ |
Arthur Heymans | d5d20d0 | 2018-11-29 14:16:49 +0100 | [diff] [blame] | 243 | static void platform_enter_postcar(void) |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 244 | { |
Arthur Heymans | f6cfbf3 | 2018-11-29 14:08:15 +0100 | [diff] [blame] | 245 | struct postcar_frame pcf; |
| 246 | uintptr_t top_of_ram; |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 247 | |
Arthur Heymans | f6cfbf3 | 2018-11-29 14:08:15 +0100 | [diff] [blame] | 248 | if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE)) |
| 249 | die("Unable to initialize postcar frame.\n"); |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 250 | /* Cache the ROM as WP just below 4GiB. */ |
Nico Huber | 4c7eee2 | 2019-02-10 19:35:41 +0100 | [diff] [blame] | 251 | postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 252 | |
Kyösti Mälkki | 65cc526 | 2016-06-19 20:38:41 +0300 | [diff] [blame] | 253 | /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ |
Arthur Heymans | f6cfbf3 | 2018-11-29 14:08:15 +0100 | [diff] [blame] | 254 | postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 255 | |
Arthur Heymans | f6cfbf3 | 2018-11-29 14:08:15 +0100 | [diff] [blame] | 256 | /* Cache at least 8 MiB below the top of ram, and at most 8 MiB |
| 257 | * above top of the ram. This satisfies MTRR alignment requirement |
| 258 | * with different TSEG size configurations. |
| 259 | */ |
| 260 | top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB); |
| 261 | postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 16*MiB, |
| 262 | MTRR_TYPE_WRBACK); |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 263 | |
Arthur Heymans | d5d20d0 | 2018-11-29 14:16:49 +0100 | [diff] [blame] | 264 | run_postcar_phase(&pcf); |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 265 | } |