Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2013 Google Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
| 20 | #include <stddef.h> |
| 21 | #include <arch/cpu.h> |
| 22 | #include <arch/io.h> |
| 23 | #include <arch/cbfs.h> |
| 24 | #include <arch/stages.h> |
| 25 | #include <console/console.h> |
| 26 | #include <cbmem.h> |
| 27 | #include <cpu/x86/mtrr.h> |
Aaron Durbin | 3e0eea1 | 2013-10-28 11:20:35 -0500 | [diff] [blame] | 28 | #if CONFIG_EC_GOOGLE_CHROMEEC |
| 29 | #include <ec/google/chromeec/ec.h> |
| 30 | #endif |
Aaron Durbin | a8e9b63 | 2013-10-30 15:46:07 -0500 | [diff] [blame] | 31 | #include <elog.h> |
Aaron Durbin | dc249f6 | 2013-10-10 21:03:50 -0500 | [diff] [blame] | 32 | #include <ramstage_cache.h> |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 33 | #include <romstage_handoff.h> |
Aaron Durbin | 794bddf | 2013-09-27 11:38:36 -0500 | [diff] [blame] | 34 | #include <timestamp.h> |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 35 | #include <baytrail/gpio.h> |
| 36 | #include <baytrail/iomap.h> |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 37 | #include <baytrail/lpc.h> |
| 38 | #include <baytrail/pci_devs.h> |
Aaron Durbin | 6e32893 | 2013-11-06 12:04:50 -0600 | [diff] [blame^] | 39 | #include <baytrail/pmc.h> |
Aaron Durbin | dc249f6 | 2013-10-10 21:03:50 -0500 | [diff] [blame] | 40 | #include <baytrail/reset.h> |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 41 | #include <baytrail/romstage.h> |
Aaron Durbin | 7837be6 | 2013-10-21 22:32:00 -0500 | [diff] [blame] | 42 | #include <baytrail/smm.h> |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 43 | |
Aaron Durbin | 794bddf | 2013-09-27 11:38:36 -0500 | [diff] [blame] | 44 | static inline uint64_t timestamp_get(void) |
| 45 | { |
| 46 | return rdtscll(); |
| 47 | } |
| 48 | |
| 49 | static inline tsc_t ts64_to_tsc(uint64_t ts) |
| 50 | { |
| 51 | tsc_t tsc = { |
| 52 | .lo = ts, |
| 53 | .hi = ts >> 32, |
| 54 | }; |
| 55 | return tsc; |
| 56 | } |
| 57 | |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 58 | /* The cache-as-ram assembly file calls romstage_main() after setting up |
| 59 | * cache-as-ram. romstage_main() will then call the mainboards's |
| 60 | * mainboard_romstage_entry() function. That function then calls |
| 61 | * romstage_common() below. The reason for the back and forth is to provide |
| 62 | * common entry point from cache-as-ram while still allowing for code sharing. |
| 63 | * Because we can't use global variables the stack is used for allocations -- |
| 64 | * thus the need to call back and forth. */ |
| 65 | |
| 66 | static void *setup_stack_and_mttrs(void); |
| 67 | |
| 68 | static void program_base_addresses(void) |
| 69 | { |
| 70 | uint32_t reg; |
| 71 | const uint32_t lpc_dev = PCI_DEV(0, LPC_DEV, LPC_FUNC); |
| 72 | |
| 73 | /* Memory Mapped IO registers. */ |
| 74 | reg = PMC_BASE_ADDRESS | 2; |
| 75 | pci_write_config32(lpc_dev, PBASE, reg); |
| 76 | reg = IO_BASE_ADDRESS | 2; |
| 77 | pci_write_config32(lpc_dev, IOBASE, reg); |
| 78 | reg = ILB_BASE_ADDRESS | 2; |
| 79 | pci_write_config32(lpc_dev, IBASE, reg); |
| 80 | reg = SPI_BASE_ADDRESS | 2; |
| 81 | pci_write_config32(lpc_dev, SBASE, reg); |
| 82 | reg = MPHY_BASE_ADDRESS | 2; |
| 83 | pci_write_config32(lpc_dev, MPBASE, reg); |
Aaron Durbin | a64ef62 | 2013-10-03 12:56:37 -0500 | [diff] [blame] | 84 | reg = PUNIT_BASE_ADDRESS | 2; |
| 85 | pci_write_config32(lpc_dev, PUBASE, reg); |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 86 | reg = RCBA_BASE_ADDRESS | 1; |
| 87 | pci_write_config32(lpc_dev, RCBA, reg); |
| 88 | |
| 89 | /* IO Port Registers. */ |
| 90 | reg = ACPI_BASE_ADDRESS | 2; |
| 91 | pci_write_config32(lpc_dev, ABASE, reg); |
| 92 | reg = GPIO_BASE_ADDRESS | 2; |
| 93 | pci_write_config32(lpc_dev, GBASE, reg); |
| 94 | } |
| 95 | |
Aaron Durbin | 794bddf | 2013-09-27 11:38:36 -0500 | [diff] [blame] | 96 | static inline void mark_ts(struct romstage_params *rp, uint64_t ts) |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 97 | { |
Aaron Durbin | 794bddf | 2013-09-27 11:38:36 -0500 | [diff] [blame] | 98 | struct romstage_timestamps *rt = &rp->ts; |
| 99 | |
| 100 | rt->times[rt->count] = ts; |
| 101 | rt->count++; |
| 102 | } |
| 103 | |
| 104 | /* Entry from cache-as-ram.inc. */ |
| 105 | void * asmlinkage romstage_main(unsigned long bist, |
| 106 | uint32_t tsc_low, uint32_t tsc_hi) |
| 107 | { |
| 108 | struct romstage_params rp = { |
| 109 | .bist = bist, |
| 110 | .mrc_params = NULL, |
| 111 | }; |
| 112 | |
| 113 | /* Save initial timestamp from bootblock. */ |
| 114 | mark_ts(&rp, (((uint64_t)tsc_hi) << 32) | (uint64_t)tsc_low); |
| 115 | /* Save romstage begin */ |
| 116 | mark_ts(&rp, timestamp_get()); |
| 117 | |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 118 | program_base_addresses(); |
| 119 | |
Aaron Durbin | fd039f7 | 2013-10-04 11:11:52 -0500 | [diff] [blame] | 120 | tco_disable(); |
| 121 | |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 122 | byt_config_com1_and_enable(); |
| 123 | |
| 124 | console_init(); |
| 125 | |
Aaron Durbin | bb3ee83 | 2013-10-07 17:12:20 -0500 | [diff] [blame] | 126 | set_max_freq(); |
| 127 | |
Aaron Durbin | 189aa3e | 2013-10-04 11:17:45 -0500 | [diff] [blame] | 128 | punit_init(); |
| 129 | |
Aaron Durbin | ecf9086 | 2013-09-24 12:36:14 -0500 | [diff] [blame] | 130 | gfx_init(); |
| 131 | |
Aaron Durbin | 3e0eea1 | 2013-10-28 11:20:35 -0500 | [diff] [blame] | 132 | #if CONFIG_EC_GOOGLE_CHROMEEC |
| 133 | /* Ensure the EC is in the right mode for recovery */ |
| 134 | google_chromeec_early_init(); |
| 135 | #endif |
| 136 | |
Aaron Durbin | 5f8ad56 | 2013-10-08 16:54:18 -0500 | [diff] [blame] | 137 | /* Call into mainboard. */ |
| 138 | mainboard_romstage_entry(&rp); |
| 139 | |
| 140 | return setup_stack_and_mttrs(); |
| 141 | } |
| 142 | |
Aaron Durbin | 6e32893 | 2013-11-06 12:04:50 -0600 | [diff] [blame^] | 143 | /* Return 0, 3, or 5 to indicate the previous sleep state. */ |
| 144 | static int chipset_prev_sleep_state(void) |
| 145 | { |
| 146 | uint16_t pm1_sts; |
| 147 | uint32_t pm1_cnt; |
| 148 | uint32_t gen_pmcon1; |
| 149 | /* Default to S0. */ |
| 150 | int prev_sleep_state = 0; |
| 151 | |
| 152 | pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS); |
| 153 | pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT); |
| 154 | |
| 155 | if (pm1_sts & WAK_STS) { |
| 156 | switch ((pm1_cnt & SLP_TYP) >> SLP_TYP_SHIFT) { |
| 157 | #if CONFIG_HAVE_ACPI_RESUME |
| 158 | case SLP_TYP_S3: |
| 159 | prev_sleep_state = 3; |
| 160 | break; |
| 161 | #endif |
| 162 | case SLP_TYP_S5: |
| 163 | prev_sleep_state = 5; |
| 164 | } |
| 165 | /* Clear SLP_TYP. */ |
| 166 | outl(pm1_cnt & ~(SLP_TYP), ACPI_BASE_ADDRESS + PM1_CNT); |
| 167 | } |
| 168 | |
| 169 | gen_pmcon1 = read32(PMC_BASE_ADDRESS + GEN_PMCON1); |
| 170 | if (gen_pmcon1 & (PWR_FLR | SUS_PWR_FLR)) { |
| 171 | /* Clear power failure bits. */ |
| 172 | write32(PMC_BASE_ADDRESS + GEN_PMCON1, gen_pmcon1); |
| 173 | prev_sleep_state = 5; |
| 174 | } |
| 175 | |
| 176 | printk(BIOS_DEBUG, "pm1_sts = %04x pm1_cnt = %08x gen_pmcon1 = %08x\n", |
| 177 | pm1_sts, pm1_cnt, gen_pmcon1); |
| 178 | |
| 179 | return prev_sleep_state; |
| 180 | } |
| 181 | |
Aaron Durbin | 5f8ad56 | 2013-10-08 16:54:18 -0500 | [diff] [blame] | 182 | /* Entry from the mainboard. */ |
| 183 | void romstage_common(struct romstage_params *params) |
| 184 | { |
| 185 | struct romstage_handoff *handoff; |
Aaron Durbin | 6e32893 | 2013-11-06 12:04:50 -0600 | [diff] [blame^] | 186 | int prev_sleep_state; |
Aaron Durbin | 5f8ad56 | 2013-10-08 16:54:18 -0500 | [diff] [blame] | 187 | |
Aaron Durbin | 794bddf | 2013-09-27 11:38:36 -0500 | [diff] [blame] | 188 | mark_ts(params, timestamp_get()); |
| 189 | |
Aaron Durbin | a8e9b63 | 2013-10-30 15:46:07 -0500 | [diff] [blame] | 190 | #if CONFIG_ELOG_BOOT_COUNT |
| 191 | boot_count_increment(); |
| 192 | #endif |
| 193 | |
Aaron Durbin | 6e32893 | 2013-11-06 12:04:50 -0600 | [diff] [blame^] | 194 | prev_sleep_state = chipset_prev_sleep_state(); |
| 195 | |
| 196 | printk(BIOS_DEBUG, "prev_sleep_state = S%d\n", prev_sleep_state); |
| 197 | |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 198 | /* Initialize RAM */ |
Aaron Durbin | 6e32893 | 2013-11-06 12:04:50 -0600 | [diff] [blame^] | 199 | raminit(params->mrc_params, prev_sleep_state); |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 200 | |
Aaron Durbin | 794bddf | 2013-09-27 11:38:36 -0500 | [diff] [blame] | 201 | mark_ts(params, timestamp_get()); |
| 202 | |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 203 | handoff = romstage_handoff_find_or_add(); |
| 204 | if (handoff != NULL) |
Aaron Durbin | 6e32893 | 2013-11-06 12:04:50 -0600 | [diff] [blame^] | 205 | handoff->s3_resume = (prev_sleep_state == 3); |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 206 | else |
| 207 | printk(BIOS_DEBUG, "Romstage handoff structure not added!\n"); |
| 208 | |
Aaron Durbin | 794bddf | 2013-09-27 11:38:36 -0500 | [diff] [blame] | 209 | /* Save timestamp information. */ |
| 210 | timestamp_init(ts64_to_tsc(params->ts.times[0])); |
| 211 | timestamp_add(TS_START_ROMSTAGE, ts64_to_tsc(params->ts.times[1])); |
| 212 | timestamp_add(TS_BEFORE_INITRAM, ts64_to_tsc(params->ts.times[2])); |
| 213 | timestamp_add(TS_AFTER_INITRAM, ts64_to_tsc(params->ts.times[3])); |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 214 | } |
| 215 | |
| 216 | static void open_up_spi(void) |
| 217 | { |
| 218 | const uintptr_t sbase = SPI_BASE_ADDRESS; |
| 219 | |
| 220 | /* Disable generating SMI when setting WPD bit. */ |
| 221 | write32(sbase + 0xf8, read32(sbase + 0xf8) & ~(1 << 7)); |
| 222 | /* Disable the SMM-only BIOS write and set WPD bit. */ |
| 223 | write32(sbase + 0xfc, 1 | (read32(sbase + 0xfc) & ~(1 << 5))); |
| 224 | } |
| 225 | |
| 226 | void asmlinkage romstage_after_car(void) |
| 227 | { |
| 228 | /* Allow BIOS to program SPI part. */ |
| 229 | open_up_spi(); |
| 230 | |
Aaron Durbin | 794bddf | 2013-09-27 11:38:36 -0500 | [diff] [blame] | 231 | timestamp_add_now(TS_END_ROMSTAGE); |
| 232 | |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 233 | /* Load the ramstage. */ |
| 234 | copy_and_run(); |
| 235 | while (1); |
| 236 | } |
| 237 | |
| 238 | static inline uint32_t *stack_push(u32 *stack, u32 value) |
| 239 | { |
| 240 | stack = &stack[-1]; |
| 241 | *stack = value; |
| 242 | return stack; |
| 243 | } |
| 244 | |
| 245 | /* Romstage needs quite a bit of stack for decompressing images since the lzma |
| 246 | * lib keeps its state on the stack during romstage. */ |
| 247 | static unsigned long choose_top_of_stack(void) |
| 248 | { |
| 249 | unsigned long stack_top; |
| 250 | const unsigned long romstage_ram_stack_size = 0x5000; |
| 251 | |
| 252 | /* cbmem_add() does a find() before add(). */ |
| 253 | stack_top = (unsigned long)cbmem_add(CBMEM_ID_ROMSTAGE_RAM_STACK, |
| 254 | romstage_ram_stack_size); |
| 255 | stack_top += romstage_ram_stack_size; |
| 256 | return stack_top; |
| 257 | } |
| 258 | |
| 259 | /* setup_stack_and_mttrs() determines the stack to use after |
| 260 | * cache-as-ram is torn down as well as the MTRR settings to use. */ |
| 261 | static void *setup_stack_and_mttrs(void) |
| 262 | { |
| 263 | unsigned long top_of_stack; |
| 264 | int num_mtrrs; |
| 265 | uint32_t *slot; |
| 266 | uint32_t mtrr_mask_upper; |
| 267 | uint32_t top_of_ram; |
| 268 | |
| 269 | /* Top of stack needs to be aligned to a 4-byte boundary. */ |
| 270 | top_of_stack = choose_top_of_stack() & ~3; |
| 271 | slot = (void *)top_of_stack; |
| 272 | num_mtrrs = 0; |
| 273 | |
| 274 | /* The upper bits of the MTRR mask need to set according to the number |
| 275 | * of physical address bits. */ |
| 276 | mtrr_mask_upper = (1 << ((cpuid_eax(0x80000008) & 0xff) - 32)) - 1; |
| 277 | |
| 278 | /* The order for each MTRR is value then base with upper 32-bits of |
| 279 | * each value coming before the lower 32-bits. The reasoning for |
| 280 | * this ordering is to create a stack layout like the following: |
| 281 | * +0: Number of MTRRs |
| 282 | * +4: MTRR base 0 31:0 |
| 283 | * +8: MTRR base 0 63:32 |
| 284 | * +12: MTRR mask 0 31:0 |
| 285 | * +16: MTRR mask 0 63:32 |
| 286 | * +20: MTRR base 1 31:0 |
| 287 | * +24: MTRR base 1 63:32 |
| 288 | * +28: MTRR mask 1 31:0 |
| 289 | * +32: MTRR mask 1 63:32 |
| 290 | */ |
| 291 | |
| 292 | /* Cache the ROM as WP just below 4GiB. */ |
| 293 | slot = stack_push(slot, mtrr_mask_upper); /* upper mask */ |
| 294 | slot = stack_push(slot, ~(CONFIG_ROM_SIZE - 1) | MTRRphysMaskValid); |
| 295 | slot = stack_push(slot, 0); /* upper base */ |
| 296 | slot = stack_push(slot, ~(CONFIG_ROM_SIZE - 1) | MTRR_TYPE_WRPROT); |
| 297 | num_mtrrs++; |
| 298 | |
| 299 | /* Cache RAM as WB from 0 -> CONFIG_RAMTOP. */ |
| 300 | slot = stack_push(slot, mtrr_mask_upper); /* upper mask */ |
| 301 | slot = stack_push(slot, ~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid); |
| 302 | slot = stack_push(slot, 0); /* upper base */ |
| 303 | slot = stack_push(slot, 0 | MTRR_TYPE_WRBACK); |
| 304 | num_mtrrs++; |
| 305 | |
| 306 | top_of_ram = (uint32_t)cbmem_top(); |
| 307 | /* Cache 8MiB below the top of ram. The top of ram under 4GiB is the |
| 308 | * start of the TSEG region. It is required to be 8MiB aligned. Set |
| 309 | * this area as cacheable so it can be used later for ramstage before |
| 310 | * setting up the entire RAM as cacheable. */ |
| 311 | slot = stack_push(slot, mtrr_mask_upper); /* upper mask */ |
| 312 | slot = stack_push(slot, ~((8 << 20) - 1) | MTRRphysMaskValid); |
| 313 | slot = stack_push(slot, 0); /* upper base */ |
| 314 | slot = stack_push(slot, (top_of_ram - (8 << 20)) | MTRR_TYPE_WRBACK); |
| 315 | num_mtrrs++; |
| 316 | |
| 317 | /* Cache 8MiB at the top of ram. Top of ram is where the TSEG |
| 318 | * region resides. However, it is not restricted to SMM mode until |
| 319 | * SMM has been relocated. By setting the region to cacheable it |
| 320 | * provides faster access when relocating the SMM handler as well |
| 321 | * as using the TSEG region for other purposes. */ |
| 322 | slot = stack_push(slot, mtrr_mask_upper); /* upper mask */ |
| 323 | slot = stack_push(slot, ~((8 << 20) - 1) | MTRRphysMaskValid); |
| 324 | slot = stack_push(slot, 0); /* upper base */ |
| 325 | slot = stack_push(slot, top_of_ram | MTRR_TYPE_WRBACK); |
| 326 | num_mtrrs++; |
| 327 | |
| 328 | /* Save the number of MTRRs to setup. Return the stack location |
| 329 | * pointing to the number of MTRRs. */ |
| 330 | slot = stack_push(slot, num_mtrrs); |
| 331 | |
| 332 | return slot; |
| 333 | } |
Aaron Durbin | dc249f6 | 2013-10-10 21:03:50 -0500 | [diff] [blame] | 334 | |
| 335 | struct ramstage_cache *ramstage_cache_location(long *size) |
| 336 | { |
| 337 | char *smm_base; |
| 338 | /* 1MiB cache size */ |
Aaron Durbin | 7837be6 | 2013-10-21 22:32:00 -0500 | [diff] [blame] | 339 | const long cache_size = CONFIG_SMM_RESERVED_SIZE; |
Aaron Durbin | dc249f6 | 2013-10-10 21:03:50 -0500 | [diff] [blame] | 340 | |
| 341 | /* Ramstage cache lives in TSEG region which is the definition of |
| 342 | * cbmem_top(). */ |
| 343 | smm_base = cbmem_top(); |
| 344 | *size = cache_size; |
Aaron Durbin | 7837be6 | 2013-10-21 22:32:00 -0500 | [diff] [blame] | 345 | return (void *)&smm_base[smm_region_size() - cache_size]; |
Aaron Durbin | dc249f6 | 2013-10-10 21:03:50 -0500 | [diff] [blame] | 346 | } |
| 347 | |
| 348 | void ramstage_cache_invalid(struct ramstage_cache *cache) |
| 349 | { |
| 350 | #if CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE |
| 351 | /* Perform cold reset on invalid ramstage cache. */ |
| 352 | cold_reset(); |
| 353 | #endif |
| 354 | } |
| 355 | |