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Andrey Petrov662da6c2020-03-16 22:46:57 -07001## SPDX-License-Identifier: GPL-2.0-only
Andrey Petrov662da6c2020-03-16 22:46:57 -07002
Elyes Haouas171ad512023-08-04 07:42:33 +02003config SOC_INTEL_SKYLAKE_SP
4 bool
5 select XEON_SP_COMMON_BASE
6 select PLATFORM_USES_FSP2_0
7 select NO_FSP_TEMP_RAM_EXIT
8 help
9 Intel Skylake-SP support
10
Andrey Petrov662da6c2020-03-16 22:46:57 -070011if SOC_INTEL_SKYLAKE_SP
12
13config MAINBOARD_USES_FSP2_0
14 bool
15 default y
16
Andrey Petrov662da6c2020-03-16 22:46:57 -070017config FSP_HEADER_PATH
18 string "Location of FSP headers"
19 depends on MAINBOARD_USES_FSP2_0
20 default "src/vendorcode/intel/fsp/fsp2_0/skylake_sp"
21
22config MAX_SOCKET
23 int
24 default 2
25
Andrey Petrov662da6c2020-03-16 22:46:57 -070026# For 2S config, the number of cpus could be as high as
27# 2 threads * 20 cores * 2 sockets
28config MAX_CPUS
29 int
30 default 80
31
32config PCR_BASE_ADDRESS
33 hex
34 default 0xfd000000
35 help
36 This option allows you to select MMIO Base Address of sideband bus.
37
38config DCACHE_RAM_BASE
39 hex
40 default 0xfe800000
41
42config DCACHE_RAM_SIZE
43 hex
44 default 0x200000
45
46config DCACHE_BSP_STACK_SIZE
47 hex
48 default 0x10000
49
50config CPU_MICROCODE_CBFS_LOC
51 hex
52 default 0xfff0fdc0
53
54config CPU_MICROCODE_CBFS_LEN
55 hex
56 default 0x7C00
57
Rocky Phagura17a798b2020-10-08 13:32:41 -070058config IED_REGION_SIZE
59 hex
60 default 0x400000
61
Johnny Linc05aa262021-06-22 11:35:41 +080062config IFD_CHIPSET
63 string
64 default "lbg"
65
Christian Walter106def92022-06-29 18:23:51 +020066config XEON_SP_HAVE_IIO_IOAPIC
67 bool
68 default y
69
Andrey Petrov662da6c2020-03-16 22:46:57 -070070endif