| Andrey Petrov | 662da6c | 2020-03-16 22:46:57 -0700 | [diff] [blame^] | 1 | ## |
| 2 | ## SPDX-License-Identifier: GPL-2.0-only |
| 3 | ## This file is part of the coreboot project. |
| 4 | ## |
| 5 | |
| 6 | if SOC_INTEL_SKYLAKE_SP |
| 7 | |
| 8 | config MAINBOARD_USES_FSP2_0 |
| 9 | bool |
| 10 | default y |
| 11 | |
| 12 | config USE_FSP2_0_DRIVER |
| 13 | def_bool y |
| 14 | depends on MAINBOARD_USES_FSP2_0 |
| 15 | select PLATFORM_USES_FSP2_0 |
| 16 | select UDK_2015_BINDING |
| 17 | select POSTCAR_CONSOLE |
| 18 | select POSTCAR_STAGE |
| 19 | |
| 20 | config FSP_HEADER_PATH |
| 21 | string "Location of FSP headers" |
| 22 | depends on MAINBOARD_USES_FSP2_0 |
| 23 | default "src/vendorcode/intel/fsp/fsp2_0/skylake_sp" |
| 24 | |
| 25 | config MAX_SOCKET |
| 26 | int |
| 27 | default 2 |
| 28 | |
| 29 | # For 2S config, the number of cpus could be as high as |
| 30 | # 2 threads * 20 cores * 2 sockets |
| 31 | config MAX_CPUS |
| 32 | int |
| 33 | default 80 |
| 34 | |
| 35 | config PCR_BASE_ADDRESS |
| 36 | hex |
| 37 | default 0xfd000000 |
| 38 | help |
| 39 | This option allows you to select MMIO Base Address of sideband bus. |
| 40 | |
| 41 | config DCACHE_RAM_BASE |
| 42 | hex |
| 43 | default 0xfe800000 |
| 44 | |
| 45 | config DCACHE_RAM_SIZE |
| 46 | hex |
| 47 | default 0x200000 |
| 48 | |
| 49 | config DCACHE_BSP_STACK_SIZE |
| 50 | hex |
| 51 | default 0x10000 |
| 52 | |
| 53 | config CPU_MICROCODE_CBFS_LOC |
| 54 | hex |
| 55 | default 0xfff0fdc0 |
| 56 | |
| 57 | config CPU_MICROCODE_CBFS_LEN |
| 58 | hex |
| 59 | default 0x7C00 |
| 60 | |
| 61 | config C_ENV_BOOTBLOCK_SIZE |
| 62 | hex |
| 63 | default 0xC000 |
| 64 | |
| 65 | config HEAP_SIZE |
| 66 | hex |
| 67 | default 0x80000 |
| 68 | |
| 69 | endif |