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review.coreboot.org / coreboot / 43b7f416783ccc98952a4eb5f9274907442b03e5 / . / src / southbridge / amd / pi / hudson / sd.c
blob: 6dad3349916b4b1947162e8d6e03e7c74d4caaf1 [file] [log] [blame]
Angel Pons182dbde2020-04-02 23:49:05 +0200[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0-only */
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300[diff] [blame]2
3#include <device/device.h>
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300[diff] [blame]4#include <device/pci.h>
5#include <device/pci_ids.h>
6#include <device/pci_ops.h>
Elyes HAOUASbf0970e2019-03-21 11:10:03 +0100[diff] [blame]7
Kyösti Mälkki830e0de2019-08-19 13:29:46 +0300[diff] [blame]8#include "chip.h"
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300[diff] [blame]9#include "hudson.h"
10
11static void sd_init(struct device *dev)
12{
Kyösti Mälkki830e0de2019-08-19 13:29:46 +0300[diff] [blame]13 struct southbridge_amd_pi_hudson_config *sd_chip = dev->chip_info;
14 u32 stepping = pci_read_config32(pcidev_on_root(0x18, 3), 0xFC);
15 u8 sd_mode = 0;
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300[diff] [blame]16
Kyösti Mälkki830e0de2019-08-19 13:29:46 +0300[diff] [blame]17 if (sd_chip)
18 sd_mode = sd_chip->sd_mode;
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300[diff] [blame]19
Kyösti Mälkki830e0de2019-08-19 13:29:46 +0300[diff] [blame]20 if (sd_mode == 3) { /* SD 3.0 mode */
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300[diff] [blame]21 pci_write_config32(dev, 0xA4, 0x31FEC8B2);
22 pci_write_config32(dev, 0xA8, 0x00002503);
23 pci_write_config32(dev, 0xB0, 0x02180C19);
24 pci_write_config32(dev, 0xD0, 0x0000078B);
25 }
26 else { /* SD 2.0 mode */
27 if ((stepping & 0x0000000F) == 0) { /* Stepping A0 */
28 pci_write_config32(dev, 0xA4, 0x31DE32B2);
29 pci_write_config32(dev, 0xB0, 0x01180C19);
30 pci_write_config32(dev, 0xD0, 0x0000058B);
31 }
32 else { /* Stepping >= A1 */
Michał Żygowski654a45d2018-07-05 16:53:44 +0200[diff] [blame]33 pci_write_config32(dev, 0xA4, 0x31FE32B2);
34 pci_write_config32(dev, 0xA8, 0x00000070);
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300[diff] [blame]35 pci_write_config32(dev, 0xB0, 0x01180C19);
36 pci_write_config32(dev, 0xD0, 0x0000078B);
37 }
38 }
39}
40
41static struct device_operations sd_ops = {
42 .read_resources = pci_dev_read_resources,
43 .set_resources = pci_dev_set_resources,
44 .enable_resources = pci_dev_enable_resources,
45 .init = sd_init,
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300[diff] [blame]46};
47
48static const struct pci_driver sd_driver __pci_driver = {
49 .ops = &sd_ops,
Felix Singer43b7f412022-03-07 04:34:52 +0100[diff] [blame^]50 .vendor = PCI_VID_AMD,
51 .device = PCI_DID_AMD_YANGTZE_SD,
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300[diff] [blame]52};