src/sb/amd/pi/hudson/sd.c: disable SDR50 tuning and set correct clock freq in SD2.0 mode
According to BKDG for AMD Family 16h Models 30h-3Fh Processors
SDR50 tuning should be disabled in 0xA8 register.
Also fix clock frequency setting in 0xA4 for stepping >= A1
which caused reduced performance of SD cards transfer speed
even by half.
Change-Id: I80ca754b0c89e08aa90ff885467c7486a3efb999
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Signed-off-by: Piotr Król <piotr.krol@3mdeb.com>
Reviewed-on: https://review.coreboot.org/27359
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
diff --git a/src/southbridge/amd/pi/hudson/sd.c b/src/southbridge/amd/pi/hudson/sd.c
index a76ff92..a87367f 100644
--- a/src/southbridge/amd/pi/hudson/sd.c
+++ b/src/southbridge/amd/pi/hudson/sd.c
@@ -43,7 +43,8 @@
pci_write_config32(dev, 0xD0, 0x0000058B);
}
else { /* Stepping >= A1 */
- pci_write_config32(dev, 0xA4, 0x31FE3FB2);
+ pci_write_config32(dev, 0xA4, 0x31FE32B2);
+ pci_write_config32(dev, 0xA8, 0x00000070);
pci_write_config32(dev, 0xB0, 0x01180C19);
pci_write_config32(dev, 0xD0, 0x0000078B);
}