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review.coreboot.org / coreboot / 43b7f416783ccc98952a4eb5f9274907442b03e5 / . / src / soc / intel / tigerlake / systemagent.c
blob: 06282eaaba645b3e7109ac1d8ad856f7703c0b55 [file] [log] [blame]
Angel Pons16f6aa82020-04-05 15:47:21 +0200[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0-only */
Subrata Banik91e89c52019-11-01 18:30:01 +0530[diff] [blame]2
3/*
4 * This file is created based on Intel Tiger Lake Processor SA Datasheet
5 * Document number: 571131
6 * Chapter number: 3
7 */
8
Tim Wawrzynczak2dcca0f2020-06-16 10:50:47 -0600[diff] [blame]9#include <console/console.h>
Subrata Banik91e89c52019-11-01 18:30:01 +0530[diff] [blame]10#include <device/device.h>
Sumeet R Pawnikard2132462020-05-15 15:55:37 +0530[diff] [blame]11#include <delay.h>
Subrata Banik91e89c52019-11-01 18:30:01 +0530[diff] [blame]12#include <device/pci.h>
Tim Wawrzynczak2dcca0f2020-06-16 10:50:47 -0600[diff] [blame]13#include <device/pci_ids.h>
John Zhao49111cd2020-01-03 11:01:23 -0800[diff] [blame]14#include <device/pci_ops.h>
Sumeet R Pawnikard2132462020-05-15 15:55:37 +0530[diff] [blame]15#include <intelblocks/power_limit.h>
Subrata Banik91e89c52019-11-01 18:30:01 +0530[diff] [blame]16#include <intelblocks/systemagent.h>
17#include <soc/iomap.h>
Sumeet R Pawnikard2132462020-05-15 15:55:37 +0530[diff] [blame]18#include <soc/soc_chip.h>
Subrata Banik91e89c52019-11-01 18:30:01 +0530[diff] [blame]19#include <soc/systemagent.h>
20
21/*
22 * SoC implementation
23 *
24 * Add all known fixed memory ranges for Host Controller/Memory
25 * controller.
26 */
27void soc_add_fixed_mmio_resources(struct device *dev, int *index)
28{
29 static const struct sa_mmio_descriptor soc_fixed_resources[] = {
Shelley Chen4e9bb332021-10-20 15:43:45 -0700[diff] [blame]30 { PCIEXBAR, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH,
Subrata Banik91e89c52019-11-01 18:30:01 +0530[diff] [blame]31 "PCIEXBAR" },
32 { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" },
33 { DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" },
34 { EPBAR, EP_BASE_ADDRESS, EP_BASE_SIZE, "EPBAR" },
35 { REGBAR, REG_BASE_ADDRESS, REG_BASE_SIZE, "REGBAR" },
36 { EDRAMBAR, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE, "EDRAMBAR" },
Subrata Banik91e89c52019-11-01 18:30:01 +0530[diff] [blame]37 };
38
39 sa_add_fixed_mmio_resources(dev, index, soc_fixed_resources,
40 ARRAY_SIZE(soc_fixed_resources));
John Zhao49111cd2020-01-03 11:01:23 -0800[diff] [blame]41
42 /* Add Vt-d resources if VT-d is enabled */
43 if ((pci_read_config32(dev, CAPID0_A) & VTD_DISABLE))
44 return;
45
46 sa_add_fixed_mmio_resources(dev, index, soc_vtd_resources,
47 ARRAY_SIZE(soc_vtd_resources));
Subrata Banik91e89c52019-11-01 18:30:01 +0530[diff] [blame]48}
49
50/*
51 * SoC implementation
52 *
53 * Perform System Agent Initialization during Ramstage phase.
54 */
55void soc_systemagent_init(struct device *dev)
56{
Sumeet R Pawnikard2132462020-05-15 15:55:37 +0530[diff] [blame]57 struct soc_power_limits_config *soc_config;
Tim Wawrzynczak2dcca0f2020-06-16 10:50:47 -0600[diff] [blame]58 struct device *sa;
59 uint16_t sa_pci_id;
Sumeet R Pawnikard2132462020-05-15 15:55:37 +0530[diff] [blame]60 config_t *config;
61
Tim Wawrzynczak2dcca0f2020-06-16 10:50:47 -0600[diff] [blame]62 /* Get System Agent PCI ID */
63 sa = pcidev_path_on_root(SA_DEVFN_ROOT);
64 sa_pci_id = sa ? pci_read_config16(sa, PCI_DEVICE_ID) : 0xFFFF;
65
Subrata Banik91e89c52019-11-01 18:30:01 +0530[diff] [blame]66 /* Enable Power Aware Interrupt Routing */
67 enable_power_aware_intr();
68
69 /* Enable BIOS Reset CPL */
70 enable_bios_reset_cpl();
Sumeet R Pawnikard2132462020-05-15 15:55:37 +0530[diff] [blame]71
72 /* Configure turbo power limits 1ms after reset complete bit */
73 mdelay(1);
74 config = config_of_soc();
Tim Wawrzynczak2dcca0f2020-06-16 10:50:47 -0600[diff] [blame]75
76 /*
77 * Choose a power limits configuration based on the SoC SKU,
78 * differentiated here based on SA PCI ID.
79 */
80 switch (sa_pci_id) {
Felix Singer43b7f412022-03-07 04:34:52 +0100[diff] [blame^]81 case PCI_DID_INTEL_TGL_ID_U_2_2:
Tim Wawrzynczak2dcca0f2020-06-16 10:50:47 -0600[diff] [blame]82 soc_config = &config->power_limits_config[POWER_LIMITS_U_2_CORE];
83 break;
Felix Singer43b7f412022-03-07 04:34:52 +0100[diff] [blame^]84 case PCI_DID_INTEL_TGL_ID_U_4_2:
Derek Huang60f178d2020-07-03 15:33:13 +0800[diff] [blame]85 soc_config = &config->power_limits_config[POWER_LIMITS_U_4_CORE];
86 break;
Felix Singer43b7f412022-03-07 04:34:52 +0100[diff] [blame^]87 case PCI_DID_INTEL_TGL_ID_Y_2_2:
Sumeet R Pawnikar1a621502020-07-20 15:44:59 +0530[diff] [blame]88 soc_config = &config->power_limits_config[POWER_LIMITS_Y_2_CORE];
89 break;
Felix Singer43b7f412022-03-07 04:34:52 +0100[diff] [blame^]90 case PCI_DID_INTEL_TGL_ID_Y_4_2:
Sumeet R Pawnikar1a621502020-07-20 15:44:59 +0530[diff] [blame]91 soc_config = &config->power_limits_config[POWER_LIMITS_Y_4_CORE];
92 break;
Felix Singer43b7f412022-03-07 04:34:52 +0100[diff] [blame^]93 case PCI_DID_INTEL_TGL_ID_H_6_1:
Jeremy Soller301b09b2021-08-12 10:49:58 -0600[diff] [blame]94 soc_config = &config->power_limits_config[POWER_LIMITS_H_6_CORE];
95 break;
Felix Singer43b7f412022-03-07 04:34:52 +0100[diff] [blame^]96 case PCI_DID_INTEL_TGL_ID_H_8_1:
Jeremy Soller301b09b2021-08-12 10:49:58 -0600[diff] [blame]97 soc_config = &config->power_limits_config[POWER_LIMITS_H_8_CORE];
98 break;
Tim Wawrzynczak2dcca0f2020-06-16 10:50:47 -0600[diff] [blame]99 default:
100 printk(BIOS_ERR, "TGL: unknown SA ID: 0x%4x, skipping power limits "
101 "configuration\n", sa_pci_id);
102 return;
103 }
104
Sumeet R Pawnikard2132462020-05-15 15:55:37 +0530[diff] [blame]105 set_power_limits(MOBILE_SKU_PL1_TIME_SEC, soc_config);
Subrata Banik91e89c52019-11-01 18:30:01 +0530[diff] [blame]106}
Patrick Rudolphbf72dcb2020-05-12 16:04:47 +0200[diff] [blame]107
108uint32_t soc_systemagent_max_chan_capacity_mib(u8 capid0_a_ddrsz)
109{
110 switch (capid0_a_ddrsz) {
111 case 1:
112 return 8192;
113 case 2:
114 return 4096;
115 case 3:
116 return 2048;
117 default:
118 return 65536;
119 }
120}