Gitiles
Code Review Sign In
review.coreboot.org / coreboot / d2132469ae86d7287576a2ba3211cdbfeb572703 / . / src / soc / intel / tigerlake / systemagent.c
blob: 977c6674e7bbfa84bb8f05ceab0b8ee0a0a432ec [file] [log] [blame]
Angel Pons16f6aa82020-04-05 15:47:21 +0200[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0-only */
Subrata Banik91e89c52019-11-01 18:30:01 +0530[diff] [blame]2
3/*
4 * This file is created based on Intel Tiger Lake Processor SA Datasheet
5 * Document number: 571131
6 * Chapter number: 3
7 */
8
9#include <device/device.h>
Sumeet R Pawnikard2132462020-05-15 15:55:37 +0530[diff] [blame^]10#include <delay.h>
Subrata Banik91e89c52019-11-01 18:30:01 +0530[diff] [blame]11#include <device/pci.h>
John Zhao49111cd2020-01-03 11:01:23 -0800[diff] [blame]12#include <device/pci_ops.h>
Sumeet R Pawnikard2132462020-05-15 15:55:37 +0530[diff] [blame^]13#include <intelblocks/power_limit.h>
Subrata Banik91e89c52019-11-01 18:30:01 +0530[diff] [blame]14#include <intelblocks/systemagent.h>
15#include <soc/iomap.h>
Sumeet R Pawnikard2132462020-05-15 15:55:37 +0530[diff] [blame^]16#include <soc/soc_chip.h>
Subrata Banik91e89c52019-11-01 18:30:01 +0530[diff] [blame]17#include <soc/systemagent.h>
18
19/*
20 * SoC implementation
21 *
22 * Add all known fixed memory ranges for Host Controller/Memory
23 * controller.
24 */
25void soc_add_fixed_mmio_resources(struct device *dev, int *index)
26{
27 static const struct sa_mmio_descriptor soc_fixed_resources[] = {
28 { PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_SA_PCIEX_LENGTH,
29 "PCIEXBAR" },
30 { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" },
31 { DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" },
32 { EPBAR, EP_BASE_ADDRESS, EP_BASE_SIZE, "EPBAR" },
33 { REGBAR, REG_BASE_ADDRESS, REG_BASE_SIZE, "REGBAR" },
34 { EDRAMBAR, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE, "EDRAMBAR" },
35 /*
36 * PMC pci device gets hidden from PCI bus due to Silicon
37 * policy hence binding PMCBAR aka PWRMBASE (offset 0x10) with
38 * SA resources to ensure that PMCBAR falls under PCI reserved
39 * memory range.
40 *
41 * Note: Don't add any more resource with same offset 0x10
42 * under this device space.
43 */
44 { PCI_BASE_ADDRESS_0, PCH_PWRM_BASE_ADDRESS, PCH_PWRM_BASE_SIZE,
45 "PMCBAR" },
46 };
47
48 sa_add_fixed_mmio_resources(dev, index, soc_fixed_resources,
49 ARRAY_SIZE(soc_fixed_resources));
John Zhao49111cd2020-01-03 11:01:23 -0800[diff] [blame]50
51 /* Add Vt-d resources if VT-d is enabled */
52 if ((pci_read_config32(dev, CAPID0_A) & VTD_DISABLE))
53 return;
54
55 sa_add_fixed_mmio_resources(dev, index, soc_vtd_resources,
56 ARRAY_SIZE(soc_vtd_resources));
Subrata Banik91e89c52019-11-01 18:30:01 +0530[diff] [blame]57}
58
59/*
60 * SoC implementation
61 *
62 * Perform System Agent Initialization during Ramstage phase.
63 */
64void soc_systemagent_init(struct device *dev)
65{
Sumeet R Pawnikard2132462020-05-15 15:55:37 +0530[diff] [blame^]66 struct soc_power_limits_config *soc_config;
67 config_t *config;
68
Subrata Banik91e89c52019-11-01 18:30:01 +0530[diff] [blame]69 /* Enable Power Aware Interrupt Routing */
70 enable_power_aware_intr();
71
72 /* Enable BIOS Reset CPL */
73 enable_bios_reset_cpl();
Sumeet R Pawnikard2132462020-05-15 15:55:37 +0530[diff] [blame^]74
75 /* Configure turbo power limits 1ms after reset complete bit */
76 mdelay(1);
77 config = config_of_soc();
78 soc_config = &config->power_limits_config;
79 set_power_limits(MOBILE_SKU_PL1_TIME_SEC, soc_config);
Subrata Banik91e89c52019-11-01 18:30:01 +0530[diff] [blame]80}