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review.coreboot.org / coreboot / bf72dcbd2f1b0138a329f0c9adac33c387e8cd9f / . / src / soc / intel / tigerlake / systemagent.c
blob: 08d1ef387c393c9e7b27e531bc2b6e1f1a7949a4 [file] [log] [blame]
Angel Pons16f6aa82020-04-05 15:47:21 +0200[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0-only */
Subrata Banik91e89c52019-11-01 18:30:01 +0530[diff] [blame]2
3/*
4 * This file is created based on Intel Tiger Lake Processor SA Datasheet
5 * Document number: 571131
6 * Chapter number: 3
7 */
8
9#include <device/device.h>
Sumeet R Pawnikard2132462020-05-15 15:55:37 +0530[diff] [blame]10#include <delay.h>
Subrata Banik91e89c52019-11-01 18:30:01 +0530[diff] [blame]11#include <device/pci.h>
John Zhao49111cd2020-01-03 11:01:23 -0800[diff] [blame]12#include <device/pci_ops.h>
Sumeet R Pawnikard2132462020-05-15 15:55:37 +0530[diff] [blame]13#include <intelblocks/power_limit.h>
Subrata Banik91e89c52019-11-01 18:30:01 +0530[diff] [blame]14#include <intelblocks/systemagent.h>
15#include <soc/iomap.h>
Sumeet R Pawnikard2132462020-05-15 15:55:37 +0530[diff] [blame]16#include <soc/soc_chip.h>
Subrata Banik91e89c52019-11-01 18:30:01 +0530[diff] [blame]17#include <soc/systemagent.h>
18
19/*
20 * SoC implementation
21 *
22 * Add all known fixed memory ranges for Host Controller/Memory
23 * controller.
24 */
25void soc_add_fixed_mmio_resources(struct device *dev, int *index)
26{
27 static const struct sa_mmio_descriptor soc_fixed_resources[] = {
28 { PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_SA_PCIEX_LENGTH,
29 "PCIEXBAR" },
30 { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" },
31 { DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" },
32 { EPBAR, EP_BASE_ADDRESS, EP_BASE_SIZE, "EPBAR" },
33 { REGBAR, REG_BASE_ADDRESS, REG_BASE_SIZE, "REGBAR" },
34 { EDRAMBAR, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE, "EDRAMBAR" },
Subrata Banik91e89c52019-11-01 18:30:01 +0530[diff] [blame]35 };
36
37 sa_add_fixed_mmio_resources(dev, index, soc_fixed_resources,
38 ARRAY_SIZE(soc_fixed_resources));
John Zhao49111cd2020-01-03 11:01:23 -0800[diff] [blame]39
40 /* Add Vt-d resources if VT-d is enabled */
41 if ((pci_read_config32(dev, CAPID0_A) & VTD_DISABLE))
42 return;
43
44 sa_add_fixed_mmio_resources(dev, index, soc_vtd_resources,
45 ARRAY_SIZE(soc_vtd_resources));
Subrata Banik91e89c52019-11-01 18:30:01 +0530[diff] [blame]46}
47
48/*
49 * SoC implementation
50 *
51 * Perform System Agent Initialization during Ramstage phase.
52 */
53void soc_systemagent_init(struct device *dev)
54{
Sumeet R Pawnikard2132462020-05-15 15:55:37 +0530[diff] [blame]55 struct soc_power_limits_config *soc_config;
56 config_t *config;
57
Subrata Banik91e89c52019-11-01 18:30:01 +0530[diff] [blame]58 /* Enable Power Aware Interrupt Routing */
59 enable_power_aware_intr();
60
61 /* Enable BIOS Reset CPL */
62 enable_bios_reset_cpl();
Sumeet R Pawnikard2132462020-05-15 15:55:37 +0530[diff] [blame]63
64 /* Configure turbo power limits 1ms after reset complete bit */
65 mdelay(1);
66 config = config_of_soc();
67 soc_config = &config->power_limits_config;
68 set_power_limits(MOBILE_SKU_PL1_TIME_SEC, soc_config);
Subrata Banik91e89c52019-11-01 18:30:01 +0530[diff] [blame]69}
Patrick Rudolphbf72dcb2020-05-12 16:04:47 +0200[diff] [blame^]70
71uint32_t soc_systemagent_max_chan_capacity_mib(u8 capid0_a_ddrsz)
72{
73 switch (capid0_a_ddrsz) {
74 case 1:
75 return 8192;
76 case 2:
77 return 4096;
78 case 3:
79 return 2048;
80 default:
81 return 65536;
82 }
83}