blob: 6bebf0546750bf74c6a5c55fcdb96ec7275da874 [file] [log] [blame]
Angel Ponsc3f58f62020-04-05 15:46:41 +02001/* SPDX-License-Identifier: GPL-2.0-only */
Shawn Nematbakhsh51d787a2014-01-16 17:52:21 -08002#include <console/console.h>
3#include <device/device.h>
4#include <device/pci.h>
5#include <device/pci_def.h>
6#include <device/pci_ids.h>
7#include <reg_script.h>
8
Duncan Laurief0aaa292014-04-22 10:48:29 -07009#include <soc/intel/common/hda_verb.h>
Julius Werner18ea2d32014-10-07 16:42:17 -070010#include <soc/iomap.h>
11#include <soc/iosf.h>
12#include <soc/pci_devs.h>
13#include <soc/ramstage.h>
Shawn Nematbakhsh51d787a2014-01-16 17:52:21 -080014
15static const struct reg_script init_ops[] = {
Shawn Nematbakhsh51d787a2014-01-16 17:52:21 -080016 /* Enable no snoop traffic. */
17 REG_PCI_OR16(0x78, 1 << 11),
18 /* Configure HDMI codec connection. */
19 REG_PCI_OR32(0xc4, 1 << 1),
20 REG_PCI_OR8(0x43, (1 << 3) | (1 << 6)),
21 REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xc0),
22 REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0x00),
23 /* Configure internal settings. */
24 REG_PCI_OR32(0xc0, 0x7 << 21),
25 REG_PCI_OR32(0xc4, (0x3 << 26) | (1 << 13) | (1 << 10)),
26 REG_PCI_WRITE32(0xc8, 0x82a30000),
27 REG_PCI_RMW32(0xd0, ~(1 << 31), 0x0),
28 /* Disable docking. */
29 REG_PCI_RMW8(0x4d, ~(1 << 7), 0),
30 REG_SCRIPT_END,
31};
32
33static const uint32_t hdmi_codec_verb_table[] = {
34 /* coreboot specific header */
35 0x80862882, /* vid did for hdmi codec */
36 0x00000000, /* subsystem id */
37 0x00000003, /* number of jacks */
38
39 /* pin widget 5 - port B */
40 0x20471c10,
41 0x20471d00,
42 0x20471e56,
43 0x20471f18,
44
45 /* pin widget 6 - port C */
46 0x20571c20,
47 0x20571d00,
48 0x20571e56,
49 0x20571f18,
50
51 /* pin widget 7 - port D */
52 0x20671c30,
53 0x20671d00,
54 0x20671e56,
55 0x20671f58,
56};
57
Elyes HAOUAS17a3ceb2018-05-22 10:42:28 +020058static void hda_init(struct device *dev)
Shawn Nematbakhsh51d787a2014-01-16 17:52:21 -080059{
60 struct resource *res;
61 int codec_mask;
62 int i;
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -080063 u8 *base;
Shawn Nematbakhsh51d787a2014-01-16 17:52:21 -080064
65 reg_script_run_on_dev(dev, init_ops);
66
Angel Ponsc1bfbe02021-11-03 13:18:53 +010067 res = probe_resource(dev, PCI_BASE_ADDRESS_0);
Shawn Nematbakhsh51d787a2014-01-16 17:52:21 -080068 if (res == NULL)
69 return;
70
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -080071 base = res2mmio(res, 0, 0);
72 codec_mask = hda_codec_detect(base);
Shawn Nematbakhsh51d787a2014-01-16 17:52:21 -080073
74 printk(BIOS_DEBUG, "codec mask = %x\n", codec_mask);
75 if (!codec_mask)
76 return;
77
78 for (i = 3; i >= 0; i--) {
79 if (!((1 << i) & codec_mask))
80 continue;
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -080081 hda_codec_init(base, i, sizeof(hdmi_codec_verb_table),
Shawn Nematbakhsh51d787a2014-01-16 17:52:21 -080082 hdmi_codec_verb_table);
83 }
84}
85
86static const struct device_operations device_ops = {
87 .read_resources = pci_dev_read_resources,
88 .set_resources = pci_dev_set_resources,
89 .enable_resources = pci_dev_enable_resources,
90 .init = hda_init,
Shawn Nematbakhsh51d787a2014-01-16 17:52:21 -080091 .ops_pci = &soc_pci_ops,
92};
93
94static const struct pci_driver southcluster __pci_driver = {
95 .ops = &device_ops,
Felix Singer43b7f412022-03-07 04:34:52 +010096 .vendor = PCI_VID_INTEL,
Shawn Nematbakhsh51d787a2014-01-16 17:52:21 -080097 .device = HDA_DEVID,
98};