blob: df23f54974d8d6f04dc15625567bcb89c3f2e046 [file] [log] [blame]
Angel Ponsc3f58f62020-04-05 15:46:41 +02001/* SPDX-License-Identifier: GPL-2.0-only */
2/* This file is part of the coreboot project. */
Shawn Nematbakhsh51d787a2014-01-16 17:52:21 -08003#include <console/console.h>
4#include <device/device.h>
5#include <device/pci.h>
6#include <device/pci_def.h>
7#include <device/pci_ids.h>
8#include <reg_script.h>
9
Duncan Laurief0aaa292014-04-22 10:48:29 -070010#include <soc/intel/common/hda_verb.h>
Julius Werner18ea2d32014-10-07 16:42:17 -070011#include <soc/iomap.h>
12#include <soc/iosf.h>
13#include <soc/pci_devs.h>
14#include <soc/ramstage.h>
Shawn Nematbakhsh51d787a2014-01-16 17:52:21 -080015
16static const struct reg_script init_ops[] = {
Shawn Nematbakhsh51d787a2014-01-16 17:52:21 -080017 /* Enable no snoop traffic. */
18 REG_PCI_OR16(0x78, 1 << 11),
19 /* Configure HDMI codec connection. */
20 REG_PCI_OR32(0xc4, 1 << 1),
21 REG_PCI_OR8(0x43, (1 << 3) | (1 << 6)),
22 REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xc0),
23 REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0x00),
24 /* Configure internal settings. */
25 REG_PCI_OR32(0xc0, 0x7 << 21),
26 REG_PCI_OR32(0xc4, (0x3 << 26) | (1 << 13) | (1 << 10)),
27 REG_PCI_WRITE32(0xc8, 0x82a30000),
28 REG_PCI_RMW32(0xd0, ~(1 << 31), 0x0),
29 /* Disable docking. */
30 REG_PCI_RMW8(0x4d, ~(1 << 7), 0),
31 REG_SCRIPT_END,
32};
33
34static const uint32_t hdmi_codec_verb_table[] = {
35 /* coreboot specific header */
36 0x80862882, /* vid did for hdmi codec */
37 0x00000000, /* subsystem id */
38 0x00000003, /* number of jacks */
39
40 /* pin widget 5 - port B */
41 0x20471c10,
42 0x20471d00,
43 0x20471e56,
44 0x20471f18,
45
46 /* pin widget 6 - port C */
47 0x20571c20,
48 0x20571d00,
49 0x20571e56,
50 0x20571f18,
51
52 /* pin widget 7 - port D */
53 0x20671c30,
54 0x20671d00,
55 0x20671e56,
56 0x20671f58,
57};
58
Elyes HAOUAS17a3ceb2018-05-22 10:42:28 +020059static void hda_init(struct device *dev)
Shawn Nematbakhsh51d787a2014-01-16 17:52:21 -080060{
61 struct resource *res;
62 int codec_mask;
63 int i;
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -080064 u8 *base;
Shawn Nematbakhsh51d787a2014-01-16 17:52:21 -080065
66 reg_script_run_on_dev(dev, init_ops);
67
68 res = find_resource(dev, PCI_BASE_ADDRESS_0);
69 if (res == NULL)
70 return;
71
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -080072 base = res2mmio(res, 0, 0);
73 codec_mask = hda_codec_detect(base);
Shawn Nematbakhsh51d787a2014-01-16 17:52:21 -080074
75 printk(BIOS_DEBUG, "codec mask = %x\n", codec_mask);
76 if (!codec_mask)
77 return;
78
79 for (i = 3; i >= 0; i--) {
80 if (!((1 << i) & codec_mask))
81 continue;
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -080082 hda_codec_init(base, i, sizeof(hdmi_codec_verb_table),
Shawn Nematbakhsh51d787a2014-01-16 17:52:21 -080083 hdmi_codec_verb_table);
84 }
85}
86
87static const struct device_operations device_ops = {
88 .read_resources = pci_dev_read_resources,
89 .set_resources = pci_dev_set_resources,
90 .enable_resources = pci_dev_enable_resources,
91 .init = hda_init,
Shawn Nematbakhsh51d787a2014-01-16 17:52:21 -080092 .ops_pci = &soc_pci_ops,
93};
94
95static const struct pci_driver southcluster __pci_driver = {
96 .ops = &device_ops,
97 .vendor = PCI_VENDOR_ID_INTEL,
98 .device = HDA_DEVID,
99};