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review.coreboot.org / coreboot / f0aaa29989f4de7258430715d64c6d465fb0c457 / . / src / soc / intel / baytrail / hda.c
blob: c5de654921f19f16ac0a178e9f67634ff76bc897 [file] [log] [blame]
Shawn Nematbakhsh51d787a2014-01-16 17:52:21 -0800[diff] [blame]1/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2014 Google Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18 */
19#include <arch/io.h>
20#include <console/console.h>
21#include <device/device.h>
22#include <device/pci.h>
23#include <device/pci_def.h>
24#include <device/pci_ids.h>
25#include <reg_script.h>
26
Duncan Laurief0aaa292014-04-22 10:48:29 -0700[diff] [blame^]27#include <soc/intel/common/hda_verb.h>
Shawn Nematbakhsh51d787a2014-01-16 17:52:21 -0800[diff] [blame]28#include <baytrail/iomap.h>
29#include <baytrail/iosf.h>
30#include <baytrail/pci_devs.h>
31#include <baytrail/ramstage.h>
32
33static const struct reg_script init_ops[] = {
34 /* Set up VC0 and VC1. */
35 REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x24, 0x80000019),
36 REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x28, 0x81000022),
37 /* Enable VCi */
38 REG_PCI_WRITE32(0x120, 0x81000022),
39 /* Enable no snoop traffic. */
40 REG_PCI_OR16(0x78, 1 << 11),
41 /* Configure HDMI codec connection. */
42 REG_PCI_OR32(0xc4, 1 << 1),
43 REG_PCI_OR8(0x43, (1 << 3) | (1 << 6)),
44 REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xc0),
45 REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0x00),
46 /* Configure internal settings. */
47 REG_PCI_OR32(0xc0, 0x7 << 21),
48 REG_PCI_OR32(0xc4, (0x3 << 26) | (1 << 13) | (1 << 10)),
49 REG_PCI_WRITE32(0xc8, 0x82a30000),
50 REG_PCI_RMW32(0xd0, ~(1 << 31), 0x0),
51 /* Disable docking. */
52 REG_PCI_RMW8(0x4d, ~(1 << 7), 0),
53 REG_SCRIPT_END,
54};
55
56static const uint32_t hdmi_codec_verb_table[] = {
57 /* coreboot specific header */
58 0x80862882, /* vid did for hdmi codec */
59 0x00000000, /* subsystem id */
60 0x00000003, /* number of jacks */
61
62 /* pin widget 5 - port B */
63 0x20471c10,
64 0x20471d00,
65 0x20471e56,
66 0x20471f18,
67
68 /* pin widget 6 - port C */
69 0x20571c20,
70 0x20571d00,
71 0x20571e56,
72 0x20571f18,
73
74 /* pin widget 7 - port D */
75 0x20671c30,
76 0x20671d00,
77 0x20671e56,
78 0x20671f58,
79};
80
81static void hda_init(device_t dev)
82{
83 struct resource *res;
84 int codec_mask;
85 int i;
86
87 reg_script_run_on_dev(dev, init_ops);
88
89 res = find_resource(dev, PCI_BASE_ADDRESS_0);
90 if (res == NULL)
91 return;
92
93 codec_mask = hda_codec_detect(res->base);
94
95 printk(BIOS_DEBUG, "codec mask = %x\n", codec_mask);
96 if (!codec_mask)
97 return;
98
99 for (i = 3; i >= 0; i--) {
100 if (!((1 << i) & codec_mask))
101 continue;
102 hda_codec_init(res->base, i, sizeof(hdmi_codec_verb_table),
103 hdmi_codec_verb_table);
104 }
105}
106
107static const struct device_operations device_ops = {
108 .read_resources = pci_dev_read_resources,
109 .set_resources = pci_dev_set_resources,
110 .enable_resources = pci_dev_enable_resources,
111 .init = hda_init,
112 .enable = NULL,
113 .scan_bus = NULL,
114 .ops_pci = &soc_pci_ops,
115};
116
117static const struct pci_driver southcluster __pci_driver = {
118 .ops = &device_ops,
119 .vendor = PCI_VENDOR_ID_INTEL,
120 .device = HDA_DEVID,
121};