Patrick Georgi | ac95903 | 2020-05-05 22:49:26 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
Hannah Williams | 01bc897 | 2016-02-04 20:13:34 -0800 | [diff] [blame] | 2 | |
Alexandru Gagniuc | a633980 | 2016-04-05 12:40:24 -0700 | [diff] [blame] | 3 | #define __SIMPLE_DEVICE__ |
| 4 | |
Furquan Shaikh | 76cedd2 | 2020-05-02 10:24:23 -0700 | [diff] [blame] | 5 | #include <acpi/acpi.h> |
Kyösti Mälkki | 2787237 | 2021-01-21 16:05:26 +0200 | [diff] [blame] | 6 | #include <acpi/acpi_pm.h> |
Hannah Williams | 01bc897 | 2016-02-04 20:13:34 -0800 | [diff] [blame] | 7 | #include <arch/io.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 8 | #include <device/mmio.h> |
Hannah Williams | 01bc897 | 2016-02-04 20:13:34 -0800 | [diff] [blame] | 9 | #include <console/console.h> |
Andrey Petrov | 3b63753 | 2016-11-30 17:39:16 -0800 | [diff] [blame] | 10 | #include <cpu/x86/msr.h> |
Shaunak Saha | 93cdc8b | 2017-04-18 15:42:09 -0700 | [diff] [blame] | 11 | #include <device/device.h> |
| 12 | #include <device/pci.h> |
Hannah Williams | 01bc897 | 2016-02-04 20:13:34 -0800 | [diff] [blame] | 13 | #include <device/pci_def.h> |
Barnali Sarkar | 66fe0c4 | 2017-05-23 18:17:14 +0530 | [diff] [blame] | 14 | #include <intelblocks/msr.h> |
Shaunak Saha | 93cdc8b | 2017-04-18 15:42:09 -0700 | [diff] [blame] | 15 | #include <intelblocks/pmclib.h> |
Aaron Durbin | 3118b62 | 2017-09-15 11:48:53 -0600 | [diff] [blame] | 16 | #include <intelblocks/rtc.h> |
Subrata Banik | 7bc4dc5 | 2018-05-17 18:40:32 +0530 | [diff] [blame] | 17 | #include <intelblocks/tco.h> |
Hannah Williams | 01bc897 | 2016-02-04 20:13:34 -0800 | [diff] [blame] | 18 | #include <soc/iomap.h> |
Andrey Petrov | 3b63753 | 2016-11-30 17:39:16 -0800 | [diff] [blame] | 19 | #include <soc/cpu.h> |
Alexandru Gagniuc | a633980 | 2016-04-05 12:40:24 -0700 | [diff] [blame] | 20 | #include <soc/pci_devs.h> |
Hannah Williams | 01bc897 | 2016-02-04 20:13:34 -0800 | [diff] [blame] | 21 | #include <soc/pm.h> |
Subrata Banik | 7bc4dc5 | 2018-05-17 18:40:32 +0530 | [diff] [blame] | 22 | #include <soc/smbus.h> |
Philipp Deppenwiese | fea2429 | 2017-10-17 17:02:29 +0200 | [diff] [blame] | 23 | #include <security/vboot/vbnv.h> |
Elyes HAOUAS | add76f9 | 2019-03-21 09:55:49 +0100 | [diff] [blame] | 24 | |
Duncan Laurie | a673d1c | 2016-09-19 12:02:54 -0700 | [diff] [blame] | 25 | #include "chip.h" |
Hannah Williams | 01bc897 | 2016-02-04 20:13:34 -0800 | [diff] [blame] | 26 | |
Subrata Banik | 480e7e5 | 2022-02-01 19:01:36 +0530 | [diff] [blame] | 27 | uint8_t *pmc_mmio_regs(void) |
Alexandru Gagniuc | a633980 | 2016-04-05 12:40:24 -0700 | [diff] [blame] | 28 | { |
Subrata Banik | 480e7e5 | 2022-02-01 19:01:36 +0530 | [diff] [blame] | 29 | return (void *)(uintptr_t)PCH_PWRM_BASE_ADDRESS; |
Alexandru Gagniuc | a633980 | 2016-04-05 12:40:24 -0700 | [diff] [blame] | 30 | } |
Hannah Williams | 01bc897 | 2016-02-04 20:13:34 -0800 | [diff] [blame] | 31 | |
Shaunak Saha | 93cdc8b | 2017-04-18 15:42:09 -0700 | [diff] [blame] | 32 | uintptr_t soc_read_pmc_base(void) |
Shaunak Saha | 9a0c9ac | 2016-06-27 23:00:15 -0700 | [diff] [blame] | 33 | { |
Subrata Banik | 480e7e5 | 2022-02-01 19:01:36 +0530 | [diff] [blame] | 34 | return (uintptr_t)pmc_mmio_regs(); |
Shaunak Saha | 9a0c9ac | 2016-06-27 23:00:15 -0700 | [diff] [blame] | 35 | } |
| 36 | |
Michael Niewöhner | b4d960b | 2019-11-02 12:14:06 +0100 | [diff] [blame] | 37 | uint32_t *soc_pmc_etr_addr(void) |
| 38 | { |
| 39 | return (uint32_t *)(soc_read_pmc_base() + ETR); |
| 40 | } |
| 41 | |
Shaunak Saha | 93cdc8b | 2017-04-18 15:42:09 -0700 | [diff] [blame] | 42 | const char *const *soc_smi_sts_array(size_t *a) |
Hannah Williams | 01bc897 | 2016-02-04 20:13:34 -0800 | [diff] [blame] | 43 | { |
Shaunak Saha | 93cdc8b | 2017-04-18 15:42:09 -0700 | [diff] [blame] | 44 | static const char *const smi_sts_bits[] = { |
Subrata Banik | 4ab7ef9 | 2020-02-20 11:53:04 +0530 | [diff] [blame] | 45 | [BIOS_STS_BIT] = "BIOS", |
| 46 | [LEGACY_USB_STS_BIT] = "LEGACY USB", |
| 47 | [SMI_ON_SLP_EN_STS_BIT] = "SLP_SMI", |
| 48 | [APM_STS_BIT] = "APM", |
| 49 | [SWSMI_TMR_STS_BIT] = "SWSMI_TMR", |
| 50 | [PM1_STS_BIT] = "PM1", |
Angel Pons | 81e9263 | 2021-02-19 16:02:45 +0100 | [diff] [blame] | 51 | [GPE0_STS_BIT] = "GPE0 (reserved)", |
Subrata Banik | 4ab7ef9 | 2020-02-20 11:53:04 +0530 | [diff] [blame] | 52 | [GPIO_STS_BIT] = "GPIO_SMI", |
| 53 | [GPIO_UNLOCK_SMI_STS_BIT] = "GPIO_UNLOCK_SSMI", |
| 54 | [MC_SMI_STS_BIT] = "MCSMI", |
| 55 | [TCO_STS_BIT] = "TCO", |
| 56 | [PERIODIC_STS_BIT] = "PERIODIC", |
| 57 | [SERIRQ_SMI_STS_BIT] = "SERIRQ", |
| 58 | [SMBUS_SMI_STS_BIT] = "SMBUS_SMI", |
| 59 | [XHCI_SMI_STS_BIT] = "XHCI", |
| 60 | [SCS_SMI_STS_BIT] = "HOST_SMBUS", |
| 61 | [SCS_SMI_STS_BIT] = "SCS", |
| 62 | [PCI_EXP_SMI_STS_BIT] = "PCI_EXP_SMI", |
| 63 | [SCC2_SMI_STS_BIT] = "SCC2", |
| 64 | [SPI_SSMI_STS_BIT] = "SPI_SSMI", |
| 65 | [SPI_SMI_STS_BIT] = "SPI", |
| 66 | [PMC_OCP_SMI_STS_BIT] = "OCP_CSE", |
Hannah Williams | 01bc897 | 2016-02-04 20:13:34 -0800 | [diff] [blame] | 67 | }; |
| 68 | |
Shaunak Saha | 93cdc8b | 2017-04-18 15:42:09 -0700 | [diff] [blame] | 69 | *a = ARRAY_SIZE(smi_sts_bits); |
| 70 | return smi_sts_bits; |
Hannah Williams | 01bc897 | 2016-02-04 20:13:34 -0800 | [diff] [blame] | 71 | } |
| 72 | |
Shaunak Saha | 93cdc8b | 2017-04-18 15:42:09 -0700 | [diff] [blame] | 73 | /* |
| 74 | * For APL/GLK this check for power button status if nothing else |
| 75 | * is indicating an SMI and SMIs aren't turned into SCIs. |
| 76 | * Apparently, there is no PM1 status bit in the SMI status |
| 77 | * register. That makes things difficult for |
| 78 | * determining if the power button caused an SMI. |
| 79 | */ |
| 80 | uint32_t soc_get_smi_status(uint32_t generic_sts) |
Hannah Williams | 01bc897 | 2016-02-04 20:13:34 -0800 | [diff] [blame] | 81 | { |
Furquan Shaikh | 43810d9 | 2017-10-16 22:22:46 -0700 | [diff] [blame] | 82 | if (generic_sts == 0 && !(pmc_read_pm1_control() & SCI_EN)) { |
Barnali Sarkar | 9e55ff6 | 2017-06-05 20:01:14 +0530 | [diff] [blame] | 83 | uint16_t pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS); |
Aaron Durbin | a554b71 | 2016-06-10 18:04:21 -0500 | [diff] [blame] | 84 | |
| 85 | /* Fake PM1 status bit if power button pressed. */ |
| 86 | if (pm1_sts & PWRBTN_STS) |
Subrata Banik | 4ab7ef9 | 2020-02-20 11:53:04 +0530 | [diff] [blame] | 87 | generic_sts |= (1 << PM1_STS_BIT); |
Aaron Durbin | a554b71 | 2016-06-10 18:04:21 -0500 | [diff] [blame] | 88 | } |
| 89 | |
Angel Pons | 81e9263 | 2021-02-19 16:02:45 +0100 | [diff] [blame] | 90 | /* |
| 91 | * GPE0_STS is reserved in APL/GLK datasheets. For compatibility |
| 92 | * with common code, mask it out so that it is always zero. |
| 93 | */ |
| 94 | return generic_sts & ~(1 << GPE0_STS_BIT); |
Hannah Williams | 01bc897 | 2016-02-04 20:13:34 -0800 | [diff] [blame] | 95 | } |
| 96 | |
Shaunak Saha | 93cdc8b | 2017-04-18 15:42:09 -0700 | [diff] [blame] | 97 | const char *const *soc_tco_sts_array(size_t *a) |
Hannah Williams | 01bc897 | 2016-02-04 20:13:34 -0800 | [diff] [blame] | 98 | { |
Shaunak Saha | 93cdc8b | 2017-04-18 15:42:09 -0700 | [diff] [blame] | 99 | static const char *const tco_sts_bits[] = { |
Hannah Williams | 01bc897 | 2016-02-04 20:13:34 -0800 | [diff] [blame] | 100 | [3] = "TIMEOUT", |
| 101 | [17] = "SECOND_TO", |
| 102 | }; |
| 103 | |
Shaunak Saha | 93cdc8b | 2017-04-18 15:42:09 -0700 | [diff] [blame] | 104 | *a = ARRAY_SIZE(tco_sts_bits); |
| 105 | return tco_sts_bits; |
Hannah Williams | 01bc897 | 2016-02-04 20:13:34 -0800 | [diff] [blame] | 106 | } |
| 107 | |
Furquan Shaikh | c4e652f | 2017-10-11 14:44:29 -0700 | [diff] [blame] | 108 | const char *const *soc_std_gpe_sts_array(size_t *a) |
Hannah Williams | 01bc897 | 2016-02-04 20:13:34 -0800 | [diff] [blame] | 109 | { |
Shaunak Saha | 93cdc8b | 2017-04-18 15:42:09 -0700 | [diff] [blame] | 110 | static const char *const gpe_sts_bits[] = { |
Hannah Williams | 01bc897 | 2016-02-04 20:13:34 -0800 | [diff] [blame] | 111 | [0] = "PCIE_SCI", |
| 112 | [2] = "SWGPE", |
| 113 | [3] = "PCIE_WAKE0", |
| 114 | [4] = "PUNIT", |
| 115 | [6] = "PCIE_WAKE1", |
| 116 | [7] = "PCIE_WAKE2", |
| 117 | [8] = "PCIE_WAKE3", |
| 118 | [9] = "PCI_EXP", |
| 119 | [10] = "BATLOW", |
| 120 | [11] = "CSE_PME", |
| 121 | [12] = "XDCI_PME", |
| 122 | [13] = "XHCI_PME", |
| 123 | [14] = "AVS_PME", |
| 124 | [15] = "GPIO_TIER1_SCI", |
| 125 | [16] = "SMB_WAK", |
| 126 | [17] = "SATA_PME", |
| 127 | }; |
| 128 | |
Shaunak Saha | 93cdc8b | 2017-04-18 15:42:09 -0700 | [diff] [blame] | 129 | *a = ARRAY_SIZE(gpe_sts_bits); |
| 130 | return gpe_sts_bits; |
Hannah Williams | 01bc897 | 2016-02-04 20:13:34 -0800 | [diff] [blame] | 131 | } |
| 132 | |
Shaunak Saha | 93cdc8b | 2017-04-18 15:42:09 -0700 | [diff] [blame] | 133 | void soc_clear_pm_registers(uintptr_t pmc_bar) |
Duncan Laurie | 2e79009 | 2016-09-19 12:05:49 -0700 | [diff] [blame] | 134 | { |
Hannah Williams | 01bc897 | 2016-02-04 20:13:34 -0800 | [diff] [blame] | 135 | uint32_t gen_pmcon1; |
| 136 | |
Shaunak Saha | 93cdc8b | 2017-04-18 15:42:09 -0700 | [diff] [blame] | 137 | gen_pmcon1 = read32((void *)(pmc_bar + GEN_PMCON1)); |
Hannah Williams | 01bc897 | 2016-02-04 20:13:34 -0800 | [diff] [blame] | 138 | /* Clear the status bits. The RPS field is cleared on a 0 write. */ |
Shaunak Saha | 93cdc8b | 2017-04-18 15:42:09 -0700 | [diff] [blame] | 139 | write32((void *)(pmc_bar + GEN_PMCON1), gen_pmcon1 & ~RPS); |
Hannah Williams | 01bc897 | 2016-02-04 20:13:34 -0800 | [diff] [blame] | 140 | } |
| 141 | |
Furquan Shaikh | c4e652f | 2017-10-11 14:44:29 -0700 | [diff] [blame] | 142 | void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2) |
Hannah Williams | 01bc897 | 2016-02-04 20:13:34 -0800 | [diff] [blame] | 143 | { |
Aaron Durbin | e4d7abc | 2017-04-16 22:05:36 -0500 | [diff] [blame] | 144 | DEVTREE_CONST struct soc_intel_apollolake_config *config; |
Duncan Laurie | a673d1c | 2016-09-19 12:02:54 -0700 | [diff] [blame] | 145 | |
Kyösti Mälkki | d5f645c | 2019-09-28 00:20:27 +0300 | [diff] [blame] | 146 | config = config_of_soc(); |
Duncan Laurie | a673d1c | 2016-09-19 12:02:54 -0700 | [diff] [blame] | 147 | |
Shaunak Saha | 93cdc8b | 2017-04-18 15:42:09 -0700 | [diff] [blame] | 148 | /* Assign to out variable */ |
| 149 | *dw0 = config->gpe0_dw1; |
| 150 | *dw1 = config->gpe0_dw2; |
| 151 | *dw2 = config->gpe0_dw3; |
| 152 | } |
Duncan Laurie | a673d1c | 2016-09-19 12:02:54 -0700 | [diff] [blame] | 153 | |
Shaunak Saha | 93cdc8b | 2017-04-18 15:42:09 -0700 | [diff] [blame] | 154 | void soc_fill_power_state(struct chipset_power_state *ps) |
| 155 | { |
Subrata Banik | 480e7e5 | 2022-02-01 19:01:36 +0530 | [diff] [blame] | 156 | uintptr_t pmc_bar0 = soc_read_pmc_base(); |
Duncan Laurie | a673d1c | 2016-09-19 12:02:54 -0700 | [diff] [blame] | 157 | |
Subrata Banik | 7bc4dc5 | 2018-05-17 18:40:32 +0530 | [diff] [blame] | 158 | ps->tco1_sts = tco_read_reg(TCO1_STS); |
| 159 | ps->tco2_sts = tco_read_reg(TCO2_STS); |
| 160 | |
Shaunak Saha | 93cdc8b | 2017-04-18 15:42:09 -0700 | [diff] [blame] | 161 | ps->prsts = read32((void *)(pmc_bar0 + PRSTS)); |
| 162 | ps->gen_pmcon1 = read32((void *)(pmc_bar0 + GEN_PMCON1)); |
| 163 | ps->gen_pmcon2 = read32((void *)(pmc_bar0 + GEN_PMCON2)); |
| 164 | ps->gen_pmcon3 = read32((void *)(pmc_bar0 + GEN_PMCON3)); |
Duncan Laurie | a673d1c | 2016-09-19 12:02:54 -0700 | [diff] [blame] | 165 | |
Subrata Banik | 7bc4dc5 | 2018-05-17 18:40:32 +0530 | [diff] [blame] | 166 | printk(BIOS_DEBUG, "prsts: %08x\n", |
| 167 | ps->prsts); |
| 168 | printk(BIOS_DEBUG, "tco_sts: %04x %04x\n", |
| 169 | ps->tco1_sts, ps->tco2_sts); |
Shaunak Saha | 93cdc8b | 2017-04-18 15:42:09 -0700 | [diff] [blame] | 170 | printk(BIOS_DEBUG, |
| 171 | "gen_pmcon1: %08x gen_pmcon2: %08x gen_pmcon3: %08x\n", |
| 172 | ps->gen_pmcon1, ps->gen_pmcon2, ps->gen_pmcon3); |
Duncan Laurie | a673d1c | 2016-09-19 12:02:54 -0700 | [diff] [blame] | 173 | } |
Andrey Petrov | 3b63753 | 2016-11-30 17:39:16 -0800 | [diff] [blame] | 174 | |
Hannah Williams | cdecc0d | 2018-01-04 11:57:14 -0800 | [diff] [blame] | 175 | /* Return 0, 3, or 5 to indicate the previous sleep state. */ |
| 176 | int soc_prev_sleep_state(const struct chipset_power_state *ps, |
| 177 | int prev_sleep_state) |
| 178 | { |
| 179 | /* WAK_STS bit will not be set when waking from G3 state */ |
| 180 | |
| 181 | if (!(ps->pm1_sts & WAK_STS) && (ps->gen_pmcon1 & COLD_BOOT_STS)) |
| 182 | prev_sleep_state = ACPI_S5; |
| 183 | return prev_sleep_state; |
| 184 | } |
| 185 | |
Aaron Durbin | 3118b62 | 2017-09-15 11:48:53 -0600 | [diff] [blame] | 186 | static int rtc_failed(uint32_t gen_pmcon1) |
| 187 | { |
| 188 | return !!(gen_pmcon1 & RPS); |
| 189 | } |
| 190 | |
| 191 | int soc_get_rtc_failed(void) |
| 192 | { |
Kyösti Mälkki | 2787237 | 2021-01-21 16:05:26 +0200 | [diff] [blame] | 193 | const struct chipset_power_state *ps; |
Aaron Durbin | 3118b62 | 2017-09-15 11:48:53 -0600 | [diff] [blame] | 194 | |
Kyösti Mälkki | 2787237 | 2021-01-21 16:05:26 +0200 | [diff] [blame] | 195 | if (acpi_pm_state_for_rtc(&ps) < 0) |
Aaron Durbin | 3118b62 | 2017-09-15 11:48:53 -0600 | [diff] [blame] | 196 | return 1; |
Aaron Durbin | 3118b62 | 2017-09-15 11:48:53 -0600 | [diff] [blame] | 197 | |
| 198 | return rtc_failed(ps->gen_pmcon1); |
| 199 | } |
Aaron Durbin | 0990fbf | 2017-09-15 15:23:04 -0600 | [diff] [blame] | 200 | |
| 201 | int vbnv_cmos_failed(void) |
| 202 | { |
Subrata Banik | 480e7e5 | 2022-02-01 19:01:36 +0530 | [diff] [blame] | 203 | uintptr_t pmc_bar = soc_read_pmc_base(); |
Furquan Shaikh | 9d07910 | 2018-02-02 15:11:29 -0800 | [diff] [blame] | 204 | uint32_t gen_pmcon1 = read32((void *)(pmc_bar + GEN_PMCON1)); |
| 205 | int rtc_failure = rtc_failed(gen_pmcon1); |
| 206 | |
| 207 | if (rtc_failure) { |
| 208 | printk(BIOS_INFO, "RTC failed!\n"); |
| 209 | |
| 210 | /* We do not want to write 1 to clear-1 bits. Set them to 0. */ |
| 211 | gen_pmcon1 &= ~GEN_PMCON1_CLR1_BITS; |
| 212 | |
| 213 | /* RPS is write 0 to clear. */ |
| 214 | gen_pmcon1 &= ~RPS; |
| 215 | |
| 216 | write32((void *)(pmc_bar + GEN_PMCON1), gen_pmcon1); |
| 217 | } |
| 218 | |
| 219 | return rtc_failure; |
Aaron Durbin | 0990fbf | 2017-09-15 15:23:04 -0600 | [diff] [blame] | 220 | } |
Eugene Myers | ebc8423 | 2020-01-21 16:46:16 -0500 | [diff] [blame] | 221 | |
| 222 | /* STM Support */ |
| 223 | uint16_t get_pmbase(void) |
| 224 | { |
| 225 | return (uint16_t) ACPI_BASE_ADDRESS; |
| 226 | } |
Angel Pons | 505e383 | 2021-04-17 13:02:37 +0200 | [diff] [blame] | 227 | |
| 228 | void pmc_soc_set_afterg3_en(const bool on) |
| 229 | { |
Angel Pons | f585c6e | 2021-06-25 10:09:35 +0200 | [diff] [blame] | 230 | const uintptr_t gen_pmcon1 = soc_read_pmc_base() + GEN_PMCON1; |
Angel Pons | 505e383 | 2021-04-17 13:02:37 +0200 | [diff] [blame] | 231 | uint32_t reg32; |
| 232 | |
Angel Pons | f585c6e | 2021-06-25 10:09:35 +0200 | [diff] [blame] | 233 | reg32 = read32p(gen_pmcon1); |
Angel Pons | 505e383 | 2021-04-17 13:02:37 +0200 | [diff] [blame] | 234 | if (on) |
| 235 | reg32 &= ~SLEEP_AFTER_POWER_FAIL; |
| 236 | else |
| 237 | reg32 |= SLEEP_AFTER_POWER_FAIL; |
Angel Pons | f585c6e | 2021-06-25 10:09:35 +0200 | [diff] [blame] | 238 | write32p(gen_pmcon1, reg32); |
Angel Pons | 505e383 | 2021-04-17 13:02:37 +0200 | [diff] [blame] | 239 | } |
Subrata Banik | 42914fe | 2022-02-06 18:45:44 +0530 | [diff] [blame] | 240 | |
| 241 | void pmc_clear_pmcon_sts(void) |
| 242 | { |
| 243 | uint32_t reg_val; |
| 244 | uint8_t *addr; |
| 245 | addr = pmc_mmio_regs(); |
| 246 | |
| 247 | reg_val = read32(addr + GEN_PMCON1); |
| 248 | /* Clear SUS_PWR_FLR, GBL_RST_STS, HOST_RST_STS, PWR_FLR bits |
| 249 | * while retaining MS4V write-1-to-clear bit */ |
| 250 | reg_val &= ~(MS4V); |
| 251 | |
| 252 | write32((addr + GEN_PMCON1), reg_val); |
| 253 | } |