Angel Pons | e67ab18 | 2020-04-04 18:51:11 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Tristan Shieh | 3ddf57e | 2018-05-31 09:20:53 +0800 | [diff] [blame] | 2 | |
| 3 | #include <memlayout.h> |
| 4 | |
| 5 | #include <arch/header.ld> |
| 6 | |
| 7 | /* |
| 8 | * SRAM_L2C is the half part of L2 cache that we borrow to be used as SRAM. |
| 9 | * It will be returned before starting the ramstage. |
| 10 | * SRAM_L2C and SRAM can be cached, but only SRAM is DMA-able. |
| 11 | */ |
Julius Werner | 82d16b1 | 2020-12-30 15:51:10 -0800 | [diff] [blame] | 12 | #define SRAM_L2C_START(addr) REGION_START(sram_l2c, addr) |
| 13 | #define SRAM_L2C_END(addr) REGION_END(sram_l2c, addr) |
Huayang Duan | 846be44 | 2019-08-30 18:01:19 +0800 | [diff] [blame] | 14 | #define DRAM_INIT_CODE(addr, size) \ |
| 15 | REGION(dram_init_code, addr, size, 4) |
Tristan Shieh | 3ddf57e | 2018-05-31 09:20:53 +0800 | [diff] [blame] | 16 | |
Yidi Lin | c221d56 | 2020-12-02 16:43:43 +0800 | [diff] [blame] | 17 | #define DRAM_DMA(addr, size) \ |
| 18 | REGION(dram_dma, addr, size, 4K) \ |
| 19 | _ = ASSERT(size % 4K == 0, \ |
| 20 | "DRAM DMA buffer should be multiple of smallest page size (4K)!"); |
| 21 | |
Tristan Shieh | 3ddf57e | 2018-05-31 09:20:53 +0800 | [diff] [blame] | 22 | SECTIONS |
| 23 | { |
| 24 | SRAM_START(0x00100000) |
| 25 | VBOOT2_WORK(0x00100000, 12K) |
Sergii Dmytruk | 2710df7 | 2022-11-10 00:40:51 +0200 | [diff] [blame] | 26 | TPM_LOG(0x00103000, 2K) |
Hung-Te Lin | e477626 | 2019-11-13 17:37:17 +0800 | [diff] [blame] | 27 | FMAP_CACHE(0x00103800, 2K) |
| 28 | WATCHDOG_TOMBSTONE(0x00104000, 4) |
| 29 | PRERAM_CBMEM_CONSOLE(0x00104004, 63K - 4) |
| 30 | TIMESTAMP(0x00113c00, 1K) |
Tristan Shieh | 4b5eefa | 2019-08-16 15:35:50 +0800 | [diff] [blame] | 31 | STACK(0x00114000, 16K) |
| 32 | TTB(0x00118000, 28K) |
| 33 | DMA_COHERENT(0x0011f000, 4K) |
Tristan Shieh | 3ddf57e | 2018-05-31 09:20:53 +0800 | [diff] [blame] | 34 | SRAM_END(0x00120000) |
| 35 | |
| 36 | SRAM_L2C_START(0x00200000) |
Tristan Shieh | 526d840 | 2019-08-06 14:19:03 +0800 | [diff] [blame] | 37 | OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0x00201000, 188K) |
Julius Werner | baf27db | 2019-10-02 17:28:56 -0700 | [diff] [blame] | 38 | BOOTBLOCK(0x00230000, 56K) |
| 39 | CBFS_MCACHE(0x0023e000, 8K) |
Hung-Te Lin | e477626 | 2019-11-13 17:37:17 +0800 | [diff] [blame] | 40 | DRAM_INIT_CODE(0x00240000, 208K) |
| 41 | PRERAM_CBFS_CACHE(0x00274000, 48K) |
Tristan Shieh | 3ddf57e | 2018-05-31 09:20:53 +0800 | [diff] [blame] | 42 | SRAM_L2C_END(0x00280000) |
| 43 | |
| 44 | DRAM_START(0x40000000) |
Yidi Lin | c221d56 | 2020-12-02 16:43:43 +0800 | [diff] [blame] | 45 | DRAM_DMA(0x40000000, 1M) |
| 46 | POSTRAM_CBFS_CACHE(0x40100000, 1M) |
Patrick Georgi | 42f1505 | 2023-10-07 11:16:43 +0200 | [diff] [blame^] | 47 | RAMSTAGE(0x40200000, 2M) |
Ting Shen | dff29e0 | 2019-01-28 18:15:00 +0800 | [diff] [blame] | 48 | |
| 49 | BL31(0x54600000, 0x60000) |
Tristan Shieh | 3ddf57e | 2018-05-31 09:20:53 +0800 | [diff] [blame] | 50 | } |