| Angel Pons | e67ab18 | 2020-04-04 18:51:11 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| Tristan Shieh | 3ddf57e | 2018-05-31 09:20:53 +0800 | [diff] [blame] | 2 | |
| 3 | #include <memlayout.h> |
| 4 | |
| 5 | #include <arch/header.ld> |
| 6 | |
| 7 | /* |
| 8 | * SRAM_L2C is the half part of L2 cache that we borrow to be used as SRAM. |
| 9 | * It will be returned before starting the ramstage. |
| 10 | * SRAM_L2C and SRAM can be cached, but only SRAM is DMA-able. |
| 11 | */ |
| 12 | #define SRAM_L2C_START(addr) SYMBOL(sram_l2c, addr) |
| 13 | #define SRAM_L2C_END(addr) SYMBOL(esram_l2c, addr) |
| Huayang Duan | 846be44 | 2019-08-30 18:01:19 +0800 | [diff] [blame] | 14 | #define DRAM_INIT_CODE(addr, size) \ |
| 15 | REGION(dram_init_code, addr, size, 4) |
| Tristan Shieh | 3ddf57e | 2018-05-31 09:20:53 +0800 | [diff] [blame] | 16 | |
| Tristan Shieh | 3ddf57e | 2018-05-31 09:20:53 +0800 | [diff] [blame] | 17 | SECTIONS |
| 18 | { |
| 19 | SRAM_START(0x00100000) |
| 20 | VBOOT2_WORK(0x00100000, 12K) |
| Bill XIE | c79e96b | 2019-08-22 20:28:36 +0800 | [diff] [blame] | 21 | TPM_TCPA_LOG(0x00103000, 2K) |
| Hung-Te Lin | e477626 | 2019-11-13 17:37:17 +0800 | [diff] [blame] | 22 | FMAP_CACHE(0x00103800, 2K) |
| 23 | WATCHDOG_TOMBSTONE(0x00104000, 4) |
| 24 | PRERAM_CBMEM_CONSOLE(0x00104004, 63K - 4) |
| 25 | TIMESTAMP(0x00113c00, 1K) |
| Tristan Shieh | 4b5eefa | 2019-08-16 15:35:50 +0800 | [diff] [blame] | 26 | STACK(0x00114000, 16K) |
| 27 | TTB(0x00118000, 28K) |
| 28 | DMA_COHERENT(0x0011f000, 4K) |
| Tristan Shieh | 3ddf57e | 2018-05-31 09:20:53 +0800 | [diff] [blame] | 29 | SRAM_END(0x00120000) |
| 30 | |
| 31 | SRAM_L2C_START(0x00200000) |
| Tristan Shieh | 526d840 | 2019-08-06 14:19:03 +0800 | [diff] [blame] | 32 | OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0x00201000, 188K) |
| Julius Werner | baf27db | 2019-10-02 17:28:56 -0700 | [diff] [blame^] | 33 | BOOTBLOCK(0x00230000, 56K) |
| 34 | CBFS_MCACHE(0x0023e000, 8K) |
| Hung-Te Lin | e477626 | 2019-11-13 17:37:17 +0800 | [diff] [blame] | 35 | DRAM_INIT_CODE(0x00240000, 208K) |
| 36 | PRERAM_CBFS_CACHE(0x00274000, 48K) |
| Tristan Shieh | 3ddf57e | 2018-05-31 09:20:53 +0800 | [diff] [blame] | 37 | SRAM_L2C_END(0x00280000) |
| 38 | |
| 39 | DRAM_START(0x40000000) |
| Tristan Shieh | 97bdb9a | 2018-06-15 14:16:48 +0800 | [diff] [blame] | 40 | POSTRAM_CBFS_CACHE(0x40000000, 2M) |
| Tristan Shieh | 3ddf57e | 2018-05-31 09:20:53 +0800 | [diff] [blame] | 41 | RAMSTAGE(0x40200000, 256K) |
| Ting Shen | dff29e0 | 2019-01-28 18:15:00 +0800 | [diff] [blame] | 42 | |
| 43 | BL31(0x54600000, 0x60000) |
| Tristan Shieh | 3ddf57e | 2018-05-31 09:20:53 +0800 | [diff] [blame] | 44 | } |