soc/mediatek/mt8183: Add DRAM_DMA section
mtk_init_mcu uses DRAM_DMA section as CBFS buffer.
The change "mediatek/mt8183: Remove DRAM_DMA section" is reverted
for using mtk_init_mcu.
On mt8173 and mt8192, this region is used by DMA hardware and is
marked as non-cacheable resource. On mt8183, this region is reserved
as CBFS buffer, so it is not necessary to be marked as non-cacheable
resource.
Change-Id: I7ce9f68883e2787ee7f3c5066f4c47c5ca315633
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48232
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
diff --git a/src/soc/mediatek/mt8183/memlayout.ld b/src/soc/mediatek/mt8183/memlayout.ld
index db56666..a549274 100644
--- a/src/soc/mediatek/mt8183/memlayout.ld
+++ b/src/soc/mediatek/mt8183/memlayout.ld
@@ -14,6 +14,11 @@
#define DRAM_INIT_CODE(addr, size) \
REGION(dram_init_code, addr, size, 4)
+#define DRAM_DMA(addr, size) \
+ REGION(dram_dma, addr, size, 4K) \
+ _ = ASSERT(size % 4K == 0, \
+ "DRAM DMA buffer should be multiple of smallest page size (4K)!");
+
SECTIONS
{
SRAM_START(0x00100000)
@@ -37,7 +42,8 @@
SRAM_L2C_END(0x00280000)
DRAM_START(0x40000000)
- POSTRAM_CBFS_CACHE(0x40000000, 2M)
+ DRAM_DMA(0x40000000, 1M)
+ POSTRAM_CBFS_CACHE(0x40100000, 1M)
RAMSTAGE(0x40200000, 256K)
BL31(0x54600000, 0x60000)