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review.coreboot.org / coreboot / 0c983df7caa041f86f28938ccae31ce2d45803e5 / . / src / vendorcode / amd / agesa / f14 / Config / PlatformInstall.h
blob: 86fe800a2a33baa3ac9f6a8d153f2805f65b0b9e [file] [log] [blame]
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]1/* $NoKeywords:$ */
2/**
3 * @file
4 *
5 * Install of build options for a combination of package type, processor, and features.
6 *
7 * This file generates the defaults tables for the all platform solution
8 * combinations. The documented build options are imported from a user
9 * controlled file for processing.
10 *
11 * @xrefitem bom "File Content Label" "Release Content"
12 * @e project: AGESA
13 * @e sub-project: Core
efdesign9884cbce22011-08-04 12:09:17 -0600[diff] [blame]14 * @e \$Revision: 47417 $ @e \$Date: 2011-02-18 12:48:20 -0700 (Fri, 18 Feb 2011) $
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]15 */
16/*
17 *****************************************************************************
18 *
19 * Copyright (c) 2011, Advanced Micro Devices, Inc.
20 * All rights reserved.
Edward O'Callaghane963b382014-07-06 19:27:14 +1000[diff] [blame]21 *
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]22 * Redistribution and use in source and binary forms, with or without
23 * modification, are permitted provided that the following conditions are met:
24 * * Redistributions of source code must retain the above copyright
25 * notice, this list of conditions and the following disclaimer.
26 * * Redistributions in binary form must reproduce the above copyright
27 * notice, this list of conditions and the following disclaimer in the
28 * documentation and/or other materials provided with the distribution.
Edward O'Callaghane963b382014-07-06 19:27:14 +1000[diff] [blame]29 * * Neither the name of Advanced Micro Devices, Inc. nor the names of
30 * its contributors may be used to endorse or promote products derived
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]31 * from this software without specific prior written permission.
Edward O'Callaghane963b382014-07-06 19:27:14 +1000[diff] [blame]32 *
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]33 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
34 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
35 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
36 * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
37 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
38 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
39 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
40 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
41 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
42 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Edward O'Callaghane963b382014-07-06 19:27:14 +1000[diff] [blame]43 *
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]44 * ***************************************************************************
45 *
46 */
47
48/*****************************************************************************
49 *
50 * Start processing the user options: First, set default settings
51 *
52 ****************************************************************************/
53
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]54VOLATILE AMD_MODULE_HEADER mCpuModuleID = {
55 //ModuleHeaderSignature
56 // Remove 'DOM$' as temp solution before update BinUtil.exe ,
efdesign9884cbce22011-08-04 12:09:17 -0600[diff] [blame]57 Int32FromChar ('0', '0', '0', '0'),
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]58 //ModuleIdentifier[8]
59 AGESA_ID,
60 //ModuleVersion[12]
61 AGESA_VERSION_STRING,
62 //ModuleDispatcher
63 NULL,//(VOID *)(UINT64)((MODULE_ENTRY)AmdAgesaDispatcher),
64 //NextBlock
65 NULL
66};
67
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]68/* Process solution defined socket / family installations
69 *
70 * As part of the release package for each image, define the options below to select the
71 * AGESA processor support included in that image.
72 */
73
74/* Default sockets to off */
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]75#define OPTION_FT1_SOCKET_SUPPORT FALSE
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]76
77/* Default families to off */
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]78#define OPTION_FAMILY14H FALSE
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]79
80/* Enable the appropriate socket support */
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]81#ifdef INSTALL_FT1_SOCKET_SUPPORT
82 #if INSTALL_FT1_SOCKET_SUPPORT == TRUE
83 #undef OPTION_FT1_SOCKET_SUPPORT
84 #define OPTION_FT1_SOCKET_SUPPORT TRUE
85 #endif
86#endif
87
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]88// F14 is supported in FT1
89#ifdef INSTALL_FAMILY_14_SUPPORT
90 #if INSTALL_FAMILY_14_SUPPORT == TRUE
91 #undef OPTION_FAMILY14H
92 #define OPTION_FAMILY14H TRUE
93 #endif
94#endif
95
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]96#if (OPTION_FAMILY14H == TRUE)
97 #if (OPTION_FT1_SOCKET_SUPPORT == FALSE)
98 #undef OPTION_FAMILY14H
99 #define OPTION_FAMILY14H FALSE
100 #endif
101#endif
102
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]103
104/* Check for invalid combinations of socket/family */
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]105
106#if (OPTION_FT1_SOCKET_SUPPORT == TRUE)
107 #if (OPTION_FAMILY14H == FALSE)
108 #error No FT1 supported families included in the build
109 #endif
110#endif
111
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]112/* Process AGESA private data
113 *
114 * Turn on appropriate CPU models and memory controllers,
115 * as well as some other memory controls.
116 */
117
118/* Default all models to off */
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]119#define OPTION_FAMILY14H_ON FALSE
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]120
121/* Default all memory controllers to off */
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]122#define OPTION_MEMCTLR_ON FALSE
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]123
124/* Default all memory controls to off */
125#define OPTION_HW_WRITE_LEV_TRAINING FALSE
126#define OPTION_SW_WRITE_LEV_TRAINING FALSE
127#define OPTION_CONTINOUS_PATTERN_GENERATION FALSE
128#define OPTION_HW_DQS_REC_EN_TRAINING FALSE
129#define OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING FALSE
130#define OPTION_OPT_SW_DQS_REC_EN_TRAINING FALSE
131#define OPTION_NON_OPT_SW_RD_WR_POS_TRAINING FALSE
132#define OPTION_OPT_SW_RD_WR_POS_TRAINING FALSE
133#define OPTION_MAX_RD_LAT_TRAINING FALSE
134#define OPTION_HW_DRAM_INIT FALSE
135#define OPTION_SW_DRAM_INIT FALSE
136#define OPTION_S3_MEM_SUPPORT FALSE
137#define OPTION_ADDR_TO_CS_TRANSLATOR FALSE
138
139/* Defaults for public user options */
140#define OPTION_UDIMMS FALSE
141#define OPTION_RDIMMS FALSE
142#define OPTION_SODIMMS FALSE
143#define OPTION_LRDIMMS FALSE
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]144#define OPTION_DDR3 FALSE
145#define OPTION_ECC FALSE
146#define OPTION_BANK_INTERLEAVE FALSE
147#define OPTION_DCT_INTERLEAVE FALSE
148#define OPTION_NODE_INTERLEAVE FALSE
149#define OPTION_PARALLEL_TRAINING FALSE
150#define OPTION_ONLINE_SPARE FALSE
151#define OPTION_MEM_RESTORE FALSE
152#define OPTION_DIMM_EXCLUDE FALSE
153
154/* Default all CPU controls to off */
155#define OPTION_MULTISOCKET FALSE
156#define OPTION_SRAT FALSE
157#define OPTION_SLIT FALSE
158#define OPTION_HT_ASSIST FALSE
159#define OPTION_ATM_MODE FALSE
160#define OPTION_CPU_CORELEVLING FALSE
161#define OPTION_MSG_BASED_C1E FALSE
162#define OPTION_CPU_CFOH FALSE
163#define OPTION_C6_STATE FALSE
164#define OPTION_IO_CSTATE FALSE
165#define OPTION_CPB FALSE
166#define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT FALSE
167#define OPTION_S3SCRIPT FALSE
168#define OPTION_GFX_RECOVERY FALSE
169
170/* Enable all private controls based on socket/family enables */
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]171
172#if (OPTION_FT1_SOCKET_SUPPORT == TRUE)
173 #if (OPTION_FAMILY14H == TRUE)
174 #undef OPTION_FAMILY14H_ON
175 #define OPTION_FAMILY14H_ON TRUE
176 #undef OPTION_MEMCTLR_ON
177 #define OPTION_MEMCTLR_ON TRUE
178 #undef OPTION_HW_WRITE_LEV_TRAINING
179 #define OPTION_HW_WRITE_LEV_TRAINING TRUE
180 #undef OPTION_CONTINOUS_PATTERN_GENERATION
181 #define OPTION_CONTINOUS_PATTERN_GENERATION TRUE
182 #undef OPTION_MAX_RD_LAT_TRAINING
183 #define OPTION_MAX_RD_LAT_TRAINING TRUE
184 #undef OPTION_HW_DQS_REC_EN_TRAINING
185 #define OPTION_HW_DQS_REC_EN_TRAINING TRUE
186 #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
187 #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
188 #undef OPTION_SW_DRAM_INIT
189 #define OPTION_SW_DRAM_INIT TRUE
190 #undef OPTION_S3_MEM_SUPPORT
191 #define OPTION_S3_MEM_SUPPORT TRUE
192 #undef OPTION_GFX_RECOVERY
193 #define OPTION_GFX_RECOVERY TRUE
194 #undef OPTION_C6_STATE
195 #define OPTION_C6_STATE TRUE
efdesign9884cbce22011-08-04 12:09:17 -0600[diff] [blame]196 #undef OPTION_CPB
197 #define OPTION_CPB TRUE
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]198 #undef OPTION_IO_CSTATE
199 #define OPTION_IO_CSTATE TRUE
200 #undef OPTION_S3SCRIPT
201 #define OPTION_S3SCRIPT TRUE
202 #undef OPTION_UDIMMS
203 #define OPTION_UDIMMS TRUE
204 #undef OPTION_SODIMMS
205 #define OPTION_SODIMMS TRUE
206 #undef OPTION_DDR3
207 #define OPTION_DDR3 TRUE
208 #undef OPTION_BANK_INTERLEAVE
209 #define OPTION_BANK_INTERLEAVE TRUE
210 #undef OPTION_MEM_RESTORE
211 #define OPTION_MEM_RESTORE TRUE
212 #undef OPTION_DIMM_EXCLUDE
213 #define OPTION_DIMM_EXCLUDE TRUE
214 #endif
215#endif
216
Kyösti Mälkkiba4e6952017-08-31 15:17:36 +0300[diff] [blame]217#if (OPTION_FAMILY14H == TRUE)
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]218 #undef GNB_SUPPORT
219 #define GNB_SUPPORT TRUE
220#endif
221
222#define OPTION_ACPI_PSTATES TRUE
223#define OPTION_WHEA TRUE
224#define OPTION_DMI TRUE
225#define OPTION_EARLY_SAMPLES FALSE
226#define CFG_ACPI_PSTATES_PPC TRUE
227#define CFG_ACPI_PSTATES_PCT TRUE
228#define CFG_ACPI_PSTATES_PSD TRUE
229#define CFG_ACPI_PSTATES_PSS TRUE
230#define CFG_ACPI_PSTATES_XPSS TRUE
231#define CFG_ACPI_PSTATE_PSD_INDPX FALSE
232#define CFG_VRM_HIGH_SPEED_ENABLE FALSE
233#define CFG_VRM_NB_HIGH_SPEED_ENABLE FALSE
234#define OPTION_ALIB TRUE
235/*---------------------------------------------------------------------------
236 * Processing the options: Second, process the user's selections
237 *--------------------------------------------------------------------------*/
238#ifdef BLDOPT_REMOVE_MULTISOCKET_SUPPORT
239 #if BLDOPT_REMOVE_MULTISOCKET_SUPPORT == TRUE
240 #undef OPTION_MULTISOCKET
241 #define OPTION_MULTISOCKET FALSE
242 #endif
243#endif
244#ifdef BLDOPT_REMOVE_ECC_SUPPORT
245 #if BLDOPT_REMOVE_ECC_SUPPORT == TRUE
246 #undef OPTION_ECC
247 #define OPTION_ECC FALSE
248 #endif
249#endif
250#ifdef BLDOPT_REMOVE_UDIMMS_SUPPORT
251 #if BLDOPT_REMOVE_UDIMMS_SUPPORT == TRUE
252 #undef OPTION_UDIMMS
253 #define OPTION_UDIMMS FALSE
254 #endif
255#endif
256#ifdef BLDOPT_REMOVE_RDIMMS_SUPPORT
257 #if BLDOPT_REMOVE_RDIMMS_SUPPORT == TRUE
258 #undef OPTION_RDIMMS
259 #define OPTION_RDIMMS FALSE
260 #endif
261#endif
262#ifdef BLDOPT_REMOVE_SODIMMS_SUPPORT
263 #if BLDOPT_REMOVE_SODIMMS_SUPPORT == TRUE
264 #undef OPTION_SODIMMS
265 #define OPTION_SODIMMS FALSE
266 #endif
267#endif
268#ifdef BLDOPT_REMOVE_LRDIMMS_SUPPORT
269 #if BLDOPT_REMOVE_LRDIMMS_SUPPORT == TRUE
270 #undef OPTION_LRDIMMS
271 #define OPTION_LRDIMMS FALSE
272 #endif
273#endif
274#ifdef BLDOPT_REMOVE_BANK_INTERLEAVE
275 #if BLDOPT_REMOVE_BANK_INTERLEAVE == TRUE
276 #undef OPTION_BANK_INTERLEAVE
277 #define OPTION_BANK_INTERLEAVE FALSE
278 #endif
279#endif
280#ifdef BLDOPT_REMOVE_DCT_INTERLEAVE
281 #if BLDOPT_REMOVE_DCT_INTERLEAVE == TRUE
282 #undef OPTION_DCT_INTERLEAVE
283 #define OPTION_DCT_INTERLEAVE FALSE
284 #endif
285#endif
286#ifdef BLDOPT_REMOVE_NODE_INTERLEAVE
287 #if BLDOPT_REMOVE_NODE_INTERLEAVE == TRUE
288 #undef OPTION_NODE_INTERLEAVE
289 #define OPTION_NODE_INTERLEAVE FALSE
290 #endif
291#endif
292#ifdef BLDOPT_REMOVE_PARALLEL_TRAINING
293 #if BLDOPT_REMOVE_PARALLEL_TRAINING == TRUE
294 #undef OPTION_PARALLEL_TRAINING
295 #define OPTION_PARALLEL_TRAINING FALSE
296 #endif
297#endif
298#ifdef BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT
299 #if BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT == TRUE
300 #undef OPTION_ONLINE_SPARE
301 #define OPTION_ONLINE_SPARE FALSE
302 #endif
303#endif
304#ifdef BLDOPT_REMOVE_MEM_RESTORE_SUPPORT
305 #if BLDOPT_REMOVE_MEM_RESTORE_SUPPORT == TRUE
306 #undef OPTION_MEM_RESTORE
307 #define OPTION_MEM_RESTORE FALSE
308 #endif
309#endif
310#ifdef BLDOPT_REMOVE_ACPI_PSTATES
311 #if BLDOPT_REMOVE_ACPI_PSTATES == TRUE
312 #undef OPTION_ACPI_PSTATES
313 #define OPTION_ACPI_PSTATES FALSE
314 #endif
315#endif
316#ifdef BLDOPT_REMOVE_SRAT
317 #if BLDOPT_REMOVE_SRAT == TRUE
318 #undef OPTION_SRAT
319 #define OPTION_SRAT FALSE
320 #endif
321#endif
322#ifdef BLDOPT_REMOVE_SLIT
323 #if BLDOPT_REMOVE_SLIT == TRUE
324 #undef OPTION_SLIT
325 #define OPTION_SLIT FALSE
326 #endif
327#endif
328#ifdef BLDOPT_REMOVE_WHEA
329 #if BLDOPT_REMOVE_WHEA == TRUE
330 #undef OPTION_WHEA
331 #define OPTION_WHEA FALSE
332 #endif
333#endif
334#ifdef BLDOPT_REMOVE_DMI
335 #if BLDOPT_REMOVE_DMI == TRUE
336 #undef OPTION_DMI
337 #define OPTION_DMI FALSE
338 #endif
339#endif
340#ifdef BLDOPT_REMOVE_ADDR_TO_CS_TRANSLATOR
341 #if BLDOPT_REMOVE_ADDR_TO_CS_TRANSLATOR == TRUE
342 #undef OPTION_ADDR_TO_CS_TRANSLATOR
343 #define OPTION_ADDR_TO_CS_TRANSLATOR FALSE
344 #endif
345#endif
346
347#ifdef BLDOPT_REMOVE_HT_ASSIST
348 #if BLDOPT_REMOVE_HT_ASSIST == TRUE
349 #undef OPTION_HT_ASSIST
350 #define OPTION_HT_ASSIST FALSE
351 #endif
352#endif
353
354#ifdef BLDOPT_REMOVE_ATM_MODE
355 #if BLDOPT_REMOVE_ATM_MODE == TRUE
356 #undef OPTION_ATM_MODE
357 #define OPTION_ATM_MODE FALSE
358 #endif
359#endif
360
361#ifdef BLDOPT_REMOVE_MSG_BASED_C1E
362 #if BLDOPT_REMOVE_MSG_BASED_C1E == TRUE
363 #undef OPTION_MSG_BASED_C1E
364 #define OPTION_MSG_BASED_C1E FALSE
365 #endif
366#endif
367
368#ifdef BLDOPT_REMOVE_C6_STATE
369 #if BLDOPT_REMOVE_C6_STATE == TRUE
370 #undef OPTION_C6_STATE
371 #define OPTION_C6_STATE FALSE
372 #endif
373#endif
374
375#ifdef BLDOPT_REMOVE_GFX_RECOVERY
376 #if BLDOPT_REMOVE_GFX_RECOVERY == TRUE
377 #undef OPTION_GFX_RECOVERY
378 #define OPTION_GFX_RECOVERY FALSE
379 #endif
380#endif
381
382#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PPC
383 #if BLDCFG_REMOVE_ACPI_PSTATES_PPC == TRUE
384 #undef CFG_ACPI_PSTATES_PPC
385 #define CFG_ACPI_PSTATES_PPC FALSE
386 #endif
387#endif
388
389#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PCT
390 #if BLDCFG_REMOVE_ACPI_PSTATES_PCT == TRUE
391 #undef CFG_ACPI_PSTATES_PCT
392 #define CFG_ACPI_PSTATES_PCT FALSE
393 #endif
394#endif
395
396#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PSD
397 #if BLDCFG_REMOVE_ACPI_PSTATES_PSD == TRUE
398 #undef CFG_ACPI_PSTATES_PSD
399 #define CFG_ACPI_PSTATES_PSD FALSE
400 #endif
401#endif
402
403#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PSS
404 #if BLDCFG_REMOVE_ACPI_PSTATES_PSS == TRUE
405 #undef CFG_ACPI_PSTATES_PSS
406 #define CFG_ACPI_PSTATES_PSS FALSE
407 #endif
408#endif
409
410#ifdef BLDCFG_REMOVE_ACPI_PSTATES_XPSS
411 #if BLDCFG_REMOVE_ACPI_PSTATES_XPSS == TRUE
412 #undef CFG_ACPI_PSTATES_XPSS
413 #define CFG_ACPI_PSTATES_XPSS FALSE
414 #endif
415#endif
416
417#ifdef BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT
418 #if BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT == TRUE
419 #undef CFG_ACPI_PSTATE_PSD_INDPX
420 #define CFG_ACPI_PSTATE_PSD_INDPX TRUE
421 #endif
422#endif
423
424#ifdef BLDCFG_VRM_HIGH_SPEED_ENABLE
425 #if BLDCFG_VRM_HIGH_SPEED_ENABLE == TRUE
426 #undef CFG_VRM_HIGH_SPEED_ENABLE
427 #define CFG_VRM_HIGH_SPEED_ENABLE TRUE
428 #endif
429#endif
430
431#ifdef BLDCFG_VRM_NB_HIGH_SPEED_ENABLE
432 #if BLDCFG_VRM_NB_HIGH_SPEED_ENABLE == TRUE
433 #undef CFG_VRM_NB_HIGH_SPEED_ENABLE
434 #define CFG_VRM_NB_HIGH_SPEED_ENABLE TRUE
435 #endif
436#endif
437
438#ifdef BLDCFG_STARTING_BUSNUM
439 #define CFG_STARTING_BUSNUM (BLDCFG_STARTING_BUSNUM)
440#else
441 #define CFG_STARTING_BUSNUM (0)
442#endif
443
444#ifdef BLDCFG_AMD_PLATFORM_TYPE
445 #define CFG_AMD_PLATFORM_TYPE BLDCFG_AMD_PLATFORM_TYPE
446#else
447 #define CFG_AMD_PLATFORM_TYPE 0
448#endif
449
450CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
451
452#ifdef BLDCFG_MAXIMUM_BUSNUM
453 #define CFG_MAXIMUM_BUSNUM (BLDCFG_MAXIMUM_BUSNUM)
454#else
455 #define CFG_MAXIMUM_BUSNUM (0xF8)
456#endif
457
458#ifdef BLDCFG_ALLOCATED_BUSNUM
459 #define CFG_ALLOCATED_BUSNUM (BLDCFG_ALLOCATED_BUSNUM)
460#else
461 #define CFG_ALLOCATED_BUSNUM (0x20)
462#endif
463
464#ifdef BLDCFG_BUID_SWAP_LIST
465 #define CFG_BUID_SWAP_LIST (BLDCFG_BUID_SWAP_LIST)
466#else
467 #define CFG_BUID_SWAP_LIST (NULL)
468#endif
469
470#ifdef BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST
471 #define CFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST (BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST)
472#else
473 #define CFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST (NULL)
474#endif
475
476#ifdef BLDCFG_HTFABRIC_LIMITS_LIST
477 #define CFG_HTFABRIC_LIMITS_LIST (BLDCFG_HTFABRIC_LIMITS_LIST)
478#else
479 #define CFG_HTFABRIC_LIMITS_LIST (NULL)
480#endif
481
482#ifdef BLDCFG_HTCHAIN_LIMITS_LIST
483 #define CFG_HTCHAIN_LIMITS_LIST (BLDCFG_HTCHAIN_LIMITS_LIST)
484#else
485 #define CFG_HTCHAIN_LIMITS_LIST (NULL)
486#endif
487
488#ifdef BLDCFG_BUS_NUMBERS_LIST
489 #define CFG_BUS_NUMBERS_LIST (BLDCFG_BUS_NUMBERS_LIST)
490#else
491 #define CFG_BUS_NUMBERS_LIST (NULL)
492#endif
493
494#ifdef BLDCFG_IGNORE_LINK_LIST
495 #define CFG_IGNORE_LINK_LIST (BLDCFG_IGNORE_LINK_LIST)
496#else
497 #define CFG_IGNORE_LINK_LIST (NULL)
498#endif
499
500#ifdef BLDCFG_LINK_SKIP_REGANG_LIST
501 #define CFG_LINK_SKIP_REGANG_LIST (BLDCFG_LINK_SKIP_REGANG_LIST)
502#else
503 #define CFG_LINK_SKIP_REGANG_LIST (NULL)
504#endif
505
506#ifdef BLDCFG_SET_HTCRC_SYNC_FLOOD
507 #define CFG_SET_HTCRC_SYNC_FLOOD (BLDCFG_SET_HTCRC_SYNC_FLOOD)
508#else
509 #define CFG_SET_HTCRC_SYNC_FLOOD (FALSE)
510#endif
511
512#ifdef BLDCFG_USE_UNIT_ID_CLUMPING
513 #define CFG_USE_UNIT_ID_CLUMPING (BLDCFG_USE_UNIT_ID_CLUMPING)
514#else
515 #define CFG_USE_UNIT_ID_CLUMPING (FALSE)
516#endif
517
518#ifdef BLDCFG_ADDITIONAL_TOPOLOGIES_LIST
519 #define CFG_ADDITIONAL_TOPOLOGIES_LIST (BLDCFG_ADDITIONAL_TOPOLOGIES_LIST)
520#else
521 #define CFG_ADDITIONAL_TOPOLOGIES_LIST (NULL)
522#endif
523
524#ifdef BLDCFG_USE_HT_ASSIST
525 #define CFG_USE_HT_ASSIST (BLDCFG_USE_HT_ASSIST)
526#else
527 #define CFG_USE_HT_ASSIST (TRUE)
528#endif
529
530#ifdef BLDCFG_USE_ATM_MODE
531 #define CFG_USE_ATM_MODE (BLDCFG_USE_ATM_MODE)
532#else
533 #define CFG_USE_ATM_MODE (TRUE)
534#endif
535
536#ifdef BLDCFG_PLATFORM_CONTROL_FLOW_MODE
537 #define CFG_PLATFORM_CONTROL_FLOW_MODE (BLDCFG_PLATFORM_CONTROL_FLOW_MODE)
538#else
539 #define CFG_PLATFORM_CONTROL_FLOW_MODE (Nfcm)
540#endif
541
542#ifdef BLDCFG_PLATFORM_DEEMPHASIS_LIST
543 #define CFG_PLATFORM_DEEMPHASIS_LIST (BLDCFG_PLATFORM_DEEMPHASIS_LIST)
544#else
545 #define CFG_PLATFORM_DEEMPHASIS_LIST (NULL)
546#endif
547
548#ifdef BLDCFG_VRM_ADDITIONAL_DELAY
549 #define CFG_VRM_ADDITIONAL_DELAY (BLDCFG_VRM_ADDITIONAL_DELAY)
550#else
551 #define CFG_VRM_ADDITIONAL_DELAY (0)
552#endif
553
554#ifdef BLDCFG_VRM_CURRENT_LIMIT
555 #define CFG_VRM_CURRENT_LIMIT BLDCFG_VRM_CURRENT_LIMIT
556#else
557 #define CFG_VRM_CURRENT_LIMIT 0
558#endif
559
560#ifdef BLDCFG_VRM_LOW_POWER_THRESHOLD
561 #define CFG_VRM_LOW_POWER_THRESHOLD BLDCFG_VRM_LOW_POWER_THRESHOLD
562#else
563 #define CFG_VRM_LOW_POWER_THRESHOLD 0
564#endif
565
566#ifdef BLDCFG_VRM_SLEW_RATE
567 #define CFG_VRM_SLEW_RATE BLDCFG_VRM_SLEW_RATE
568#else
569 #define CFG_VRM_SLEW_RATE DFLT_VRM_SLEW_RATE
570#endif
571
572#ifdef BLDCFG_VRM_INRUSH_CURRENT_LIMIT
573 #define CFG_VRM_INRUSH_CURRENT_LIMIT BLDCFG_VRM_INRUSH_CURRENT_LIMIT
574#else
575 #define CFG_VRM_INRUSH_CURRENT_LIMIT 0
576#endif
577
578#ifdef BLDCFG_VRM_NB_ADDITIONAL_DELAY
579 #define CFG_VRM_NB_ADDITIONAL_DELAY (BLDCFG_VRM_NB_ADDITIONAL_DELAY)
580#else
581 #define CFG_VRM_NB_ADDITIONAL_DELAY (0)
582#endif
583
584#ifdef BLDCFG_VRM_NB_CURRENT_LIMIT
585 #define CFG_VRM_NB_CURRENT_LIMIT BLDCFG_VRM_NB_CURRENT_LIMIT
586#else
587 #define CFG_VRM_NB_CURRENT_LIMIT (0)
588#endif
589
590#ifdef BLDCFG_VRM_NB_LOW_POWER_THRESHOLD
591 #define CFG_VRM_NB_LOW_POWER_THRESHOLD BLDCFG_VRM_NB_LOW_POWER_THRESHOLD
592#else
593 #define CFG_VRM_NB_LOW_POWER_THRESHOLD (0)
594#endif
595
596#ifdef BLDCFG_VRM_NB_SLEW_RATE
597 #define CFG_VRM_NB_SLEW_RATE BLDCFG_VRM_NB_SLEW_RATE
598#else
599 #define CFG_VRM_NB_SLEW_RATE DFLT_VRM_SLEW_RATE
600#endif
601
602#ifdef BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT
603 #define CFG_VRM_NB_INRUSH_CURRENT_LIMIT BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT
604#else
605 #define CFG_VRM_NB_INRUSH_CURRENT_LIMIT (0)
606#endif
607
608
609#ifdef BLDCFG_PLAT_NUM_IO_APICS
610 #define CFG_PLAT_NUM_IO_APICS BLDCFG_PLAT_NUM_IO_APICS
611#else
612 #define CFG_PLAT_NUM_IO_APICS 0
613#endif
614
615#ifdef BLDCFG_MEM_INIT_PSTATE
616 #define CFG_MEM_INIT_PSTATE BLDCFG_MEM_INIT_PSTATE
617#else
618 #define CFG_MEM_INIT_PSTATE 0
619#endif
620
621#ifdef BLDCFG_PLATFORM_C1E_MODE
622 #define CFG_C1E_MODE BLDCFG_PLATFORM_C1E_MODE
623#else
624 #define CFG_C1E_MODE C1eModeDisabled
625#endif
626
627#ifdef BLDCFG_PLATFORM_C1E_OPDATA
628 #define CFG_C1E_OPDATA BLDCFG_PLATFORM_C1E_OPDATA
629#else
630 #define CFG_C1E_OPDATA 0
631#endif
632
633#ifdef BLDCFG_PLATFORM_C1E_OPDATA1
634 #define CFG_C1E_OPDATA1 BLDCFG_PLATFORM_C1E_OPDATA1
635#else
636 #define CFG_C1E_OPDATA1 0
637#endif
638
639#ifdef BLDCFG_PLATFORM_C1E_OPDATA2
640 #define CFG_C1E_OPDATA2 BLDCFG_PLATFORM_C1E_OPDATA2
641#else
642 #define CFG_C1E_OPDATA2 0
643#endif
644
645#ifdef BLDCFG_PLATFORM_CSTATE_MODE
646 #define CFG_CSTATE_MODE BLDCFG_PLATFORM_CSTATE_MODE
647#else
648 #define CFG_CSTATE_MODE CStateModeDisabled
649#endif
650
651#ifdef BLDCFG_PLATFORM_CSTATE_OPDATA
652 #define CFG_CSTATE_OPDATA BLDCFG_PLATFORM_CSTATE_OPDATA
653#else
654 #define CFG_CSTATE_OPDATA 0
655#endif
656
657#ifdef BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS
658 #define CFG_CSTATE_IO_BASE_ADDRESS BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS
659#else
660 #define CFG_CSTATE_IO_BASE_ADDRESS 0
661#endif
662
663#ifdef BLDCFG_PLATFORM_CPB_MODE
664 #define CFG_CPB_MODE BLDCFG_PLATFORM_CPB_MODE
665#else
666 #define CFG_CPB_MODE CpbModeAuto
667#endif
668
669#ifdef BLDCFG_CORE_LEVELING_MODE
670 #define CFG_CORE_LEVELING_MODE BLDCFG_CORE_LEVELING_MODE
671#else
672 #define CFG_CORE_LEVELING_MODE 0
673#endif
674
675#ifdef BLDCFG_AMD_PSTATE_CAP_VALUE
676 #define CFG_AMD_PSTATE_CAP_VALUE BLDCFG_AMD_PSTATE_CAP_VALUE
677#else
678 #define CFG_AMD_PSTATE_CAP_VALUE 0
679#endif
680
681#ifdef BLDCFG_HEAP_DRAM_ADDRESS
682 #define CFG_HEAP_DRAM_ADDRESS BLDCFG_HEAP_DRAM_ADDRESS
683#else
684 #define CFG_HEAP_DRAM_ADDRESS AMD_HEAP_RAM_ADDRESS
685#endif
686
687#ifdef BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT
688 #define CFG_MEMORY_BUS_FREQUENCY_LIMIT BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT
689#else
690 #define CFG_MEMORY_BUS_FREQUENCY_LIMIT DDR800_FREQUENCY
691#endif
692
693#ifdef BLDCFG_MEMORY_MODE_UNGANGED
694 #define CFG_MEMORY_MODE_UNGANGED BLDCFG_MEMORY_MODE_UNGANGED
695#else
696 #define CFG_MEMORY_MODE_UNGANGED TRUE
697#endif
698
699#ifdef BLDCFG_MEMORY_QUAD_RANK_CAPABLE
700 #define CFG_MEMORY_QUAD_RANK_CAPABLE BLDCFG_MEMORY_QUAD_RANK_CAPABLE
701#else
702 #define CFG_MEMORY_QUAD_RANK_CAPABLE TRUE
703#endif
704
705#ifdef BLDCFG_MEMORY_QUADRANK_TYPE
706 #define CFG_MEMORY_QUADRANK_TYPE BLDCFG_MEMORY_QUADRANK_TYPE
707#else
708 #define CFG_MEMORY_QUADRANK_TYPE DFLT_MEMORY_QUADRANK_TYPE
709#endif
710
711#ifdef BLDCFG_MEMORY_RDIMM_CAPABLE
712 #define CFG_MEMORY_RDIMM_CAPABLE BLDCFG_MEMORY_RDIMM_CAPABLE
713#else
714 #define CFG_MEMORY_RDIMM_CAPABLE TRUE
715#endif
716
717#ifdef BLDCFG_MEMORY_LRDIMM_CAPABLE
718 #define CFG_MEMORY_LRDIMM_CAPABLE BLDCFG_MEMORY_LRDIMM_CAPABLE
719#else
720 #define CFG_MEMORY_LRDIMM_CAPABLE TRUE
721#endif
722
723#ifdef BLDCFG_MEMORY_UDIMM_CAPABLE
724 #define CFG_MEMORY_UDIMM_CAPABLE BLDCFG_MEMORY_UDIMM_CAPABLE
725#else
726 #define CFG_MEMORY_UDIMM_CAPABLE TRUE
727#endif
728
729#ifdef BLDCFG_MEMORY_SODIMM_CAPABLE
730 #define CFG_MEMORY_SODIMM_CAPABLE BLDCFG_MEMORY_SODIMM_CAPABLE
731#else
732 #define CFG_MEMORY_SODIMM_CAPABLE FALSE
733#endif
734
735#ifdef BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING
736 #define CFG_MEMORY_ENABLE_BANK_INTERLEAVING BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING
737#else
738 #define CFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE
739#endif
740
741#ifdef BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING
742 #define CFG_MEMORY_ENABLE_NODE_INTERLEAVING BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING
743#else
744 #define CFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE
745#endif
746
747#ifdef BLDCFG_MEMORY_CHANNEL_INTERLEAVING
748 #define CFG_MEMORY_CHANNEL_INTERLEAVING BLDCFG_MEMORY_CHANNEL_INTERLEAVING
749#else
750 #define CFG_MEMORY_CHANNEL_INTERLEAVING TRUE
751#endif
752
753#ifdef BLDCFG_MEMORY_POWER_DOWN
754 #define CFG_MEMORY_POWER_DOWN BLDCFG_MEMORY_POWER_DOWN
755#else
756 #define CFG_MEMORY_POWER_DOWN FALSE
757#endif
758
759#ifdef BLDCFG_POWER_DOWN_MODE
760 #define CFG_POWER_DOWN_MODE BLDCFG_POWER_DOWN_MODE
761#else
762 #define CFG_POWER_DOWN_MODE POWER_DOWN_MODE_AUTO
763#endif
764
765#ifdef BLDCFG_ONLINE_SPARE
766 #define CFG_ONLINE_SPARE BLDCFG_ONLINE_SPARE
767#else
768 #define CFG_ONLINE_SPARE FALSE
769#endif
770
771#ifdef BLDCFG_MEMORY_PARITY_ENABLE
772 #define CFG_MEMORY_PARITY_ENABLE BLDCFG_MEMORY_PARITY_ENABLE
773#else
774 #define CFG_MEMORY_PARITY_ENABLE FALSE
775#endif
776
777#ifdef BLDCFG_BANK_SWIZZLE
778 #define CFG_BANK_SWIZZLE BLDCFG_BANK_SWIZZLE
779#else
780 #define CFG_BANK_SWIZZLE TRUE
781#endif
782
783#ifdef BLDCFG_TIMING_MODE_SELECT
784 #define CFG_TIMING_MODE_SELECT BLDCFG_TIMING_MODE_SELECT
785#else
786 #define CFG_TIMING_MODE_SELECT TIMING_MODE_AUTO
787#endif
788
789#ifdef BLDCFG_MEMORY_CLOCK_SELECT
790 #define CFG_MEMORY_CLOCK_SELECT BLDCFG_MEMORY_CLOCK_SELECT
791#else
792 #define CFG_MEMORY_CLOCK_SELECT DDR800_FREQUENCY
793#endif
794
795#ifdef BLDCFG_DQS_TRAINING_CONTROL
796 #define CFG_DQS_TRAINING_CONTROL BLDCFG_DQS_TRAINING_CONTROL
797#else
798 #define CFG_DQS_TRAINING_CONTROL TRUE
799#endif
800
801#ifdef BLDCFG_IGNORE_SPD_CHECKSUM
802 #define CFG_IGNORE_SPD_CHECKSUM BLDCFG_IGNORE_SPD_CHECKSUM
803#else
804 #define CFG_IGNORE_SPD_CHECKSUM FALSE
805#endif
806
807#ifdef BLDCFG_USE_BURST_MODE
808 #define CFG_USE_BURST_MODE BLDCFG_USE_BURST_MODE
809#else
810 #define CFG_USE_BURST_MODE FALSE
811#endif
812
813#ifdef BLDCFG_MEMORY_ALL_CLOCKS_ON
814 #define CFG_MEMORY_ALL_CLOCKS_ON BLDCFG_MEMORY_ALL_CLOCKS_ON
815#else
816 #define CFG_MEMORY_ALL_CLOCKS_ON FALSE
817#endif
818
819#ifdef BLDCFG_ENABLE_ECC_FEATURE
820 #define CFG_ENABLE_ECC_FEATURE BLDCFG_ENABLE_ECC_FEATURE
821#else
822 #define CFG_ENABLE_ECC_FEATURE TRUE
823#endif
824
825#ifdef BLDCFG_ECC_REDIRECTION
826 #define CFG_ECC_REDIRECTION BLDCFG_ECC_REDIRECTION
827#else
828 #define CFG_ECC_REDIRECTION FALSE
829#endif
830
831#ifdef BLDCFG_SCRUB_DRAM_RATE
832 #define CFG_SCRUB_DRAM_RATE BLDCFG_SCRUB_DRAM_RATE
833#else
834 #define CFG_SCRUB_DRAM_RATE DFLT_SCRUB_DRAM_RATE
835#endif
836
837#ifdef BLDCFG_SCRUB_L2_RATE
838 #define CFG_SCRUB_L2_RATE BLDCFG_SCRUB_L2_RATE
839#else
840 #define CFG_SCRUB_L2_RATE DFLT_SCRUB_L2_RATE
841#endif
842
843#ifdef BLDCFG_SCRUB_L3_RATE
844 #define CFG_SCRUB_L3_RATE BLDCFG_SCRUB_L3_RATE
845#else
846 #define CFG_SCRUB_L3_RATE DFLT_SCRUB_L3_RATE
847#endif
848
849#ifdef BLDCFG_SCRUB_IC_RATE
850 #define CFG_SCRUB_IC_RATE BLDCFG_SCRUB_IC_RATE
851#else
852 #define CFG_SCRUB_IC_RATE DFLT_SCRUB_IC_RATE
853#endif
854
855#ifdef BLDCFG_SCRUB_DC_RATE
856 #define CFG_SCRUB_DC_RATE BLDCFG_SCRUB_DC_RATE
857#else
858 #define CFG_SCRUB_DC_RATE DFLT_SCRUB_DC_RATE
859#endif
860
861#ifdef BLDCFG_ECC_SYNC_FLOOD
862 #define CFG_ECC_SYNC_FLOOD BLDCFG_ECC_SYNC_FLOOD
863#else
864 #define CFG_ECC_SYNC_FLOOD 0
865#endif
866
867#ifdef BLDCFG_ECC_SYMBOL_SIZE
868 #define CFG_ECC_SYMBOL_SIZE BLDCFG_ECC_SYMBOL_SIZE
869#else
870 #define CFG_ECC_SYMBOL_SIZE 0
871#endif
872
873#ifdef BLDCFG_1GB_ALIGN
874 #define CFG_1GB_ALIGN BLDCFG_1GB_ALIGN
875#else
876 #define CFG_1GB_ALIGN FALSE
877#endif
878
879#ifdef BLDCFG_UMA_ALLOCATION_MODE
880 #define CFG_UMA_MODE BLDCFG_UMA_ALLOCATION_MODE
881#else
882 #define CFG_UMA_MODE UMA_AUTO
883#endif
884
885#ifdef BLDCFG_UMA_ALLOCATION_SIZE
886 #define CFG_UMA_SIZE BLDCFG_UMA_ALLOCATION_SIZE
887#else
888 #define CFG_UMA_SIZE 0
889#endif
890
891#ifdef BLDCFG_UMA_ABOVE4G_SUPPORT
892 #define CFG_UMA_ABOVE4G BLDCFG_UMA_ABOVE4G_SUPPORT
893#else
894 #define CFG_UMA_ABOVE4G FALSE
895#endif
896
897#ifdef BLDCFG_UMA_ALIGNMENT
898 #define CFG_UMA_ALIGNMENT BLDCFG_UMA_ALIGNMENT
899#else
900 #define CFG_UMA_ALIGNMENT NO_UMA_ALIGNED
901#endif
902
903#ifdef BLDCFG_PROCESSOR_SCOPE_IN_SB
904 #define CFG_PROCESSOR_SCOPE_IN_SB BLDCFG_PROCESSOR_SCOPE_IN_SB
905#else
906 #define CFG_PROCESSOR_SCOPE_IN_SB FALSE
907#endif
908
909#ifdef BLDCFG_S3_LATE_RESTORE
910 #define CFG_S3_LATE_RESTORE BLDCFG_S3_LATE_RESTORE
911#else
912 #define CFG_S3_LATE_RESTORE TRUE
913#endif
914
915#ifdef BLDCFG_USE_32_BYTE_REFRESH
916 #define CFG_USE_32_BYTE_REFRESH (BLDCFG_USE_32_BYTE_REFRESH)
917#else
918 #define CFG_USE_32_BYTE_REFRESH (FALSE)
919#endif
920
921#ifdef BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY
922 #define CFG_USE_VARIABLE_MCT_ISOC_PRIORITY (BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY)
923#else
924 #define CFG_USE_VARIABLE_MCT_ISOC_PRIORITY (FALSE)
925#endif
926
927#ifdef BLDCFG_PROCESSOR_SCOPE_NAME0
928 #define CFG_PROCESSOR_SCOPE_NAME0 BLDCFG_PROCESSOR_SCOPE_NAME0
929#else
930 #define CFG_PROCESSOR_SCOPE_NAME0 SCOPE_NAME_VALUE
931#endif
932
933#ifdef BLDCFG_PROCESSOR_SCOPE_NAME1
934 #define CFG_PROCESSOR_SCOPE_NAME1 BLDCFG_PROCESSOR_SCOPE_NAME1
935#else
936 #define CFG_PROCESSOR_SCOPE_NAME1 SCOPE_NAME_VALUE1
937#endif
938
939#ifdef BLDCFG_CFG_GNB_HD_AUDIO
940 #define CFG_GNB_HD_AUDIO BLDCFG_CFG_GNB_HD_AUDIO
941#else
942 #define CFG_GNB_HD_AUDIO TRUE
943#endif
944
945#ifdef BLDCFG_CFG_ABM_SUPPORT
946 #define CFG_ABM_SUPPORT BLDCFG_CFG_ABM_SUPPORT
947#else
948 #define CFG_ABM_SUPPORT FALSE
949#endif
950
951#ifdef BLDCFG_CFG_DYNAMIC_REFRESH_RATE
952 #define CFG_DINAMIC_REFRESH_RATE BLDCFG_CFG_DYNAMIC_REFRESH_RATE
953#else
954 #define CFG_DYNAMIC_REFRESH_RATE 0
955#endif
956
957#ifdef BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL
958 #define CFG_LCD_BACK_LIGHT_CONTROL BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL
959#else
960 #define CFG_LCD_BACK_LIGHT_CONTROL 0
961#endif
962
963#ifdef BLDCFG_STEREO_3D_PINOUT
964 #define CFG_GNB_STEREO_3D_PINOUT BLDCFG_STEREO_3D_PINOUT
965#else
966 #define CFG_GNB_STEREO_3D_PINOUT 0
967#endif
968
969#ifdef BLDCFG_IGPU_SUBSYSTEM_ID
970 #define CFG_GNB_IGPU_SSID BLDCFG_IGPU_SUBSYSTEM_ID
971#else
972 #define CFG_GNB_IGPU_SSID 0
973#endif
974
975#ifdef BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID
976 #define CFG_GNB_HDAUDIO_SSID BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID
977#else
978 #define CFG_GNB_HDAUDIO_SSID 0
979#endif
980
981#ifdef BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID
982 #define CFG_GNB_PCIE_SSID BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID
983#else
984 #define CFG_GNB_PCIE_SSID 0x12341022
985#endif
986
987#ifdef BLDCFG_GFX_LVDS_SPREAD_SPECTRUM
988 #define CFG_GFX_LVDS_SPREAD_SPECTRUM BLDCFG_GFX_LVDS_SPREAD_SPECTRUM
989#else
990 #define CFG_GFX_LVDS_SPREAD_SPECTRUM 0
991#endif
992
993#ifdef BLDCFG_GFX_LVDS_SPREAD_SPECTRUM_RATE
994 #define CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE BLDCFG_GFX_LVDS_SPREAD_SPECTRUM_RATE
995#else
996 #define CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE 0
997#endif
998
efdesign9884cbce22011-08-04 12:09:17 -0600[diff] [blame]999#ifdef BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM
1000 #define CFG_PCIE_REFCLK_SPREAD_SPECTRUM BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM
1001#else
1002 #define CFG_PCIE_REFCLK_SPREAD_SPECTRUM 0
1003#endif
1004
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]1005#ifdef BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS
1006 #define CFG_TEMP_PCIE_MMIO_BASE_ADDRESS BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS
1007#else
1008 #define CFG_TEMP_PCIE_MMIO_BASE_ADDRESS 0xD0000000
1009#endif
1010
1011#ifdef BLDOPT_REMOVE_EARLY_SAMPLES
1012 #if BLDOPT_REMOVE_EARLY_SAMPLES == TRUE
1013 #undef OPTION_EARLY_SAMPLES
1014 #define OPTION_EARLY_SAMPLES FALSE
1015 #else
1016 #undef OPTION_EARLY_SAMPLES
1017 #define OPTION_EARLY_SAMPLES TRUE
1018 #endif
1019#endif
1020
1021#ifdef BLDOPT_REMOVE_ALIB
1022 #if BLDOPT_REMOVE_ALIB == TRUE
1023 #undef OPTION_ALIB
1024 #define OPTION_ALIB FALSE
1025 #else
1026 #undef OPTION_ALIB
1027 #define OPTION_ALIB TRUE
1028 #endif
1029#endif
1030
efdesign9884cbce22011-08-04 12:09:17 -0600[diff] [blame]1031#ifdef BLDCFG_LVDS_MISC_888_FPDI_MODE
1032 #define CFG_LVDS_MISC_888_FPDI_MODE BLDCFG_LVDS_MISC_888_FPDI_MODE
1033#else
1034 #define CFG_LVDS_MISC_888_FPDI_MODE FALSE
1035#endif
1036
1037#ifdef BLDCFG_LVDS_MISC_DL_CH_SWAP
1038 #define CFG_LVDS_MISC_DL_CH_SWAP BLDCFG_LVDS_MISC_DL_CH_SWAP
1039#else
1040 #define CFG_LVDS_MISC_DL_CH_SWAP FALSE
1041#endif
1042
1043#ifdef BLDCFG_LVDS_MISC_VSYNC_ACTIVE_LOW
1044 #define CFG_LVDS_MISC_VSYNC_ACTIVE_LOW BLDCFG_LVDS_MISC_VSYNC_ACTIVE_LOW
1045#else
1046 #define CFG_LVDS_MISC_VSYNC_ACTIVE_LOW FALSE
1047#endif
1048
1049#ifdef BLDCFG_LVDS_MISC_HSYNC_ACTIVE_LOW
1050 #define CFG_LVDS_MISC_HSYNC_ACTIVE_LOW BLDCFG_LVDS_MISC_HSYNC_ACTIVE_LOW
1051#else
1052 #define CFG_LVDS_MISC_HSYNC_ACTIVE_LOW FALSE
1053#endif
1054
1055#ifdef BLDCFG_LVDS_MISC_BLON_ACTIVE_LOW
1056 #define CFG_LVDS_MISC_BLON_ACTIVE_LOW BLDCFG_LVDS_MISC_BLON_ACTIVE_LOW
1057#else
1058 #define CFG_LVDS_MISC_BLON_ACTIVE_LOW FALSE
1059#endif
Kyösti Mälkki206e1572016-05-18 14:04:45 +0300[diff] [blame]1060
1061#ifdef BLDCFG_PLATFORM_POWER_POLICY_MODE
1062 #define CFG_PLATFORM_POWER_POLICY_MODE (BLDCFG_PLATFORM_POWER_POLICY_MODE)
1063#else
1064 #define CFG_PLATFORM_POWER_POLICY_MODE (Performance)
1065#endif
1066
1067#ifdef BLDCFG_PCI_MMIO_BASE
1068 #define CFG_PCI_MMIO_BASE (BLDCFG_PCI_MMIO_BASE)
1069#else
1070 #define CFG_PCI_MMIO_BASE (0)
1071#endif
1072
1073#ifdef BLDCFG_PCI_MMIO_SIZE
1074 #define CFG_PCI_MMIO_SIZE (BLDCFG_PCI_MMIO_SIZE)
1075#else
1076 #define CFG_PCI_MMIO_SIZE (0)
1077#endif
1078
1079#ifdef BLDCFG_AP_MTRR_SETTINGS_LIST
1080 #define CFG_AP_MTRR_SETTINGS_LIST (BLDCFG_AP_MTRR_SETTINGS_LIST)
1081#else
1082 #define CFG_AP_MTRR_SETTINGS_LIST (NULL)
1083#endif
1084
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]1085/*---------------------------------------------------------------------------
1086 * Processing the options: Third, perform the option cross checks
1087 *--------------------------------------------------------------------------*/
1088// Assure that at least one type of memory support is included
1089#if OPTION_UDIMMS == FALSE
1090 #if OPTION_RDIMMS == FALSE
1091 #if OPTION_SODIMMS == FALSE
1092 #if OPTION_LRDIMMS == FALSE
1093 #error BLDOPT: No DIMM support selected. Either BLDOPT_REMOVE_UDIMMS_SUPPORT or BLDOPT_REMOVE_RDIMMS_SUPPORT or BLDOPT_REMOVE_SODIMMS_SUPPORT or BLDOPT_REMOVE_LRDIMMS_SUPPORT must be FALSE.
1094 #endif
1095 #endif
1096 #endif
1097#endif
1098// Ensure at least one dimm type is capable
1099#if CFG_MEMORY_RDIMM_CAPABLE == FALSE
1100 #if CFG_MEMORY_UDIMM_CAPABLE == FALSE
1101 #if CFG_MEMORY_SODIMM_CAPABLE == FALSE
1102 #if CFG_MEMORY_LRDIMM_CAPABLE == FALSE
1103 #error BLDCFG: No dimm type is capable
1104 #endif
1105 #endif
1106 #endif
1107#endif
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]1108// Turn off multi-socket based features if only one node...
1109#if OPTION_MULTISOCKET == FALSE
1110 #undef OPTION_PARALLEL_TRAINING
1111 #define OPTION_PARALLEL_TRAINING FALSE
1112 #undef OPTION_NODE_INTERLEAVE
1113 #define OPTION_NODE_INTERLEAVE FALSE
1114#endif
1115// Ensure that at least one write leveling option is selected
1116#if OPTION_DDR3 == TRUE
1117 #if OPTION_HW_WRITE_LEV_TRAINING == FALSE
1118 #if OPTION_SW_WRITE_LEV_TRAINING == FALSE
1119 #error No Write leveling option selected for DDR3
1120 #endif
1121 #endif
1122 #if OPTION_SW_DRAM_INIT == FALSE
1123 #error Software dram init must be enabled for DDR3 dimms
1124 #endif
1125#endif
1126// Ensure at least one DQS receiver training option is selected
1127#if OPTION_HW_DQS_REC_EN_TRAINING == FALSE
1128 #if OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == FALSE
1129 #if OPTION_OPT_SW_DQS_REC_EN_TRAINING == FALSE
1130 #error No DQS receiver training option has been slected
1131 #endif
1132 #endif
1133#endif
1134// Ensure at least one Rd Wr position training option has been selected
1135#if OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == FALSE
1136 #if OPTION_OPT_SW_RD_WR_POS_TRAINING == FALSE
1137 #error No Rd Wr position training option has been selected
1138 #endif
1139#endif
1140// Ensure at least one dram init option has been selected
1141#if OPTION_HW_DRAM_INIT == FALSE
1142 #if OPTION_SW_DRAM_INIT == FALSE
1143 #error No Dram init option has been selected
1144 #endif
1145#endif
1146// Ensure the frequency limit is valid
1147#if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1866_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 933)
1148 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1600_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 800)
1149 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1333_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 667)
1150 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1066_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 533)
1151 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR800_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 400)
1152 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR667_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 333)
1153 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR533_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 266)
1154 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR400_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 200)
1155 #error BLDCFG: Unsupported memory bus frequency
1156 #endif
1157 #endif
1158 #endif
1159 #endif
1160 #endif
1161 #endif
1162 #endif
1163#endif
1164// Ensure timing mode is valid
1165#if CFG_TIMING_MODE_SELECT != TIMING_MODE_SPECIFIC
1166 #if CFG_TIMING_MODE_SELECT != TIMING_MODE_LIMITED
1167 #if CFG_TIMING_MODE_SELECT != TIMING_MODE_AUTO
1168 #error BLDCFG: Invalid timing mode is set
1169 #endif
1170 #endif
1171#endif
1172// Ensure the scrub rate is valid
1173#if ((CFG_SCRUB_DRAM_RATE > 0x16) && (CFG_SCRUB_DRAM_RATE != 0xFF))
1174 #error BLDCFG: Unsupported dram scrub rate set
1175#endif
1176#if CFG_SCRUB_L2_RATE > 0x16
1177 #error BLDCFG: Unsupported L2 scrubber rate set
1178#endif
1179#if CFG_SCRUB_L3_RATE > 0x16
1180 #error BLDCFG: unsupported L3 scrubber rate set
1181#endif
1182#if CFG_SCRUB_IC_RATE > 0x16
1183 #error BLDCFG: Unsupported Instruction cache scrub rate set
1184#endif
1185#if CFG_SCRUB_DC_RATE > 0x16
1186 #error BLDCFG: Unsupported Dcache scrub rate set
1187#endif
1188// Ensure Quad rank dimm type is valid
1189#if CFG_MEMORY_QUADRANK_TYPE != QUADRANK_UNBUFFERED
1190 #if CFG_MEMORY_QUADRANK_TYPE != QUADRANK_REGISTERED
1191 #error BLDCFG: Invalid quad rank dimm type set
1192 #endif
1193#endif
1194// Ensure ECC symbol size is valid
1195#if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_USE_BKDG
1196 #if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_FORCE_X4
1197 #if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_FORCE_X8
1198 #error BLDCFG: Invalid Ecc symbol size set
1199 #endif
1200 #endif
1201#endif
1202// Ensure power down mode is valid
1203#if CFG_POWER_DOWN_MODE != POWER_DOWN_BY_CHIP_SELECT
1204 #if CFG_POWER_DOWN_MODE != POWER_DOWN_BY_CHANNEL
1205 #error BLDCFG: Invalid power down mode set
1206 #endif
1207#endif
1208
1209/*****************************************************************************
1210 *
1211 * Process the option logic, setting local control variables
1212 *
1213 ****************************************************************************/
1214#if OPTION_ACPI_PSTATES == TRUE
1215 #define OPTFCN_ACPI_TABLES CreateAcpiTablesMain
1216 #define OPTFCN_GATHER_DATA PStateGatherData
1217 #if OPTION_MULTISOCKET == TRUE
1218 #define OPTFCN_PSTATE_LEVELING PStateLeveling
1219 #else
1220 #define OPTFCN_PSTATE_LEVELING CommonReturnAgesaSuccess
1221 #endif
1222#else
1223 #define OPTFCN_ACPI_TABLES CommonReturnAgesaSuccess
1224 #define OPTFCN_GATHER_DATA CommonReturnAgesaSuccess
1225 #define OPTFCN_PSTATE_LEVELING CommonReturnAgesaSuccess
1226#endif
1227
1228
1229/*****************************************************************************
1230 *
1231 * Include the structure definitions for the defaults table structures
1232 *
1233 ****************************************************************************/
Kyösti Mälkki062ef1c2016-04-19 15:18:02 +0300[diff] [blame]1234#include <CommonReturns.h>
1235#include <agesa-entry-cfg.h>
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]1236#include "Options.h"
1237#include "OptionCpuFamiliesInstall.h"
1238#include "OptionsHt.h"
1239#include "OptionHtInstall.h"
1240#include "OptionMemory.h"
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]1241#include "OptionMemoryInstall.h"
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]1242#include "OptionCpuFeaturesInstall.h"
1243#include "OptionDmi.h"
1244#include "OptionDmiInstall.h"
1245#include "OptionPstate.h"
1246#include "OptionPstateInstall.h"
1247#include "OptionWhea.h"
1248#include "OptionWheaInstall.h"
1249#include "OptionSrat.h"
1250#include "OptionSratInstall.h"
1251#include "OptionSlit.h"
1252#include "OptionSlitInstall.h"
1253#include "OptionMultiSocket.h"
1254#include "OptionMultiSocketInstall.h"
1255#include "OptionIdsInstall.h"
1256#include "OptionGfxRecovery.h"
1257#include "OptionGfxRecoveryInstall.h"
1258#include "OptionGnb.h"
1259#include "OptionGnbInstall.h"
1260#include "OptionS3ScriptInstall.h"
1261
1262
1263/*****************************************************************************
1264 *
1265 * Generate the output structures (defaults tables)
1266 *
1267 ****************************************************************************/
1268BUILD_OPT_CFG UserOptions = {
1269 { // AGESA version string
1270 AGESA_CODE_SIGNATURE, // code header Signature
1271 AGESA_PACKAGE_STRING, // 8 character ID
1272 AGESA_VERSION_STRING, // 12 character version string
1273 0 // null string terminator
1274 },
1275 //Build Option Area
1276 OPTION_UDIMMS, //UDIMMS
1277 OPTION_RDIMMS, //RDIMMS
1278 OPTION_LRDIMMS, //LRDIMMS
1279 OPTION_ECC, //ECC
1280 OPTION_BANK_INTERLEAVE, //BANK_INTERLEAVE
1281 OPTION_DCT_INTERLEAVE, //DCT_INTERLEAVE
1282 OPTION_NODE_INTERLEAVE, //NODE_INTERLEAVE
1283 OPTION_PARALLEL_TRAINING, //PARALLEL_TRAINING
1284 OPTION_ONLINE_SPARE, //ONLINE_SPARE
1285 OPTION_MEM_RESTORE, //MEM CONTEXT RESTORE
1286 OPTION_MULTISOCKET, //MULTISOCKET
1287 OPTION_ACPI_PSTATES, //ACPI_PSTATES
1288 OPTION_SRAT, //SRAT
1289 OPTION_SLIT, //SLIT
1290 OPTION_WHEA, //WHEA
1291 OPTION_DMI, //DMI
1292 OPTION_EARLY_SAMPLES, //EARLY_SAMPLES
1293 OPTION_ADDR_TO_CS_TRANSLATOR, //ADDR_TO_CS_TRANSLATOR
1294
1295 //Build Configuration Area
1296 CFG_PCI_MMIO_BASE,
1297 CFG_PCI_MMIO_SIZE,
1298 {
1299 // CoreVrm
1300 {
1301 CFG_VRM_CURRENT_LIMIT, // VrmCurrentLimit
1302 CFG_VRM_LOW_POWER_THRESHOLD, // VrmLowPowerThershold
1303 CFG_VRM_SLEW_RATE, // VrmSlewRate
1304 CFG_VRM_ADDITIONAL_DELAY, // VrmAdditionalDelay
1305 CFG_VRM_HIGH_SPEED_ENABLE, // VrmHiSpeedEnable
1306 CFG_VRM_INRUSH_CURRENT_LIMIT // VrmInrushCurrentLimit
1307 },
1308 // NbVrm
1309 {
1310 CFG_VRM_NB_CURRENT_LIMIT, // VrmNbCurrentLimit
1311 CFG_VRM_NB_LOW_POWER_THRESHOLD, // VrmNbLowPowerThershold
1312 CFG_VRM_NB_SLEW_RATE, // VrmNbSlewRate
1313 CFG_VRM_NB_ADDITIONAL_DELAY, // VrmNbAdditionalDelay
1314 CFG_VRM_NB_HIGH_SPEED_ENABLE, // VrmNbHiSpeedEnable
1315 CFG_VRM_NB_INRUSH_CURRENT_LIMIT // VrmNbInrushCurrentLimit
1316 }
1317 },
1318 CFG_PLAT_NUM_IO_APICS, //PlatformApicIoNumber
1319 CFG_MEM_INIT_PSTATE, //MemoryInitPstate
1320 CFG_C1E_MODE, //C1eMode
1321 CFG_C1E_OPDATA, //C1ePlatformData
1322 CFG_C1E_OPDATA1, //C1ePlatformData1
1323 CFG_C1E_OPDATA2, //C1ePlatformData2
1324 CFG_CSTATE_MODE, //CStateMode
1325 CFG_CSTATE_OPDATA, //CStatePlatformData
1326 CFG_CSTATE_IO_BASE_ADDRESS, //CStateIoBaseAddress
1327 CFG_CPB_MODE, //CpbMode
1328 CFG_CORE_LEVELING_MODE, //CoreLevelingCofig
1329 {
1330 CFG_PLATFORM_CONTROL_FLOW_MODE, // The platform's control flow mode.
1331 CFG_USE_HT_ASSIST, // CfgUseHtAssist
1332 CFG_USE_ATM_MODE, // CfgUseAtmMode
1333 CFG_USE_32_BYTE_REFRESH, // Display Refresh uses 32 byte packets.
1334 CFG_USE_VARIABLE_MCT_ISOC_PRIORITY, // The Memory controller will be set to Variable Isoc Priority.
1335 CFG_PLATFORM_POWER_POLICY_MODE // The platform's power policy mode.
1336 },
1337 (CPU_HT_DEEMPHASIS_LEVEL *)CFG_PLATFORM_DEEMPHASIS_LIST, // Deemphasis settings
1338 CFG_AMD_PLATFORM_TYPE, //AmdPlatformType
1339 CFG_AMD_PSTATE_CAP_VALUE, // Amd pstate ceiling enabling deck
1340
1341 CFG_MEMORY_BUS_FREQUENCY_LIMIT, // CfgMemoryBusFrequencyLimit
1342 CFG_MEMORY_MODE_UNGANGED, // CfgMemoryModeUnganged
1343 CFG_MEMORY_QUAD_RANK_CAPABLE, // CfgMemoryQuadRankCapable
1344 CFG_MEMORY_QUADRANK_TYPE, // CfgMemoryQuadrankType
1345 CFG_MEMORY_RDIMM_CAPABLE, // CfgMemoryRDimmCapable
1346 CFG_MEMORY_LRDIMM_CAPABLE, // CfgMemoryLRDimmCapable
1347 CFG_MEMORY_UDIMM_CAPABLE, // CfgMemoryUDimmCapable
1348 CFG_MEMORY_SODIMM_CAPABLE, // CfgMemorySodimmCapable
1349 CFG_MEMORY_ENABLE_BANK_INTERLEAVING, // CfgMemoryEnableBankInterleaving
1350 CFG_MEMORY_ENABLE_NODE_INTERLEAVING, // CfgMemoryEnableNodeInterleaving
1351 CFG_MEMORY_CHANNEL_INTERLEAVING, // CfgMemoryChannelInterleaving
1352 CFG_MEMORY_POWER_DOWN, // CfgMemoryPowerDown
1353 CFG_POWER_DOWN_MODE, // CfgPowerDownMode
1354 CFG_ONLINE_SPARE, // CfgOnlineSpare
1355 CFG_MEMORY_PARITY_ENABLE, // CfgMemoryParityEnable
1356 CFG_BANK_SWIZZLE, // CfgBankSwizzle
1357 CFG_TIMING_MODE_SELECT, // CfgTimingModeSelect
1358 CFG_MEMORY_CLOCK_SELECT, // CfgMemoryClockSelect
1359 CFG_DQS_TRAINING_CONTROL, // CfgDqsTrainingControl
1360 CFG_IGNORE_SPD_CHECKSUM, // CfgIgnoreSpdChecksum
1361 CFG_USE_BURST_MODE, // CfgUseBurstMode
1362 CFG_MEMORY_ALL_CLOCKS_ON, // CfgMemoryAllClocksOn
1363 CFG_ENABLE_ECC_FEATURE, // CfgEnableEccFeature
1364 CFG_ECC_REDIRECTION, // CfgEccRedirection
1365 CFG_SCRUB_DRAM_RATE, // CfgScrubDramRate
1366 CFG_SCRUB_L2_RATE, // CfgScrubL2Rate
1367 CFG_SCRUB_L3_RATE, // CfgScrubL3Rate
1368 CFG_SCRUB_IC_RATE, // CfgScrubIcRate
1369 CFG_SCRUB_DC_RATE, // CfgScrubDcRate
1370 CFG_ECC_SYNC_FLOOD, // CfgEccSyncFlood
1371 CFG_ECC_SYMBOL_SIZE, // CfgEccSymbolSize
1372 CFG_HEAP_DRAM_ADDRESS, // CfgHeapDramAddress
1373 CFG_1GB_ALIGN, // CfgNodeMem1GBAlign
1374 CFG_S3_LATE_RESTORE, // CfgS3LateRestore
1375 CFG_ACPI_PSTATE_PSD_INDPX, // CfgAcpiPstateIndependent
1376 (AP_MTRR_SETTINGS *) CFG_AP_MTRR_SETTINGS_LIST, // CfgApMtrrSettingsList
1377 CFG_UMA_MODE, // CfgUmaMode
1378 CFG_UMA_SIZE, // CfgUmaSize
1379 CFG_UMA_ABOVE4G, // CfgUmaAbove4G
1380 CFG_UMA_ALIGNMENT, // CfgUmaAlignment
1381 CFG_PROCESSOR_SCOPE_IN_SB, // CfgProcessorScopeInSb
1382 CFG_PROCESSOR_SCOPE_NAME0, // CfgProcessorScopeName0
1383 CFG_PROCESSOR_SCOPE_NAME1, // CfgProcessorScopeName1
1384 CFG_GNB_HD_AUDIO, // CfgGnbHdAudio
1385 CFG_ABM_SUPPORT, // CfgAbmSupport
1386 CFG_DYNAMIC_REFRESH_RATE, // CfgDynamicRefreshRate
1387 CFG_LCD_BACK_LIGHT_CONTROL, // CfgLcdBackLightControl
1388 CFG_GNB_STEREO_3D_PINOUT, // CfgGnb3dStereoPinIndex
1389 CFG_TEMP_PCIE_MMIO_BASE_ADDRESS, // CfgTempPcieMmioBaseAddress
1390 CFG_GNB_IGPU_SSID, // CfgGnbIGPUSSID
1391 CFG_GNB_HDAUDIO_SSID, // CfgGnbHDAudioSSID
1392 CFG_GNB_PCIE_SSID, // CfgGnbPcieSSID
1393 CFG_GFX_LVDS_SPREAD_SPECTRUM, // CfgLvdsSpreadSpectrum
1394 CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE, // CfgLvdsSpreadSpectrumRate
1395
efdesign9884cbce22011-08-04 12:09:17 -0600[diff] [blame]1396 {{
1397 CFG_LVDS_MISC_888_FPDI_MODE, // CfgLvdsMiscControl
1398 CFG_LVDS_MISC_DL_CH_SWAP, // CfgLvdsMiscControl
1399 CFG_LVDS_MISC_VSYNC_ACTIVE_LOW, // CfgLvdsMiscControl
1400 CFG_LVDS_MISC_HSYNC_ACTIVE_LOW, // CfgLvdsMiscControl
1401 CFG_LVDS_MISC_BLON_ACTIVE_LOW, // CfgLvdsMiscControl
1402 }},
1403 CFG_PCIE_REFCLK_SPREAD_SPECTRUM, // CfgPcieRefClkSpreadSpectrum
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]1404 0, //reserved...
1405};
1406
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]1407
1408CONST DISPATCH_TABLE ROMDATA ApDispatchTable[] =
1409{
1410 IDS_LATE_RUN_AP_TASK
1411 // Get DMI info
1412 CPU_DMI_AP_GET_TYPE4_TYPE7
1413 // Probe filter enable
1414 HT_ASSIST_AP_DISABLE_CACHE
1415 HT_ASSIST_AP_ENABLE_CACHE
1416
1417 { 0, NULL }
1418};
1419
1420#if AGESA_ENTRY_INIT_RESET == TRUE
1421 #if IDSOPT_IDS_ENABLED == TRUE
1422 #if IDSOPT_TRACING_ENABLED == TRUE
1423 #define MAKE_DBG_STR(x, y) MAKE_AS_A_STRING(x : y)
1424 CONST CHAR8 *BldOptDebugOutput[] = {
1425 #if IDS_TRACE_SHOW_BLD_OPT_CFG == TRUE
1426 //Build Option Area
1427 MAKE_DBG_STR (\nOptUDIMM, OPTION_UDIMMS)
1428 MAKE_DBG_STR (\nOptRDIMM, OPTION_RDIMMS)
1429 MAKE_DBG_STR (\nOptLRDIMM, OPTION_LRDIMMS)
1430 MAKE_DBG_STR (\nOptECC, OPTION_ECC)
1431 MAKE_DBG_STR (\nOptCsIntlv, OPTION_BANK_INTERLEAVE)
1432 MAKE_DBG_STR (\nOptDctIntlv, OPTION_DCT_INTERLEAVE)
1433 MAKE_DBG_STR (\nOptNodeIntlv, OPTION_NODE_INTERLEAVE)
1434 //MAKE_DBG_STR (\nOptParallelTraining, OPTION_PARALLEL_TRAINING)
1435 MAKE_DBG_STR (\nOptOnlineSpare, OPTION_ONLINE_SPARE)
1436 MAKE_DBG_STR (\nOptAddr2CsTranslator, OPTION_ADDR_TO_CS_TRANSLATOR)
1437 MAKE_DBG_STR (\nOptMemRestore, OPTION_MEM_RESTORE)
1438 MAKE_DBG_STR (\nOptMultiSocket, OPTION_MULTISOCKET)
1439 MAKE_DBG_STR (\nOptPstates, OPTION_ACPI_PSTATES)
1440 MAKE_DBG_STR (\nOptSRAT, OPTION_SRAT)
1441 MAKE_DBG_STR (\nOptSLIT, OPTION_SLIT)
1442 MAKE_DBG_STR (\nOptWHEA, OPTION_WHEA)
1443 MAKE_DBG_STR (\nOptDMI, OPTION_DMI)
1444 MAKE_DBG_STR (\nOptEarlySamples, OPTION_EARLY_SAMPLES),
1445
1446 //Build Configuration Area
1447 // CoreVrm
1448 MAKE_DBG_STR (\nVrmCurrentLimit , CFG_VRM_CURRENT_LIMIT)
1449 MAKE_DBG_STR (\nVrmLowPowerThreshold , CFG_VRM_LOW_POWER_THRESHOLD)
1450 MAKE_DBG_STR (\nVrmSlewRate , CFG_VRM_SLEW_RATE)
1451 MAKE_DBG_STR (\nVrmAdditionalDelay , CFG_VRM_ADDITIONAL_DELAY)
1452 MAKE_DBG_STR (\nVrmHiSpeedEnable , CFG_VRM_HIGH_SPEED_ENABLE)
1453 MAKE_DBG_STR (\nVrmInrushCurrentLimit, CFG_VRM_INRUSH_CURRENT_LIMIT)
1454 // NbVrm
1455 MAKE_DBG_STR (\nNbVrmCurrentLimit , CFG_VRM_NB_CURRENT_LIMIT)
1456 MAKE_DBG_STR (\nNbVrmLowPowerThreshold , CFG_VRM_NB_LOW_POWER_THRESHOLD)
1457 MAKE_DBG_STR (\nNbVrmSlewRate , CFG_VRM_NB_SLEW_RATE)
1458 MAKE_DBG_STR (\nNbVrmAdditionalDelay , CFG_VRM_NB_ADDITIONAL_DELAY)
1459 MAKE_DBG_STR (\nNbVrmHiSpeedEnable , CFG_VRM_NB_HIGH_SPEED_ENABLE)
1460 MAKE_DBG_STR (\nNbVrmInrushCurrentLimit, CFG_VRM_NB_INRUSH_CURRENT_LIMIT),
1461
1462 MAKE_DBG_STR (\nNumIoApics , CFG_PLAT_NUM_IO_APICS)
1463 MAKE_DBG_STR (\nMemInitPstate , CFG_MEM_INIT_PSTATE)
1464 MAKE_DBG_STR (\nC1eMode , CFG_C1E_MODE)
1465 MAKE_DBG_STR (\nC1eOpData , CFG_C1E_OPDATA)
1466 MAKE_DBG_STR (\nC1eOpdata1 , CFG_C1E_OPDATA1)
1467 MAKE_DBG_STR (\nC1eOpdata2 , CFG_C1E_OPDATA2)
1468 MAKE_DBG_STR (\nCStateMode , CFG_CSTATE_MODE)
1469 MAKE_DBG_STR (\nCStateOpData , CFG_CSTATE_OPDATA)
1470 MAKE_DBG_STR (\nCStateIoBaseAddr , CFG_CSTATE_IO_BASE_ADDRESS)
1471 MAKE_DBG_STR (\nCpbMode , CFG_CPB_MODE)
1472 MAKE_DBG_STR (\nCoreLevelingMode , CFG_CORE_LEVELING_MODE),
1473
1474 MAKE_DBG_STR (\nControlFlowMode , CFG_PLATFORM_CONTROL_FLOW_MODE)
1475 MAKE_DBG_STR (\nUseHtAssist , CFG_USE_HT_ASSIST)
1476 MAKE_DBG_STR (\nUseAtmMode , CFG_USE_ATM_MODE)
1477 MAKE_DBG_STR (\nUse32ByteRefresh , CFG_USE_32_BYTE_REFRESH)
1478 MAKE_DBG_STR (\nUseVarMctIsocPriority , CFG_USE_VARIABLE_MCT_ISOC_PRIORITY)
1479 MAKE_DBG_STR (\nPowerPolicy , CFG_PLATFORM_POWER_POLICY_MOD)
1480
1481 MAKE_DBG_STR (\nDeemphasisList , CFG_PLATFORM_DEEMPHASIS_LIST)
1482
1483 MAKE_DBG_STR (\nPciMmioAddr , CFG_PCI_MMIO_BASE)
1484 MAKE_DBG_STR (\nPciMmioSize , CFG_PCI_MMIO_SIZE)
1485 MAKE_DBG_STR (\nPlatformType , CFG_AMD_PLATFORM_TYPE)
1486 MAKE_DBG_STR (\nPstateCapValue , CFG_AMD_PSTATE_CAP_VALUE),
1487
1488 MAKE_DBG_STR (\nMemBusFreqLimit , CFG_MEMORY_BUS_FREQUENCY_LIMIT)
1489 MAKE_DBG_STR (\nTimingModeSelect , CFG_TIMING_MODE_SELECT)
1490 MAKE_DBG_STR (\nMemoryClockSelect , CFG_MEMORY_CLOCK_SELECT)
1491
1492 MAKE_DBG_STR (\nMemUnganged , CFG_MEMORY_MODE_UNGANGED)
1493 MAKE_DBG_STR (\nQRCap , CFG_MEMORY_QUAD_RANK_CAPABLE)
1494 MAKE_DBG_STR (\nQRType , CFG_MEMORY_QUADRANK_TYPE)
1495 MAKE_DBG_STR (\nRDimmCap , CFG_MEMORY_RDIMM_CAPABLE)
1496 MAKE_DBG_STR (\nLRDimmCap , CFG_MEMORY_LRDIMM_CAPABLE)
1497 MAKE_DBG_STR (\nUDimmCap , CFG_MEMORY_UDIMM_CAPABLE)
1498 MAKE_DBG_STR (\nSODimmCap , CFG_MEMORY_SODIMM_CAPABLE)
1499 MAKE_DBG_STR (\nDqsTrainingControl , CFG_DQS_TRAINING_CONTROL)
1500 MAKE_DBG_STR (\nIgnoreSpdChecksum , CFG_IGNORE_SPD_CHECKSUM)
1501 MAKE_DBG_STR (\nUseBurstMode , CFG_USE_BURST_MODE)
1502 MAKE_DBG_STR (\nAllMemClkOn , CFG_MEMORY_ALL_CLOCKS_ON),
1503
1504 MAKE_DBG_STR (\nPowerDownEn , CFG_MEMORY_POWER_DOWN)
1505 MAKE_DBG_STR (\nPowerDownMode , CFG_POWER_DOWN_MODE)
1506 MAKE_DBG_STR (\nOnlineSpare , CFG_ONLINE_SPARE)
1507 MAKE_DBG_STR (\nAddrParityEn , CFG_MEMORY_PARITY_ENABLE)
1508 MAKE_DBG_STR (\nBankSwizzle , CFG_BANK_SWIZZLE)
1509 MAKE_DBG_STR (\nCsIntlvEn , CFG_MEMORY_ENABLE_BANK_INTERLEAVING)
1510 MAKE_DBG_STR (\nNodeIntlvEn , CFG_MEMORY_ENABLE_NODE_INTERLEAVING)
1511 MAKE_DBG_STR (\nDctIntlvEn , CFG_MEMORY_CHANNEL_INTERLEAVING),
1512
1513 MAKE_DBG_STR (\nUmaMode , CFG_UMA_MODE)
1514 MAKE_DBG_STR (\nUmaSize , CFG_UMA_SIZE)
1515 MAKE_DBG_STR (\nUmaAbove4G , CFG_UMA_ABOVE4G)
1516 MAKE_DBG_STR (\nUmaAlignment , CFG_UMA_ALIGNMENT)
1517
1518 MAKE_DBG_STR (\nEccEn , CFG_ENABLE_ECC_FEATURE)
1519 MAKE_DBG_STR (\nEccRedirect , CFG_ECC_REDIRECTION)
1520 MAKE_DBG_STR (\nScrubDramRate , CFG_SCRUB_DRAM_RATE)
1521 MAKE_DBG_STR (\nScrubL2Rate , CFG_SCRUB_L2_RATE)
1522 MAKE_DBG_STR (\nScrubL3Rate , CFG_SCRUB_L3_RATE)
1523 MAKE_DBG_STR (\nScrubIcRate , CFG_SCRUB_IC_RATE)
1524 MAKE_DBG_STR (\nScrubDcRate , CFG_SCRUB_DC_RATE)
1525 MAKE_DBG_STR (\nEccSyncFlood , CFG_ECC_SYNC_FLOOD)
1526 MAKE_DBG_STR (\nEccSymbolSize , CFG_ECC_SYMBOL_SIZE)
1527 MAKE_DBG_STR (\nHeapDramAddress , CFG_HEAP_DRAM_ADDRESS)
1528 MAKE_DBG_STR (\nNodeMem1GBAlign , CFG_1GB_ALIGN),
1529
1530 MAKE_DBG_STR (\nS3LateRestore , CFG_S3_LATE_RESTORE)
1531 MAKE_DBG_STR (\nAcpiPstateIndependent , CFG_ACPI_PSTATE_PSD_INDPX)
1532
1533 MAKE_DBG_STR (\nApMtrrSettingsList , CFG_AP_MTRR_SETTINGS_LIST)
1534
1535 MAKE_DBG_STR (\nProcessorScopeInSb , CFG_PROCESSOR_SCOPE_IN_SB)
1536 MAKE_DBG_STR (\nProcessorScopeName0 , CFG_PROCESSOR_SCOPE_NAME0)
1537 MAKE_DBG_STR (\nProcessorScopeName1 , CFG_PROCESSOR_SCOPE_NAME1)
1538 MAKE_DBG_STR (\nGnbHdAudio , CFG_GNB_HD_AUDIO)
1539 MAKE_DBG_STR (\nAbmSupport , CFG_ABM_SUPPORT)
1540 MAKE_DBG_STR (\nDynamicRefreshRate , CFG_DYNAMIC_REFRESH_RATE)
1541 MAKE_DBG_STR (\nLcdBackLightControl , CFG_LCD_BACK_LIGHT_CONTROL)
1542 MAKE_DBG_STR (\nGnb3dStereoPinIndex , CFG_GNB_STEREO_3D_PINOUT)
1543 MAKE_DBG_STR (\nTempPcieMmioBaseAddress, CFG_TEMP_PCIE_MMIO_BASE_ADDRESS),
1544 MAKE_DBG_STR (\nCfgGnbIGPUSSID , CFG_GNB_IGPU_SSID),
1545 MAKE_DBG_STR (\nCfgGnbHDAudioSSID , CFG_GNB_HDAUDIO_SSID),
1546 MAKE_DBG_STR (\nCfgGnbPcieSSID , CFG_GNB_PCIE_SSID),
1547
1548 MAKE_DBG_STR (\nCfgLvdsSpreadSpectrum , CFG_GFX_LVDS_SPREAD_SPECTRUM),
1549 MAKE_DBG_STR (\nCfgLvdsSpreadSpectrumRate , CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE),
efdesign9884cbce22011-08-04 12:09:17 -0600[diff] [blame]1550 MAKE_DBG_STR (\nCfgLvdsMiscControl.FpdiMode , CFG_LVDS_MISC_888_FPDI_MODE),
1551 MAKE_DBG_STR (\nCfgLvdsMiscControl.DlChSwap , CFG_LVDS_MISC_DL_CH_SWAP),
1552 MAKE_DBG_STR (\nCfgLvdsMiscControl.VsyncActiveLow , CFG_LVDS_MISC_VSYNC_ACTIVE_LOW),
1553 MAKE_DBG_STR (\nCfgLvdsMiscControl.HsyncActiveLow , CFG_LVDS_MISC_HSYNC_ACTIVE_LOW),
1554 MAKE_DBG_STR (\nCfgLvdsMiscControl.BLONActiveLow , CFG_LVDS_MISC_BLON_ACTIVE_LOW),
1555 MAKE_DBG_STR (\nCfgPcieRefClkSpreadSpectrum , CFG_PCIE_REFCLK_SPREAD_SPECTRUM),
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]1556 #endif
1557 NULL
1558 };
1559 #endif
1560 #endif
1561#endif