blob: a958570905a2194dcd38666fe488356e3c79032e [file] [log] [blame]
Angel Ponsae593872020-04-04 18:50:57 +02001/* SPDX-License-Identifier: GPL-2.0-only */
Martin Roth5c354b92019-04-22 14:55:16 -06002
Felix Heldc79c64b2023-06-01 21:52:05 +02003#include <soc/amd/common/acpi/pci_root.asl>
4
5ROOT_BRIDGE(PCI0)
6
7Scope(PCI0) {
Martin Roth5c354b92019-04-22 14:55:16 -06008 /* Describe the AMD Northbridge */
9 #include "northbridge.asl"
10
11 /* Describe the AMD Fusion Controller Hub */
Felix Held78381092023-06-01 21:56:39 +020012 #include <soc/amd/common/acpi/lpc.asl>
13 #include <soc/amd/common/acpi/platform.asl>
Martin Roth5c354b92019-04-22 14:55:16 -060014}
15
Felix Held753827e2022-11-03 23:05:03 +010016/* PCI IRQ mapping for the Southbridge */
17#include "pci_int_defs.asl"
18
Martin Roth5c354b92019-04-22 14:55:16 -060019/* Describe PCI INT[A-H] for the Southbridge */
Raul E Rangelafe1fe52021-05-04 16:48:25 -060020#include <soc/amd/common/acpi/pci_int.asl>
Martin Roth5c354b92019-04-22 14:55:16 -060021
Felix Held4d6c39d2023-06-01 23:03:13 +020022/* Describe the MMIO devices in the FCH */
23#include "mmio.asl"
Martin Roth5c354b92019-04-22 14:55:16 -060024
25/* Add GPIO library */
26#include <soc/amd/common/acpi/gpio_bank_lib.asl>
Tim Van Patten92443582022-08-23 16:06:33 -060027
Tim Van Patten9b3112c2022-09-13 10:08:49 -060028#if CONFIG(SOC_AMD_COMMON_BLOCK_ACPI_DPTC)
Tim Van Patten92443582022-08-23 16:06:33 -060029#include <soc/amd/common/acpi/dptc.asl>
Tim Van Patten9b3112c2022-09-13 10:08:49 -060030#endif