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Duncan Lauriec88c54c2014-04-30 16:36:13 -07001config SOC_INTEL_BROADWELL
2 bool
3 help
4 Intel Broadwell and Haswell ULT support.
5
6if SOC_INTEL_BROADWELL
7
Angel Ponsa3288b32020-11-23 13:00:51 +01008config SOC_SPECIFIC_OPTIONS
Duncan Lauriec88c54c2014-04-30 16:36:13 -07009 def_bool y
Duncan Lauriec88c54c2014-04-30 16:36:13 -070010 select CACHE_MRC_SETTINGS
Angel Pons3f0a95a2020-11-23 13:34:56 +010011 select CPU_INTEL_HASWELL
Matt DeVillier773488f2017-10-18 12:27:25 -050012 select INTEL_GMA_ACPI
Angel Ponsdbdd5282021-06-14 12:14:48 +020013 select MRC_SETTINGS_PROTECT
14 select REG_SCRIPT
Kyösti Mälkkie8a3af12022-11-19 18:39:22 +020015 select TCO_SPACE_NOT_YET_SPLIT
Youness Alaouib191c9f2017-05-08 15:22:03 -040016
Angel Pons865c97c2021-06-23 16:51:16 +020017config BROADWELL_LPDDR3
18 bool
19 help
20 Selected by mainboards using LPDDR3 DRAM to supply mainboard-specific
21 LPDDR3 DQ and DQS CPU-to-DRAM mapping info needed to perform raminit.
22
Yu-Ping Wu35835de2022-08-01 02:54:10 +000023config VBOOT
24 select VBOOT_MUST_REQUEST_DISPLAY
Yu-Ping Wu478c71e2022-08-16 11:22:29 +080025 select VBOOT_STARTS_IN_BOOTBLOCK
Yu-Ping Wu35835de2022-08-01 02:54:10 +000026
Shelley Chen4e9bb332021-10-20 15:43:45 -070027config ECAM_MMCONF_BASE_ADDRESS
Duncan Lauriec88c54c2014-04-30 16:36:13 -070028 default 0xf0000000
29
Shelley Chen4e9bb332021-10-20 15:43:45 -070030config ECAM_MMCONF_BUS_NUMBER
Angel Pons9debbd62021-01-28 12:42:53 +010031 default 64
32
Duncan Lauriec88c54c2014-04-30 16:36:13 -070033config VGA_BIOS_ID
34 string
35 default "8086,0406"
36
Angel Ponsc715dc82021-01-31 00:33:04 +010037config FIXED_MCHBAR_MMIO_BASE
38 default 0xfed10000
39
40config FIXED_DMIBAR_MMIO_BASE
41 default 0xfed18000
42
43config FIXED_EPBAR_MMIO_BASE
44 default 0xfed19000
45
Duncan Lauriec88c54c2014-04-30 16:36:13 -070046config DCACHE_RAM_BASE
47 hex
48 default 0xff7c0000
49
50config DCACHE_RAM_SIZE
51 hex
52 default 0x10000
53 help
54 The size of the cache-as-ram region required during bootblock
55 and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE
56 must add up to a power of 2.
57
58config DCACHE_RAM_MRC_VAR_SIZE
59 hex
60 default 0x30000
61 help
62 The amount of cache-as-ram region required by the reference code.
63
Arthur Heymans5bb15f12018-12-22 16:02:25 +010064config DCACHE_BSP_STACK_SIZE
65 hex
66 default 0x2000
67 help
68 The amount of anticipated stack usage in CAR by bootblock and
69 other stages.
70
Duncan Lauriec88c54c2014-04-30 16:36:13 -070071config HAVE_MRC
72 bool "Add a Memory Reference Code binary"
73 help
74 Select this option to add a Memory Reference Code binary to
75 the resulting coreboot image.
76
77 Note: Without this binary coreboot will not work
78
79if HAVE_MRC
80
81config MRC_FILE
82 string "Intel Memory Reference Code path and filename"
83 depends on HAVE_MRC
84 default "mrc.bin"
85 help
86 The filename of the file to use as Memory Reference Code binary.
87
88config MRC_BIN_ADDRESS
89 hex
90 default 0xfffa0000
91
Yu-Ping Wu35835de2022-08-01 02:54:10 +000092# The UEFI System Agent binary needs to be at a fixed offset in the flash
93# and can therefore only reside in the COREBOOT fmap region
94config RO_REGION_ONLY
95 string
96 depends on VBOOT
97 default "mrc.bin"
98
Duncan Lauriec88c54c2014-04-30 16:36:13 -070099endif # HAVE_MRC
100
Patrick Georgie6e94932015-06-22 22:26:45 +0200101config HAVE_REFCODE_BLOB
102 depends on ARCH_X86
103 bool "An external reference code blob should be put into cbfs."
104 default n
105 help
106 The reference code blob will be placed into cbfs.
107
108if HAVE_REFCODE_BLOB
109
110config REFCODE_BLOB_FILE
111 string "Path and filename to reference code blob."
112 default "refcode.elf"
113 help
114 The path and filename to the file to be added to cbfs.
115
116endif # HAVE_REFCODE_BLOB
117
Angel Ponsdbdd5282021-06-14 12:14:48 +0200118source "src/soc/intel/broadwell/pch/Kconfig"
119
Duncan Lauriec88c54c2014-04-30 16:36:13 -0700120endif