Patrick Georgi | c49d7a3 | 2020-05-08 22:50:46 +0200 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0-only |
Lee Leahy | 47bd2d9 | 2016-07-24 18:12:16 -0700 | [diff] [blame] | 2 | |
Andrey Petrov | b37fd67 | 2016-03-01 16:25:38 -0800 | [diff] [blame] | 3 | config PLATFORM_USES_FSP2_0 |
| 4 | bool |
Subrata Banik | 7455881 | 2018-01-25 11:41:04 +0530 | [diff] [blame] | 5 | default n |
Andrey Petrov | b37fd67 | 2016-03-01 16:25:38 -0800 | [diff] [blame] | 6 | help |
| 7 | Include FSP 2.0 wrappers and functionality |
| 8 | |
Subrata Banik | 8a83282 | 2018-12-19 16:46:37 +0530 | [diff] [blame] | 9 | config PLATFORM_USES_FSP2_1 |
| 10 | bool |
| 11 | default n |
| 12 | select PLATFORM_USES_FSP2_0 |
| 13 | select FSP_USES_CB_STACK |
Subrata Banik | 8a83282 | 2018-12-19 16:46:37 +0530 | [diff] [blame] | 14 | help |
| 15 | Include FSP 2.1 wrappers and functionality. |
Jonathan Zhang | 01e3855 | 2020-06-17 16:03:18 -0700 | [diff] [blame] | 16 | Feature added into FSP 2.1 specification that impacts coreboot is: |
Subrata Banik | 8a83282 | 2018-12-19 16:46:37 +0530 | [diff] [blame] | 17 | 1. Remove FSP stack switch and use the same stack with boot firmware |
Subrata Banik | 8a83282 | 2018-12-19 16:46:37 +0530 | [diff] [blame] | 18 | |
Subrata Banik | 33d9c4a | 2020-05-26 18:26:54 +0530 | [diff] [blame] | 19 | config PLATFORM_USES_FSP2_2 |
| 20 | bool |
| 21 | default n |
| 22 | select PLATFORM_USES_FSP2_1 |
| 23 | help |
| 24 | Include FSP 2.2 wrappers and functionality. |
| 25 | Features added into FSP 2.2 specification that impact coreboot are: |
| 26 | 1. Added multi-phase silicon initialization to increase the modularity of the |
| 27 | FspSiliconInit() API |
| 28 | 2. FSP_INFO_HEADER changes to add FspMultiPhaseSiInitEntryOffset |
| 29 | 3. Added EnableMultiPhaseSiliconInit, bootloaders designed for FSP2.0/2.1 can disable |
| 30 | the FspMultiPhaseSiInit() API and continue to use FspSiliconInit() without change. |
| 31 | |
Anil Kumar | 57309d3 | 2021-11-11 18:56:21 -0800 | [diff] [blame] | 32 | config PLATFORM_USES_FSP2_3 |
| 33 | bool |
| 34 | default n |
| 35 | select PLATFORM_USES_FSP2_2 |
| 36 | help |
| 37 | Include FSP 2.3 wrappers and functionality. |
| 38 | Features added into FSP 2.3 specification that impact coreboot are: |
| 39 | 1. Added ExtendedImageRevision field in FSP_INFO_HEADER |
| 40 | 2. Added FSP_NON_VOLATILE_STORAGE_HOB2 |
| 41 | |
Andrey Petrov | 9be1a11 | 2016-05-14 16:32:39 -0700 | [diff] [blame] | 42 | if PLATFORM_USES_FSP2_0 |
Andrey Petrov | b37fd67 | 2016-03-01 16:25:38 -0800 | [diff] [blame] | 43 | |
Patrick Rudolph | 31218a4 | 2020-11-30 15:50:06 +0100 | [diff] [blame] | 44 | config PLATFORM_USES_FSP2_X86_32 |
| 45 | bool |
| 46 | default y |
| 47 | help |
| 48 | The FSP 2.0 runs in x86_32 protected mode. |
| 49 | Once there's a x86_64 FSP this needs to default to n. |
| 50 | |
Nico Huber | a0e72c4 | 2020-04-03 23:38:17 +0200 | [diff] [blame] | 51 | config HAVE_INTEL_FSP_REPO |
| 52 | bool |
| 53 | help |
| 54 | Select this, if the FSP binaries for the platform are public |
| 55 | and available in 3rdparty/fsp/. When selecting this option, the |
| 56 | platform must also set FSP_HEADER_PATH and FSP_FD_PATH correctly. |
| 57 | |
Nico Huber | 04da5d7 | 2020-03-27 20:34:54 +0100 | [diff] [blame] | 58 | config FSP_USE_REPO |
| 59 | bool "Use binaries of the Intel FSP repository on GitHub" |
| 60 | depends on HAVE_INTEL_FSP_REPO |
Michael Niewöhner | 59f06ad | 2020-11-25 13:55:42 +0100 | [diff] [blame] | 61 | select FSP_FULL_FD |
Nico Huber | 04da5d7 | 2020-03-27 20:34:54 +0100 | [diff] [blame] | 62 | default y |
Andrey Petrov | 9be1a11 | 2016-05-14 16:32:39 -0700 | [diff] [blame] | 63 | help |
Nico Huber | a0e72c4 | 2020-04-03 23:38:17 +0200 | [diff] [blame] | 64 | Select this option to use the default FSP headers and binaries |
| 65 | found in the IntelFsp GitHub repository at |
| 66 | |
| 67 | https://github.com/IntelFsp/FSP/ |
| 68 | |
| 69 | If unsure, say Y. |
| 70 | |
| 71 | config FSP_HEADER_PATH |
| 72 | string "Location of FSP headers" if !FSP_USE_REPO |
| 73 | help |
| 74 | Include directory with the FSP ABI header files. |
| 75 | |
Nico Huber | 04da5d7 | 2020-03-27 20:34:54 +0100 | [diff] [blame] | 76 | config ADD_FSP_BINARIES |
| 77 | bool "Add Intel FSP 2.0 binaries to CBFS" if !FSP_USE_REPO |
| 78 | default y if FSP_USE_REPO |
| 79 | help |
| 80 | Add the FSP-M and FSP-S binaries to CBFS. |
Andrey Petrov | 9be1a11 | 2016-05-14 16:32:39 -0700 | [diff] [blame] | 81 | |
Brenton Dong | 0a5971c | 2016-10-18 11:35:15 -0700 | [diff] [blame] | 82 | config FSP_T_CBFS |
| 83 | string "Name of FSP-T in CBFS" |
| 84 | depends on FSP_CAR |
| 85 | default "fspt.bin" |
| 86 | |
Arthur Heymans | 0f068a6 | 2021-05-03 10:59:45 +0200 | [diff] [blame] | 87 | config FSP_T_LOCATION |
| 88 | hex |
| 89 | default 0xfffe0000 |
| 90 | help |
| 91 | The location for FSP-T. |
| 92 | |
Andrey Petrov | 9be1a11 | 2016-05-14 16:32:39 -0700 | [diff] [blame] | 93 | config FSP_S_CBFS |
| 94 | string "Name of FSP-S in CBFS" |
| 95 | default "fsps.bin" |
| 96 | |
| 97 | config FSP_M_CBFS |
| 98 | string "Name of FSP-M in CBFS" |
| 99 | default "fspm.bin" |
| 100 | |
Michael Niewöhner | 59f06ad | 2020-11-25 13:55:42 +0100 | [diff] [blame] | 101 | config FSP_FULL_FD |
| 102 | bool "Use a combined FSP FD file" if !FSP_USE_REPO |
| 103 | depends on ADD_FSP_BINARIES |
| 104 | help |
| 105 | Use a combined FSP FD file instead of specifying individual, already split |
| 106 | binaries and split the file at build-time. |
| 107 | |
Michael Niewöhner | 3044d70 | 2020-11-25 15:07:47 +0100 | [diff] [blame] | 108 | config FSP_FD_PATH |
| 109 | string "Location of FSP FD file" if FSP_FULL_FD && !FSP_USE_REPO |
| 110 | help |
| 111 | Path to the FSP FD file that contains the individual FSP-T, FSP-M |
| 112 | and FSP-S binaries. The file gets split at build-time. |
| 113 | |
Brenton Dong | 0a5971c | 2016-10-18 11:35:15 -0700 | [diff] [blame] | 114 | config FSP_T_FILE |
Michael Niewöhner | 59f06ad | 2020-11-25 13:55:42 +0100 | [diff] [blame] | 115 | string "Intel FSP-T (temp RAM init) binary path and filename" if !FSP_FULL_FD |
Nico Huber | 04da5d7 | 2020-03-27 20:34:54 +0100 | [diff] [blame] | 116 | depends on ADD_FSP_BINARIES |
Brenton Dong | 0a5971c | 2016-10-18 11:35:15 -0700 | [diff] [blame] | 117 | depends on FSP_CAR |
Michael Niewöhner | 59f06ad | 2020-11-25 13:55:42 +0100 | [diff] [blame] | 118 | default "\$(obj)/Fsp_T.fd" if FSP_FULL_FD |
Brenton Dong | 0a5971c | 2016-10-18 11:35:15 -0700 | [diff] [blame] | 119 | help |
Nico Huber | 04da5d7 | 2020-03-27 20:34:54 +0100 | [diff] [blame] | 120 | The path and filename of the Intel FSP-T binary for this platform. |
Brenton Dong | 0a5971c | 2016-10-18 11:35:15 -0700 | [diff] [blame] | 121 | |
Andrey Petrov | 9be1a11 | 2016-05-14 16:32:39 -0700 | [diff] [blame] | 122 | config FSP_M_FILE |
Michael Niewöhner | 59f06ad | 2020-11-25 13:55:42 +0100 | [diff] [blame] | 123 | string "Intel FSP-M (memory init) binary path and filename" if !FSP_FULL_FD |
Andrey Petrov | 9be1a11 | 2016-05-14 16:32:39 -0700 | [diff] [blame] | 124 | depends on ADD_FSP_BINARIES |
Michael Niewöhner | 59f06ad | 2020-11-25 13:55:42 +0100 | [diff] [blame] | 125 | default "\$(obj)/Fsp_M.fd" if FSP_FULL_FD |
Andrey Petrov | 9be1a11 | 2016-05-14 16:32:39 -0700 | [diff] [blame] | 126 | help |
| 127 | The path and filename of the Intel FSP-M binary for this platform. |
| 128 | |
| 129 | config FSP_S_FILE |
Michael Niewöhner | 59f06ad | 2020-11-25 13:55:42 +0100 | [diff] [blame] | 130 | string "Intel FSP-S (silicon init) binary path and filename" if !FSP_FULL_FD |
Andrey Petrov | 9be1a11 | 2016-05-14 16:32:39 -0700 | [diff] [blame] | 131 | depends on ADD_FSP_BINARIES |
Michael Niewöhner | 59f06ad | 2020-11-25 13:55:42 +0100 | [diff] [blame] | 132 | default "\$(obj)/Fsp_S.fd" if FSP_FULL_FD |
Andrey Petrov | 9be1a11 | 2016-05-14 16:32:39 -0700 | [diff] [blame] | 133 | help |
| 134 | The path and filename of the Intel FSP-S binary for this platform. |
| 135 | |
Brenton Dong | 0a5971c | 2016-10-18 11:35:15 -0700 | [diff] [blame] | 136 | config FSP_CAR |
Arthur Heymans | acc88f8 | 2019-10-20 14:29:59 +0200 | [diff] [blame] | 137 | bool |
Brenton Dong | 0a5971c | 2016-10-18 11:35:15 -0700 | [diff] [blame] | 138 | default n |
Arthur Heymans | 5fc2bed | 2021-01-23 15:09:48 +0100 | [diff] [blame] | 139 | select NO_CBFS_MCACHE if !NO_FSP_TEMP_RAM_EXIT |
Brenton Dong | 0a5971c | 2016-10-18 11:35:15 -0700 | [diff] [blame] | 140 | help |
| 141 | Use FSP APIs to initialize & Tear Down the Cache-As-Ram |
| 142 | |
Arthur Heymans | 9789689 | 2021-01-04 12:22:57 +0100 | [diff] [blame] | 143 | config FSP_T_RESERVED_SIZE |
| 144 | hex |
| 145 | default 0x100 if FSP_CAR |
| 146 | default 0x0 |
| 147 | help |
| 148 | This is the size of the area reserved by FSP-T. This is not |
| 149 | defined in the FSP specification but in the SOC integration |
| 150 | guides. |
| 151 | |
Arthur Heymans | 98cc783 | 2020-12-08 12:49:38 +0100 | [diff] [blame] | 152 | config NO_FSP_TEMP_RAM_EXIT |
| 153 | bool |
| 154 | depends on FSP_CAR |
| 155 | help |
| 156 | Select this on a platform where you want to use FSP-T but use |
| 157 | coreboot code to tear down CAR. |
| 158 | |
Lee Leahy | 27cd96a | 2016-07-21 11:16:39 -0700 | [diff] [blame] | 159 | config FSP_M_XIP |
Arthur Heymans | 585786b | 2019-10-20 14:32:57 +0200 | [diff] [blame] | 160 | bool |
Lee Leahy | 27cd96a | 2016-07-21 11:16:39 -0700 | [diff] [blame] | 161 | default n |
| 162 | help |
| 163 | Select this value when FSP-M is execute-in-place. |
| 164 | |
praveen hodagatta pranesh | 6c96542 | 2018-10-10 22:48:00 +0800 | [diff] [blame] | 165 | config FSP_T_XIP |
| 166 | bool |
| 167 | default n |
| 168 | help |
| 169 | Select this value when FSP-T is execute-in-place. |
| 170 | |
Aamir Bohra | 6d569e0c | 2018-08-27 13:36:15 +0530 | [diff] [blame] | 171 | config FSP_USES_CB_STACK |
| 172 | bool |
| 173 | default n |
| 174 | help |
| 175 | Enable support for fsp to use same stack as coreboot. |
| 176 | This option allows fsp to continue using coreboot stack |
| 177 | without reinitializing stack pointer. This feature is |
| 178 | supported Icelake onwards. |
| 179 | |
Kyösti Mälkki | c987150 | 2019-09-03 07:03:39 +0300 | [diff] [blame] | 180 | config FSP_TEMP_RAM_SIZE |
| 181 | hex |
Subrata Banik | 1d260e6 | 2019-09-09 13:55:42 +0530 | [diff] [blame] | 182 | help |
Felix Held | 414d7e4 | 2020-08-11 22:54:06 +0200 | [diff] [blame] | 183 | The amount of memory coreboot reserves for the FSP to use. In the |
| 184 | case of FSP 2.1 and newer that share the stack with coreboot instead |
| 185 | of having its own stack, this is the amount of anticipated heap usage |
| 186 | in CAR by FSP to setup HOB and needs to be the recommended value from |
| 187 | the Platform FSP integration guide. In the case of the FSP having its |
| 188 | own stack that will be placed in DRAM and not in CAR, this is the |
| 189 | amount of memory the FSP needs for its stack and heap. |
Kyösti Mälkki | c987150 | 2019-09-03 07:03:39 +0300 | [diff] [blame] | 190 | |
Aaron Durbin | a3cecb2 | 2017-04-25 21:58:10 -0500 | [diff] [blame] | 191 | config FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS |
| 192 | bool |
| 193 | help |
| 194 | This is selected by SoC or mainboard to supply their own |
| 195 | concept of a version for the memory settings respectively. |
| 196 | This allows deployed systems to bump their version number |
| 197 | with the same FSP which will trigger a retrain of the memory. |
| 198 | |
Wim Vervoorn | d137150 | 2019-12-17 14:10:16 +0100 | [diff] [blame] | 199 | config HAVE_FSP_LOGO_SUPPORT |
| 200 | bool |
| 201 | default n |
| 202 | |
Kyösti Mälkki | 4949a3d | 2021-01-09 20:38:43 +0200 | [diff] [blame] | 203 | config BMP_LOGO |
Wim Vervoorn | cbc878d2 | 2019-11-28 14:45:12 +0100 | [diff] [blame] | 204 | bool "Enable logo" |
| 205 | default n |
Wim Vervoorn | d137150 | 2019-12-17 14:10:16 +0100 | [diff] [blame] | 206 | depends on HAVE_FSP_LOGO_SUPPORT |
Wim Vervoorn | cbc878d2 | 2019-11-28 14:45:12 +0100 | [diff] [blame] | 207 | help |
| 208 | Uses the FSP to display the boot logo. This method supports a |
| 209 | BMP file only. The uncompressed size can be up to 1 MB. The logo can be compressed |
| 210 | using LZMA. |
| 211 | |
| 212 | config FSP2_0_LOGO_FILE_NAME |
| 213 | string "Logo file" |
Kyösti Mälkki | 4949a3d | 2021-01-09 20:38:43 +0200 | [diff] [blame] | 214 | depends on BMP_LOGO |
Patrick Georgi | b8fba86 | 2020-06-17 21:06:53 +0200 | [diff] [blame] | 215 | default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/logo.bmp" |
Wim Vervoorn | cbc878d2 | 2019-11-28 14:45:12 +0100 | [diff] [blame] | 216 | |
Aaron Durbin | a85febc | 2020-05-15 15:09:10 -0600 | [diff] [blame] | 217 | config FSP_COMPRESS_FSP_S_LZMA |
| 218 | bool |
| 219 | |
| 220 | config FSP_COMPRESS_FSP_S_LZ4 |
| 221 | bool |
| 222 | |
Aaron Durbin | ecbfa99 | 2020-05-15 17:01:58 -0600 | [diff] [blame] | 223 | config FSP_COMPRESS_FSP_M_LZMA |
| 224 | bool |
| 225 | depends on !FSP_M_XIP |
| 226 | |
| 227 | config FSP_COMPRESS_FSP_M_LZ4 |
| 228 | bool |
| 229 | depends on !FSP_M_XIP |
| 230 | |
Raul E Rangel | 82897c9 | 2021-11-05 10:29:24 -0600 | [diff] [blame] | 231 | config FSP_ALIGNMENT_FSP_S |
| 232 | int |
| 233 | help |
| 234 | Sets the CBFS alignment for FSP-S |
| 235 | |
| 236 | config FSP_ALIGNMENT_FSP_M |
| 237 | int |
| 238 | help |
| 239 | Sets the CBFS alignment for FSP-M |
| 240 | |
Aaron Durbin | ecbfa99 | 2020-05-15 17:01:58 -0600 | [diff] [blame] | 241 | config FSP_M_ADDR |
| 242 | hex |
| 243 | help |
| 244 | The address FSP-M will be relocated to during build time |
| 245 | |
Subrata Banik | 8f7a248 | 2020-09-20 12:28:45 +0530 | [diff] [blame] | 246 | config FSP_STATUS_GLOBAL_RESET_REQUIRED_3 |
| 247 | bool |
| 248 | help |
| 249 | FSP Reset Status code used for global reset as per FSP EAS v2.0 section 11.2.2 |
| 250 | |
| 251 | config FSP_STATUS_GLOBAL_RESET_REQUIRED_4 |
| 252 | bool |
| 253 | help |
| 254 | FSP Reset Status code used for global reset as per FSP EAS v2.0 section 11.2.2 |
| 255 | |
| 256 | config FSP_STATUS_GLOBAL_RESET_REQUIRED_5 |
| 257 | bool |
| 258 | help |
| 259 | FSP Reset Status code used for global reset as per FSP EAS v2.0 section 11.2.2 |
| 260 | |
| 261 | config FSP_STATUS_GLOBAL_RESET_REQUIRED_6 |
| 262 | bool |
| 263 | help |
| 264 | FSP Reset Status code used for global reset as per FSP EAS v2.0 section 11.2.2 |
| 265 | |
| 266 | config FSP_STATUS_GLOBAL_RESET_REQUIRED_7 |
| 267 | bool |
| 268 | help |
| 269 | FSP Reset Status code used for global reset as per FSP EAS v2.0 section 11.2.2 |
| 270 | |
| 271 | config FSP_STATUS_GLOBAL_RESET_REQUIRED_8 |
| 272 | bool |
| 273 | help |
| 274 | FSP Reset Status code used for global reset as per FSP EAS v2.0 section 11.2.2 |
| 275 | |
| 276 | config FSP_STATUS_GLOBAL_RESET |
| 277 | hex |
Subrata Banik | 2b2ade9 | 2020-10-31 21:07:16 +0530 | [diff] [blame] | 278 | depends on SOC_INTEL_COMMON_FSP_RESET |
Subrata Banik | 8f7a248 | 2020-09-20 12:28:45 +0530 | [diff] [blame] | 279 | default 0x40000003 if FSP_STATUS_GLOBAL_RESET_REQUIRED_3 |
| 280 | default 0x40000004 if FSP_STATUS_GLOBAL_RESET_REQUIRED_4 |
| 281 | default 0x40000005 if FSP_STATUS_GLOBAL_RESET_REQUIRED_5 |
| 282 | default 0x40000006 if FSP_STATUS_GLOBAL_RESET_REQUIRED_6 |
| 283 | default 0x40000007 if FSP_STATUS_GLOBAL_RESET_REQUIRED_7 |
| 284 | default 0x40000008 if FSP_STATUS_GLOBAL_RESET_REQUIRED_8 |
| 285 | default 0xffffffff |
| 286 | help |
| 287 | If global reset is supported by SoC then select the correct status value for global |
| 288 | reset type from SoC Kconfig based on available Kconfig options |
| 289 | FSP_STATUS_GLOBAL_RESET_REQUIRED_X. Default is unsupported. |
| 290 | |
Subrata Banik | 2b2ade9 | 2020-10-31 21:07:16 +0530 | [diff] [blame] | 291 | config SOC_INTEL_COMMON_FSP_RESET |
| 292 | bool |
| 293 | help |
| 294 | Common code block to handle platform reset request raised by FSP. The FSP |
| 295 | will use the FSP EAS v2.0 section 12.2.2 (OEM Status Code) to indicate that |
| 296 | a reset is required. |
Subrata Banik | 298b359 | 2021-09-14 12:38:08 +0530 | [diff] [blame] | 297 | |
| 298 | config FSPS_HAS_ARCH_UPD |
| 299 | bool |
| 300 | help |
| 301 | SoC users must select this Kconfig if the `FSPS_UPD` header has architecture |
| 302 | UPD structure as `FSPS_ARCH_UPD`. Typically, platform with FSP 2.2 specification |
| 303 | onwards has support for `FSPS_ARCH_UPD` section as part of `FSPS_UPD` structure. |
| 304 | But there are some exceptions as in TGL, JSL, XEON_SP FSP header doesn't have |
| 305 | support for FSPS_ARCH_UPD. |
| 306 | |
| 307 | config FSPS_USE_MULTI_PHASE_INIT |
| 308 | bool |
| 309 | help |
| 310 | SoC users to select this Kconfig to set EnableMultiPhaseSiliconInit to enable and |
| 311 | execute FspMultiPhaseSiInit() API. |
| 312 | |
Subrata Banik | 34f26b2 | 2022-02-10 12:38:02 +0530 | [diff] [blame] | 313 | config USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM |
Subrata Banik | e8feab0 | 2021-12-27 10:25:55 +0000 | [diff] [blame] | 314 | bool |
| 315 | help |
| 316 | The FSP API is used to notify the FSP about different phases in the boot process. |
| 317 | The current FSP specification supports three notify phases: |
| 318 | - Post PCI enumeration |
| 319 | - Ready to Boot |
| 320 | - End of Firmware |
Subrata Banik | 34f26b2 | 2022-02-10 12:38:02 +0530 | [diff] [blame] | 321 | This option allows FSP to execute Notify Phase API (Post PCI enumeration). |
| 322 | SoC users can override this config to use coreboot native implementations |
| 323 | to perform the required lock down and chipset register configuration prior |
| 324 | to executing any 3rd-party code during PCI enumeration (i.e. Option ROM). |
| 325 | |
| 326 | coreboot native implementation to skip FSP Notify Phase (Post PCI enumeration) |
| 327 | is still WIP. |
| 328 | |
| 329 | config USE_FSP_NOTIFY_PHASE_READY_TO_BOOT |
| 330 | bool |
| 331 | help |
| 332 | The FSP API is used to notify the FSP about different phases in the boot process. |
| 333 | The current FSP specification supports three notify phases: |
| 334 | - Post PCI enumeration |
| 335 | - Ready to Boot |
| 336 | - End of Firmware |
| 337 | This option allows FSP to execute Notify Phase API (Ready to Boot). |
| 338 | SoC users can override this config to use coreboot native implementations |
Subrata Banik | e8feab0 | 2021-12-27 10:25:55 +0000 | [diff] [blame] | 339 | to perform the required lock down and chipset register configuration prior |
| 340 | boot to payload. |
| 341 | |
Subrata Banik | 34f26b2 | 2022-02-10 12:38:02 +0530 | [diff] [blame] | 342 | config USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE |
Subrata Banik | e8feab0 | 2021-12-27 10:25:55 +0000 | [diff] [blame] | 343 | bool |
| 344 | help |
| 345 | The FSP API is used to notify the FSP about different phases in the boot process. |
| 346 | The current FSP specification supports three notify phases: |
| 347 | - Post PCI enumeration |
| 348 | - Ready to Boot |
| 349 | - End of Firmware |
Subrata Banik | 34f26b2 | 2022-02-10 12:38:02 +0530 | [diff] [blame] | 350 | This option allows FSP to execute Notify Phase API (End of Firmware). |
| 351 | SoC users can override this config to use coreboot native implementations |
| 352 | to perform the required lock down and chipset register configuration prior |
| 353 | boot to payload. |
Subrata Banik | e8feab0 | 2021-12-27 10:25:55 +0000 | [diff] [blame] | 354 | |
Subrata Banik | 3ba6f8c | 2022-03-23 03:22:28 +0530 | [diff] [blame] | 355 | config FSP_USES_CB_DEBUG_EVENT_HANDLER |
| 356 | bool |
| 357 | default n |
| 358 | help |
| 359 | This option allows to create `Debug Event Handler` to print FSP debug messages |
| 360 | to output device using coreboot native implementation. |
| 361 | |
Subrata Banik | 6de1d9f | 2022-03-20 19:50:38 +0530 | [diff] [blame] | 362 | config DISPLAY_FSP_TIMESTAMPS |
| 363 | bool "Display FSP Timestamps" |
| 364 | default n |
| 365 | help |
| 366 | Select this config to retrieve FSP timestamps from Firmware Performance Data Table |
| 367 | (FPDT) and display from ramstage after FSP-S is executed. |
| 368 | |
| 369 | To be able to use this, FSP has to be compiled with `PcdFspPerformanceEnable` set to |
| 370 | `TRUE`. |
| 371 | |
Subrata Banik | 9bc5b00 | 2022-04-06 18:41:25 +0000 | [diff] [blame] | 372 | config FSP_ENABLE_SERIAL_DEBUG |
| 373 | bool "Output FSP debug messages on serial console" |
| 374 | default y |
| 375 | depends on FSP_USES_CB_DEBUG_EVENT_HANDLER |
| 376 | help |
| 377 | Output FSP debug messages on serial console. |
| 378 | |
| 379 | The config option is selected based on your FSP configuration i.e., debug or |
| 380 | release. Enable this option from site-local to print FSP serial messages using |
| 381 | coreboot native debug driver when coreboot has integrated the debug FSP |
| 382 | binaries. coreboot disables serial messages when this config is not enabled. |
| 383 | |
Johnny Lin | 55bc2d3 | 2022-06-13 14:05:43 +0800 | [diff] [blame] | 384 | config SAVE_MRC_AFTER_FSPS |
| 385 | bool |
| 386 | default n |
| 387 | depends on XEON_SP_COMMON_BASE |
| 388 | help |
| 389 | Save MRC training data after FSP-S. Select this on platforms that generate MRC |
| 390 | cache HOB data as part of FSP-S rather than FSP-M. |
| 391 | |
Subrata Banik | da7d00e | 2023-04-26 16:31:56 +0530 | [diff] [blame] | 392 | config FSP_MULTIPHASE_SI_INIT_RETURN_BROKEN |
| 393 | bool |
| 394 | default n |
| 395 | depends on PLATFORM_USES_FSP2_2 |
| 396 | help |
| 397 | Select this config for Intel SoC platform where FSP MultiPhaseSiInit API is unable |
| 398 | to return ERROR status properly. |
| 399 | |
| 400 | The config option will be selected based on the target SoC platform and if the |
| 401 | problem existed inside the FSP MultiPhaseSiInit. At present the problem has only |
| 402 | reported with Alder Lake and Raptor Lake FSP where MultiPhaseSiInit API is unable |
| 403 | to return any ERROR status. |
| 404 | |
Andrey Petrov | 9be1a11 | 2016-05-14 16:32:39 -0700 | [diff] [blame] | 405 | endif |