Angel Pons | 8a3453f | 2020-04-02 23:48:19 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Lee Leahy | 3dad489 | 2015-05-05 11:14:02 -0700 | [diff] [blame] | 2 | |
Arthur Heymans | 8256ca0 | 2019-10-21 18:47:46 +0200 | [diff] [blame] | 3 | #include <cpu/x86/mtrr.h> |
| 4 | #include <cpu/x86/cache.h> |
Frans Hendriks | 4e0ec59 | 2019-06-06 10:07:17 +0200 | [diff] [blame] | 5 | #include <cpu/x86/post_code.h> |
| 6 | |
Lee Leahy | b5ad827 | 2015-04-20 15:29:16 -0700 | [diff] [blame] | 7 | /* |
| 8 | * Replacement for cache_as_ram.inc when using the FSP binary. This code |
| 9 | * locates the FSP binary, initializes the cache as RAM and performs the |
| 10 | * first stage of initialization. Next this code switches the stack from |
| 11 | * the cache to RAM and then disables the cache as RAM. Finally this code |
| 12 | * performs the final stage of initialization. |
| 13 | */ |
| 14 | |
Frans Hendriks | 4e0ec59 | 2019-06-06 10:07:17 +0200 | [diff] [blame] | 15 | #define LHLT_DELAY 0x50000 /* I/O delay between post codes on failure */ |
| 16 | |
Kyösti Mälkki | 7522a8f | 2020-11-20 16:47:38 +0200 | [diff] [blame] | 17 | .section .init, "ax", @progbits |
| 18 | |
Frans Hendriks | 4e0ec59 | 2019-06-06 10:07:17 +0200 | [diff] [blame] | 19 | .global bootblock_pre_c_entry |
| 20 | bootblock_pre_c_entry: |
Lee Leahy | b5ad827 | 2015-04-20 15:29:16 -0700 | [diff] [blame] | 21 | /* |
Kyösti Mälkki | ee2e936 | 2018-12-28 16:06:45 +0200 | [diff] [blame] | 22 | * Per FSP1.1 specs, following registers are preserved: |
| 23 | * EBX, EDI, ESI, EBP, MM0, MM1 |
| 24 | * |
| 25 | * Shift values to release MM2. |
Arthur Heymans | 59b6542 | 2019-05-23 15:24:30 +0200 | [diff] [blame] | 26 | * mm0 -> ebx: BIST value |
Kyösti Mälkki | ee2e936 | 2018-12-28 16:06:45 +0200 | [diff] [blame] | 27 | * mm1 -> mm0: low 32-bits of TSC value |
| 28 | * mm2 -> mm1: high 32-bits of TSC value |
Lee Leahy | b5ad827 | 2015-04-20 15:29:16 -0700 | [diff] [blame] | 29 | */ |
Arthur Heymans | 59b6542 | 2019-05-23 15:24:30 +0200 | [diff] [blame] | 30 | movd %mm0, %ebx |
Kyösti Mälkki | ee2e936 | 2018-12-28 16:06:45 +0200 | [diff] [blame] | 31 | movd %mm1, %eax |
| 32 | movd %eax, %mm0 |
| 33 | movd %mm2, %eax |
| 34 | movd %eax, %mm1 |
| 35 | |
Lee Leahy | 3dad489 | 2015-05-05 11:14:02 -0700 | [diff] [blame] | 36 | cache_as_ram: |
lilacious | 40cb3fe | 2023-06-21 23:24:14 +0200 | [diff] [blame^] | 37 | post_code(POSTCODE_BOOTBLOCK_CAR) |
Lee Leahy | 3dad489 | 2015-05-05 11:14:02 -0700 | [diff] [blame] | 38 | |
Arthur Heymans | 8256ca0 | 2019-10-21 18:47:46 +0200 | [diff] [blame] | 39 | /* Cache the rom and update the microcode */ |
| 40 | cache_rom: |
| 41 | /* Disable cache */ |
| 42 | movl %cr0, %eax |
| 43 | orl $CR0_CacheDisable, %eax |
| 44 | movl %eax, %cr0 |
| 45 | |
| 46 | movl $MTRR_PHYS_BASE(1), %ecx |
| 47 | xorl %edx, %edx |
| 48 | movl $(CACHE_ROM_BASE | MTRR_TYPE_WRPROT), %eax |
| 49 | wrmsr |
| 50 | |
| 51 | movl $MTRR_PHYS_MASK(1), %ecx |
| 52 | rdmsr |
| 53 | movl $(~(CACHE_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax |
| 54 | wrmsr |
| 55 | |
| 56 | /* Enable cache */ |
| 57 | movl %cr0, %eax |
| 58 | andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax |
| 59 | invd |
| 60 | movl %eax, %cr0 |
| 61 | |
| 62 | /* Enable MTRR. */ |
| 63 | movl $MTRR_DEF_TYPE_MSR, %ecx |
| 64 | rdmsr |
| 65 | orl $MTRR_DEF_TYPE_EN, %eax |
| 66 | wrmsr |
| 67 | |
| 68 | /* The Google FSP release for Braswell has broken microcode update |
| 69 | code and FSP needs the installed microcode revision to be non zero. |
| 70 | It is better to have coreboot do it instead of relying on a fragile |
| 71 | blob. */ |
| 72 | update_microcode: |
| 73 | /* put the return address in %esp */ |
| 74 | movl $end_microcode_update, %esp |
| 75 | jmp update_bsp_microcode |
| 76 | end_microcode_update: |
| 77 | |
Lee Leahy | b5ad827 | 2015-04-20 15:29:16 -0700 | [diff] [blame] | 78 | /* |
Lee Leahy | 3dad489 | 2015-05-05 11:14:02 -0700 | [diff] [blame] | 79 | * Find the FSP binary in cbfs. |
| 80 | * Make a fake stack that has the return value back to this code. |
| 81 | */ |
Lee Leahy | b5ad827 | 2015-04-20 15:29:16 -0700 | [diff] [blame] | 82 | lea fake_fsp_stack, %esp |
| 83 | jmp find_fsp |
Lee Leahy | 3dad489 | 2015-05-05 11:14:02 -0700 | [diff] [blame] | 84 | find_fsp_ret: |
| 85 | /* Save the FSP location */ |
Lee Leahy | b5ad827 | 2015-04-20 15:29:16 -0700 | [diff] [blame] | 86 | mov %eax, %ebp |
| 87 | |
| 88 | /* |
| 89 | * Only when a valid FSP binary is found at CONFIG_FSP_LOC is |
| 90 | * the returned FSP_INFO_HEADER structure address above the base |
| 91 | * address of FSP binary specified by the CONFIG_FSP_LOC value. |
| 92 | * All of the error values are in the 0x8xxxxxxx range which are |
| 93 | * below the CONFIG_FSP_LOC value. |
| 94 | */ |
| 95 | cmp $CONFIG_FSP_LOC, %eax |
| 96 | jbe halt1 |
Lee Leahy | 3dad489 | 2015-05-05 11:14:02 -0700 | [diff] [blame] | 97 | |
lilacious | 40cb3fe | 2023-06-21 23:24:14 +0200 | [diff] [blame^] | 98 | post_code(POSTCODE_FSP_TEMP_RAM_INIT) |
Lee Leahy | 3dad489 | 2015-05-05 11:14:02 -0700 | [diff] [blame] | 99 | |
| 100 | /* Calculate entry into FSP */ |
Lee Leahy | b5ad827 | 2015-04-20 15:29:16 -0700 | [diff] [blame] | 101 | mov 0x30(%ebp), %eax /* Load TempRamInitEntry */ |
| 102 | add 0x1c(%ebp), %eax /* add in the offset for FSP */ |
Lee Leahy | 3dad489 | 2015-05-05 11:14:02 -0700 | [diff] [blame] | 103 | |
| 104 | /* |
| 105 | * Pass early init variables on a fake stack (no memory yet) |
| 106 | * as well as the return location |
| 107 | */ |
Lee Leahy | b5ad827 | 2015-04-20 15:29:16 -0700 | [diff] [blame] | 108 | lea CAR_init_stack, %esp |
Lee Leahy | 3dad489 | 2015-05-05 11:14:02 -0700 | [diff] [blame] | 109 | |
| 110 | /* |
Lee Leahy | b5ad827 | 2015-04-20 15:29:16 -0700 | [diff] [blame] | 111 | * BIST value is zero |
| 112 | * eax: TempRamInitApi address |
Arthur Heymans | 59b6542 | 2019-05-23 15:24:30 +0200 | [diff] [blame] | 113 | * ebx: BIST value |
Lee Leahy | b5ad827 | 2015-04-20 15:29:16 -0700 | [diff] [blame] | 114 | * ebp: FSP_INFO_HEADER address |
Lee Leahy | b5ad827 | 2015-04-20 15:29:16 -0700 | [diff] [blame] | 115 | * esi: Not used |
| 116 | * mm0: low 32-bits of TSC value |
| 117 | * mm1: high 32-bits of TSC value |
Lee Leahy | 3dad489 | 2015-05-05 11:14:02 -0700 | [diff] [blame] | 118 | */ |
Lee Leahy | 3dad489 | 2015-05-05 11:14:02 -0700 | [diff] [blame] | 119 | |
Lee Leahy | b5ad827 | 2015-04-20 15:29:16 -0700 | [diff] [blame] | 120 | /* call FSP binary to setup temporary stack */ |
| 121 | jmp *%eax |
| 122 | |
| 123 | CAR_init_done: |
Lee Leahy | b5ad827 | 2015-04-20 15:29:16 -0700 | [diff] [blame] | 124 | |
| 125 | /* |
| 126 | * ebp: FSP_INFO_HEADER address |
Arthur Heymans | 59b6542 | 2019-05-23 15:24:30 +0200 | [diff] [blame] | 127 | * ebx: BIST value |
Lee Leahy | b5ad827 | 2015-04-20 15:29:16 -0700 | [diff] [blame] | 128 | * ecx: Temp RAM base |
| 129 | * edx: Temp RAM top |
Lee Leahy | b5ad827 | 2015-04-20 15:29:16 -0700 | [diff] [blame] | 130 | * mm0: low 32-bits of TSC value |
| 131 | * mm1: high 32-bits of TSC value |
| 132 | */ |
| 133 | |
| 134 | cmp $0, %eax |
| 135 | jne halt2 |
| 136 | |
Frans Hendriks | 7590c37 | 2020-11-20 11:24:54 +0100 | [diff] [blame] | 137 | /* Setup bootblock stack */ |
Frans Hendriks | 7ba970a | 2020-11-19 08:10:47 +0100 | [diff] [blame] | 138 | movl $_ecar_stack, %esp |
Lee Leahy | b5ad827 | 2015-04-20 15:29:16 -0700 | [diff] [blame] | 139 | |
Lee Leahy | b5ad827 | 2015-04-20 15:29:16 -0700 | [diff] [blame] | 140 | /* |
| 141 | * ebp: FSP_INFO_HEADER address |
Arthur Heymans | 59b6542 | 2019-05-23 15:24:30 +0200 | [diff] [blame] | 142 | * ebx: BIST value |
Lee Leahy | b5ad827 | 2015-04-20 15:29:16 -0700 | [diff] [blame] | 143 | * ecx: Temp RAM base |
| 144 | * edx: Temp RAM top |
| 145 | * esp: Top of stack in temp RAM |
| 146 | * mm0: low 32-bits of TSC value |
| 147 | * mm1: high 32-bits of TSC value |
Lee Leahy | b5ad827 | 2015-04-20 15:29:16 -0700 | [diff] [blame] | 148 | */ |
| 149 | |
Frans Hendriks | c022a79 | 2020-11-20 10:52:39 +0100 | [diff] [blame] | 150 | /* |
| 151 | * temp_memory_start/end reside in the .bss section, which gets cleared |
| 152 | * below. Save the FSP return value to the stack before writing those |
| 153 | * variables. |
| 154 | */ |
| 155 | push %ecx |
| 156 | push %edx |
| 157 | |
Frans Hendriks | 335eb12 | 2020-11-19 15:45:43 +0100 | [diff] [blame] | 158 | /* clear .bss section */ |
Lee Leahy | b5ad827 | 2015-04-20 15:29:16 -0700 | [diff] [blame] | 159 | cld |
Frans Hendriks | 335eb12 | 2020-11-19 15:45:43 +0100 | [diff] [blame] | 160 | xor %eax, %eax |
| 161 | movl $(_ebss), %ecx |
| 162 | movl $(_bss), %edi |
| 163 | sub %edi, %ecx |
Lee Leahy | b5ad827 | 2015-04-20 15:29:16 -0700 | [diff] [blame] | 164 | shrl $2, %ecx |
Lee Leahy | b5ad827 | 2015-04-20 15:29:16 -0700 | [diff] [blame] | 165 | rep stosl |
| 166 | |
Frans Hendriks | c022a79 | 2020-11-20 10:52:39 +0100 | [diff] [blame] | 167 | pop %edx |
| 168 | movl %edx, temp_memory_end |
| 169 | pop %ecx |
| 170 | movl %ecx, temp_memory_start |
| 171 | |
Arthur Heymans | 59b6542 | 2019-05-23 15:24:30 +0200 | [diff] [blame] | 172 | /* Need to align stack to 16 bytes at call instruction. Account for |
| 173 | the pushes below. */ |
| 174 | andl $0xfffffff0, %esp |
Frans Hendriks | 4e0ec59 | 2019-06-06 10:07:17 +0200 | [diff] [blame] | 175 | subl $8, %esp |
Arthur Heymans | 59b6542 | 2019-05-23 15:24:30 +0200 | [diff] [blame] | 176 | |
Frans Hendriks | 4e0ec59 | 2019-06-06 10:07:17 +0200 | [diff] [blame] | 177 | /* Push initial timestamp on the stack */ |
Arthur Heymans | 59b6542 | 2019-05-23 15:24:30 +0200 | [diff] [blame] | 178 | movd %mm1, %eax |
| 179 | pushl %eax /* tsc[63:32] */ |
| 180 | movd %mm0, %eax |
| 181 | pushl %eax /* tsc[31:0] */ |
| 182 | |
Lee Leahy | 3dad489 | 2015-05-05 11:14:02 -0700 | [diff] [blame] | 183 | before_romstage: |
Frans Hendriks | 4e0ec59 | 2019-06-06 10:07:17 +0200 | [diff] [blame] | 184 | /* Call bootblock_c_entry(uint64_t base_timestamp) */ |
| 185 | call bootblock_c_entry |
Lee Leahy | 3dad489 | 2015-05-05 11:14:02 -0700 | [diff] [blame] | 186 | |
Frans Hendriks | 4e0ec59 | 2019-06-06 10:07:17 +0200 | [diff] [blame] | 187 | /* Never reached */ |
Lee Leahy | 3dad489 | 2015-05-05 11:14:02 -0700 | [diff] [blame] | 188 | |
| 189 | halt1: |
| 190 | /* |
Lee Leahy | b5ad827 | 2015-04-20 15:29:16 -0700 | [diff] [blame] | 191 | * Failures for postcode 0xBA - failed in fsp_fih_early_find() |
Lee Leahy | 3dad489 | 2015-05-05 11:14:02 -0700 | [diff] [blame] | 192 | * |
| 193 | * Values are: |
| 194 | * 0x01 - FV signature, "_FVH" not present |
| 195 | * 0x02 - FFS GUID not present |
| 196 | * 0x03 - FSP INFO Header not found |
Frans Hendriks | 683e77e | 2019-04-29 13:29:36 +0200 | [diff] [blame] | 197 | * 0x04 - ImageBase does not equal CONFIG_FSP_LOC - Is the FSP rebased |
| 198 | * to a different location, or does it need to be? |
Lee Leahy | 3dad489 | 2015-05-05 11:14:02 -0700 | [diff] [blame] | 199 | * 0x05 - FSP INFO Header signature "FSPH" not found |
| 200 | * 0x06 - FSP Image ID is not the expected ID. |
| 201 | */ |
Lee Leahy | b5ad827 | 2015-04-20 15:29:16 -0700 | [diff] [blame] | 202 | movb $0xBA, %ah |
| 203 | jmp .Lhlt |
Lee Leahy | 3dad489 | 2015-05-05 11:14:02 -0700 | [diff] [blame] | 204 | |
| 205 | halt2: |
| 206 | /* |
| 207 | * Failures for postcode 0xBB - failed in the FSP: |
| 208 | * |
| 209 | * 0x00 - FSP_SUCCESS: Temp RAM was initialized successfully. |
| 210 | * 0x02 - FSP_INVALID_PARAMETER: Input parameters are invalid. |
Lee Leahy | 3dad489 | 2015-05-05 11:14:02 -0700 | [diff] [blame] | 211 | * 0x03 - FSP_UNSUPPORTED: The FSP calling conditions were not met. |
| 212 | * 0x07 - FSP_DEVICE_ERROR: Temp RAM initialization failed |
Frans Hendriks | 683e77e | 2019-04-29 13:29:36 +0200 | [diff] [blame] | 213 | * 0x0E - FSP_NOT_FOUND: No valid microcode was found in the microcode |
| 214 | * region. |
Lee Leahy | 3dad489 | 2015-05-05 11:14:02 -0700 | [diff] [blame] | 215 | * 0x14 - FSP_ALREADY_STARTED: Temp RAM initialization has been invoked |
| 216 | */ |
Lee Leahy | b5ad827 | 2015-04-20 15:29:16 -0700 | [diff] [blame] | 217 | movb $0xBB, %ah |
| 218 | jmp .Lhlt |
| 219 | |
Lee Leahy | 3dad489 | 2015-05-05 11:14:02 -0700 | [diff] [blame] | 220 | .Lhlt: |
Lee Leahy | b5ad827 | 2015-04-20 15:29:16 -0700 | [diff] [blame] | 221 | xchg %al, %ah |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 222 | #if CONFIG(POST_IO) |
Lee Leahy | b5ad827 | 2015-04-20 15:29:16 -0700 | [diff] [blame] | 223 | outb %al, $CONFIG_POST_IO_PORT |
Lee Leahy | 3dad489 | 2015-05-05 11:14:02 -0700 | [diff] [blame] | 224 | #else |
lilacious | 40cb3fe | 2023-06-21 23:24:14 +0200 | [diff] [blame^] | 225 | post_code(POSTCODE_DEAD_CODE) |
Lee Leahy | 3dad489 | 2015-05-05 11:14:02 -0700 | [diff] [blame] | 226 | #endif |
Lee Leahy | b5ad827 | 2015-04-20 15:29:16 -0700 | [diff] [blame] | 227 | movl $LHLT_DELAY, %ecx |
Lee Leahy | 3dad489 | 2015-05-05 11:14:02 -0700 | [diff] [blame] | 228 | .Lhlt_Delay: |
Lee Leahy | b5ad827 | 2015-04-20 15:29:16 -0700 | [diff] [blame] | 229 | outb %al, $0xED |
| 230 | loop .Lhlt_Delay |
| 231 | jmp .Lhlt |
Lee Leahy | 3dad489 | 2015-05-05 11:14:02 -0700 | [diff] [blame] | 232 | |
| 233 | /* |
| 234 | * esp is set to this location so that the call into and return from the FSP |
| 235 | * in find_fsp will work. |
| 236 | */ |
| 237 | .align 4 |
| 238 | fake_fsp_stack: |
Lee Leahy | b5ad827 | 2015-04-20 15:29:16 -0700 | [diff] [blame] | 239 | .long find_fsp_ret |
Lee Leahy | a887492 | 2015-08-26 14:58:29 -0700 | [diff] [blame] | 240 | .long CONFIG_FSP_LOC /* FSP base address */ |
Lee Leahy | 3dad489 | 2015-05-05 11:14:02 -0700 | [diff] [blame] | 241 | |
| 242 | CAR_init_params: |
Arthur Heymans | 12440ce | 2019-10-23 11:30:22 +0200 | [diff] [blame] | 243 | .long fake_microcode /* Microcode Location */ |
| 244 | .long fake_microcode_end - fake_microcode /* Microcode Length */ |
Aaron Durbin | 2524be4 | 2015-10-29 10:43:21 -0500 | [diff] [blame] | 245 | .long 0xFFFFFFFF - CONFIG_ROM_SIZE + 1 /* Firmware Location */ |
Frans Hendriks | 683e77e | 2019-04-29 13:29:36 +0200 | [diff] [blame] | 246 | .long CONFIG_ROM_SIZE /* Firmware Length */ |
Lee Leahy | 3dad489 | 2015-05-05 11:14:02 -0700 | [diff] [blame] | 247 | |
| 248 | CAR_init_stack: |
Lee Leahy | b5ad827 | 2015-04-20 15:29:16 -0700 | [diff] [blame] | 249 | .long CAR_init_done |
| 250 | .long CAR_init_params |
Arthur Heymans | 12440ce | 2019-10-23 11:30:22 +0200 | [diff] [blame] | 251 | |
| 252 | /* coreboot updates microcode itself. FSP still needs a pointer |
| 253 | to something that looks like microcode, so provide it with fake |
| 254 | microcode. */ |
| 255 | fake_microcode: |
| 256 | fake_microcode_header_start: |
| 257 | .long 1 /* Header Version */ |
| 258 | .long 1 /* Microcode revision */ |
| 259 | .long 0x10232019 /* Date: Time of writing 23-10-2019 */ |
| 260 | .long 0x00010ff0 /* Sig: (non existing) Family: 0xf, Model: 0x1f, stepping: 0 */ |
| 261 | .long 0 /* Checksum: not checked by FSP, so won't care */ |
| 262 | .long 1 /* Loader Revision */ |
| 263 | .long 1 /* Processor Flags */ |
| 264 | .long fake_microcode_end - fake_microcode_header_end /* Data Size */ |
| 265 | .long fake_microcode_end - fake_microcode /* Total Size */ |
| 266 | .space 12 /* Reserved */ |
| 267 | fake_microcode_header_end: |
| 268 | .space 0x10 /* 16 bytes of empty data */ |
| 269 | fake_microcode_end: |