Lee Leahy | 3dad489 | 2015-05-05 11:14:02 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
Lee Leahy | 3dad489 | 2015-05-05 11:14:02 -0700 | [diff] [blame] | 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License as published by |
| 6 | * the Free Software Foundation; version 2 of the License. |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | * GNU General Public License for more details. |
Lee Leahy | 3dad489 | 2015-05-05 11:14:02 -0700 | [diff] [blame] | 12 | */ |
| 13 | |
Arthur Heymans | 8256ca0 | 2019-10-21 18:47:46 +0200 | [diff] [blame^] | 14 | #include <cpu/x86/mtrr.h> |
| 15 | #include <cpu/x86/cache.h> |
Frans Hendriks | 4e0ec59 | 2019-06-06 10:07:17 +0200 | [diff] [blame] | 16 | #include <cpu/x86/post_code.h> |
| 17 | |
Lee Leahy | b5ad827 | 2015-04-20 15:29:16 -0700 | [diff] [blame] | 18 | /* |
| 19 | * Replacement for cache_as_ram.inc when using the FSP binary. This code |
| 20 | * locates the FSP binary, initializes the cache as RAM and performs the |
| 21 | * first stage of initialization. Next this code switches the stack from |
| 22 | * the cache to RAM and then disables the cache as RAM. Finally this code |
| 23 | * performs the final stage of initialization. |
| 24 | */ |
| 25 | |
Frans Hendriks | 4e0ec59 | 2019-06-06 10:07:17 +0200 | [diff] [blame] | 26 | #define LHLT_DELAY 0x50000 /* I/O delay between post codes on failure */ |
| 27 | |
| 28 | .global bootblock_pre_c_entry |
| 29 | bootblock_pre_c_entry: |
Lee Leahy | b5ad827 | 2015-04-20 15:29:16 -0700 | [diff] [blame] | 30 | /* |
Kyösti Mälkki | ee2e936 | 2018-12-28 16:06:45 +0200 | [diff] [blame] | 31 | * Per FSP1.1 specs, following registers are preserved: |
| 32 | * EBX, EDI, ESI, EBP, MM0, MM1 |
| 33 | * |
| 34 | * Shift values to release MM2. |
Arthur Heymans | 59b6542 | 2019-05-23 15:24:30 +0200 | [diff] [blame] | 35 | * mm0 -> ebx: BIST value |
Kyösti Mälkki | ee2e936 | 2018-12-28 16:06:45 +0200 | [diff] [blame] | 36 | * mm1 -> mm0: low 32-bits of TSC value |
| 37 | * mm2 -> mm1: high 32-bits of TSC value |
Lee Leahy | b5ad827 | 2015-04-20 15:29:16 -0700 | [diff] [blame] | 38 | */ |
Arthur Heymans | 59b6542 | 2019-05-23 15:24:30 +0200 | [diff] [blame] | 39 | movd %mm0, %ebx |
Kyösti Mälkki | ee2e936 | 2018-12-28 16:06:45 +0200 | [diff] [blame] | 40 | movd %mm1, %eax |
| 41 | movd %eax, %mm0 |
| 42 | movd %mm2, %eax |
| 43 | movd %eax, %mm1 |
| 44 | |
Lee Leahy | 3dad489 | 2015-05-05 11:14:02 -0700 | [diff] [blame] | 45 | cache_as_ram: |
| 46 | post_code(0x20) |
| 47 | |
Arthur Heymans | 8256ca0 | 2019-10-21 18:47:46 +0200 | [diff] [blame^] | 48 | /* Cache the rom and update the microcode */ |
| 49 | cache_rom: |
| 50 | /* Disable cache */ |
| 51 | movl %cr0, %eax |
| 52 | orl $CR0_CacheDisable, %eax |
| 53 | movl %eax, %cr0 |
| 54 | |
| 55 | movl $MTRR_PHYS_BASE(1), %ecx |
| 56 | xorl %edx, %edx |
| 57 | movl $(CACHE_ROM_BASE | MTRR_TYPE_WRPROT), %eax |
| 58 | wrmsr |
| 59 | |
| 60 | movl $MTRR_PHYS_MASK(1), %ecx |
| 61 | rdmsr |
| 62 | movl $(~(CACHE_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax |
| 63 | wrmsr |
| 64 | |
| 65 | /* Enable cache */ |
| 66 | movl %cr0, %eax |
| 67 | andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax |
| 68 | invd |
| 69 | movl %eax, %cr0 |
| 70 | |
| 71 | /* Enable MTRR. */ |
| 72 | movl $MTRR_DEF_TYPE_MSR, %ecx |
| 73 | rdmsr |
| 74 | orl $MTRR_DEF_TYPE_EN, %eax |
| 75 | wrmsr |
| 76 | |
| 77 | /* The Google FSP release for Braswell has broken microcode update |
| 78 | code and FSP needs the installed microcode revision to be non zero. |
| 79 | It is better to have coreboot do it instead of relying on a fragile |
| 80 | blob. */ |
| 81 | update_microcode: |
| 82 | /* put the return address in %esp */ |
| 83 | movl $end_microcode_update, %esp |
| 84 | jmp update_bsp_microcode |
| 85 | end_microcode_update: |
| 86 | |
Lee Leahy | b5ad827 | 2015-04-20 15:29:16 -0700 | [diff] [blame] | 87 | /* |
Lee Leahy | 3dad489 | 2015-05-05 11:14:02 -0700 | [diff] [blame] | 88 | * Find the FSP binary in cbfs. |
| 89 | * Make a fake stack that has the return value back to this code. |
| 90 | */ |
Lee Leahy | b5ad827 | 2015-04-20 15:29:16 -0700 | [diff] [blame] | 91 | lea fake_fsp_stack, %esp |
| 92 | jmp find_fsp |
Lee Leahy | 3dad489 | 2015-05-05 11:14:02 -0700 | [diff] [blame] | 93 | find_fsp_ret: |
| 94 | /* Save the FSP location */ |
Lee Leahy | b5ad827 | 2015-04-20 15:29:16 -0700 | [diff] [blame] | 95 | mov %eax, %ebp |
| 96 | |
| 97 | /* |
| 98 | * Only when a valid FSP binary is found at CONFIG_FSP_LOC is |
| 99 | * the returned FSP_INFO_HEADER structure address above the base |
| 100 | * address of FSP binary specified by the CONFIG_FSP_LOC value. |
| 101 | * All of the error values are in the 0x8xxxxxxx range which are |
| 102 | * below the CONFIG_FSP_LOC value. |
| 103 | */ |
| 104 | cmp $CONFIG_FSP_LOC, %eax |
| 105 | jbe halt1 |
Lee Leahy | 3dad489 | 2015-05-05 11:14:02 -0700 | [diff] [blame] | 106 | |
Duncan Laurie | fb50983 | 2015-11-22 14:53:57 -0800 | [diff] [blame] | 107 | post_code(POST_FSP_TEMP_RAM_INIT) |
Lee Leahy | 3dad489 | 2015-05-05 11:14:02 -0700 | [diff] [blame] | 108 | |
| 109 | /* Calculate entry into FSP */ |
Lee Leahy | b5ad827 | 2015-04-20 15:29:16 -0700 | [diff] [blame] | 110 | mov 0x30(%ebp), %eax /* Load TempRamInitEntry */ |
| 111 | add 0x1c(%ebp), %eax /* add in the offset for FSP */ |
Lee Leahy | 3dad489 | 2015-05-05 11:14:02 -0700 | [diff] [blame] | 112 | |
| 113 | /* |
| 114 | * Pass early init variables on a fake stack (no memory yet) |
| 115 | * as well as the return location |
| 116 | */ |
Lee Leahy | b5ad827 | 2015-04-20 15:29:16 -0700 | [diff] [blame] | 117 | lea CAR_init_stack, %esp |
Lee Leahy | 3dad489 | 2015-05-05 11:14:02 -0700 | [diff] [blame] | 118 | |
| 119 | /* |
Lee Leahy | b5ad827 | 2015-04-20 15:29:16 -0700 | [diff] [blame] | 120 | * BIST value is zero |
| 121 | * eax: TempRamInitApi address |
Arthur Heymans | 59b6542 | 2019-05-23 15:24:30 +0200 | [diff] [blame] | 122 | * ebx: BIST value |
Lee Leahy | b5ad827 | 2015-04-20 15:29:16 -0700 | [diff] [blame] | 123 | * ebp: FSP_INFO_HEADER address |
Lee Leahy | b5ad827 | 2015-04-20 15:29:16 -0700 | [diff] [blame] | 124 | * esi: Not used |
| 125 | * mm0: low 32-bits of TSC value |
| 126 | * mm1: high 32-bits of TSC value |
Lee Leahy | 3dad489 | 2015-05-05 11:14:02 -0700 | [diff] [blame] | 127 | */ |
Lee Leahy | 3dad489 | 2015-05-05 11:14:02 -0700 | [diff] [blame] | 128 | |
Lee Leahy | b5ad827 | 2015-04-20 15:29:16 -0700 | [diff] [blame] | 129 | /* call FSP binary to setup temporary stack */ |
| 130 | jmp *%eax |
| 131 | |
| 132 | CAR_init_done: |
Lee Leahy | b5ad827 | 2015-04-20 15:29:16 -0700 | [diff] [blame] | 133 | |
| 134 | /* |
| 135 | * ebp: FSP_INFO_HEADER address |
Arthur Heymans | 59b6542 | 2019-05-23 15:24:30 +0200 | [diff] [blame] | 136 | * ebx: BIST value |
Lee Leahy | b5ad827 | 2015-04-20 15:29:16 -0700 | [diff] [blame] | 137 | * ecx: Temp RAM base |
| 138 | * edx: Temp RAM top |
Lee Leahy | b5ad827 | 2015-04-20 15:29:16 -0700 | [diff] [blame] | 139 | * mm0: low 32-bits of TSC value |
| 140 | * mm1: high 32-bits of TSC value |
| 141 | */ |
| 142 | |
| 143 | cmp $0, %eax |
| 144 | jne halt2 |
| 145 | |
| 146 | /* Setup bootloader stack */ |
| 147 | movl %edx, %esp |
| 148 | |
Lee Leahy | b5ad827 | 2015-04-20 15:29:16 -0700 | [diff] [blame] | 149 | /* |
| 150 | * ebp: FSP_INFO_HEADER address |
Arthur Heymans | 59b6542 | 2019-05-23 15:24:30 +0200 | [diff] [blame] | 151 | * ebx: BIST value |
Lee Leahy | b5ad827 | 2015-04-20 15:29:16 -0700 | [diff] [blame] | 152 | * ecx: Temp RAM base |
| 153 | * edx: Temp RAM top |
| 154 | * esp: Top of stack in temp RAM |
| 155 | * mm0: low 32-bits of TSC value |
| 156 | * mm1: high 32-bits of TSC value |
Lee Leahy | b5ad827 | 2015-04-20 15:29:16 -0700 | [diff] [blame] | 157 | */ |
| 158 | |
Martin Roth | e18e642 | 2017-06-03 20:03:18 -0600 | [diff] [blame] | 159 | /* coreboot assumes stack/heap region will be zero */ |
Lee Leahy | b5ad827 | 2015-04-20 15:29:16 -0700 | [diff] [blame] | 160 | cld |
| 161 | movl %ecx, %edi |
| 162 | neg %ecx |
Arthur Heymans | 59b6542 | 2019-05-23 15:24:30 +0200 | [diff] [blame] | 163 | /* Clear up to Temp Ram top. */ |
| 164 | add %edx, %ecx |
Lee Leahy | b5ad827 | 2015-04-20 15:29:16 -0700 | [diff] [blame] | 165 | shrl $2, %ecx |
| 166 | xorl %eax, %eax |
| 167 | rep stosl |
| 168 | |
Arthur Heymans | 59b6542 | 2019-05-23 15:24:30 +0200 | [diff] [blame] | 169 | /* Need to align stack to 16 bytes at call instruction. Account for |
| 170 | the pushes below. */ |
| 171 | andl $0xfffffff0, %esp |
Frans Hendriks | 4e0ec59 | 2019-06-06 10:07:17 +0200 | [diff] [blame] | 172 | subl $8, %esp |
Arthur Heymans | 59b6542 | 2019-05-23 15:24:30 +0200 | [diff] [blame] | 173 | |
Frans Hendriks | 4e0ec59 | 2019-06-06 10:07:17 +0200 | [diff] [blame] | 174 | /* Push initial timestamp on the stack */ |
Arthur Heymans | 59b6542 | 2019-05-23 15:24:30 +0200 | [diff] [blame] | 175 | movd %mm1, %eax |
| 176 | pushl %eax /* tsc[63:32] */ |
| 177 | movd %mm0, %eax |
| 178 | pushl %eax /* tsc[31:0] */ |
| 179 | |
Lee Leahy | 3dad489 | 2015-05-05 11:14:02 -0700 | [diff] [blame] | 180 | before_romstage: |
Subrata Banik | fbdc719 | 2016-01-19 19:19:15 +0530 | [diff] [blame] | 181 | post_code(0x2A) |
Lee Leahy | 3dad489 | 2015-05-05 11:14:02 -0700 | [diff] [blame] | 182 | |
Frans Hendriks | 4e0ec59 | 2019-06-06 10:07:17 +0200 | [diff] [blame] | 183 | /* Call bootblock_c_entry(uint64_t base_timestamp) */ |
| 184 | call bootblock_c_entry |
Lee Leahy | 3dad489 | 2015-05-05 11:14:02 -0700 | [diff] [blame] | 185 | |
Frans Hendriks | 4e0ec59 | 2019-06-06 10:07:17 +0200 | [diff] [blame] | 186 | /* Never reached */ |
Lee Leahy | 3dad489 | 2015-05-05 11:14:02 -0700 | [diff] [blame] | 187 | |
| 188 | halt1: |
| 189 | /* |
Lee Leahy | b5ad827 | 2015-04-20 15:29:16 -0700 | [diff] [blame] | 190 | * Failures for postcode 0xBA - failed in fsp_fih_early_find() |
Lee Leahy | 3dad489 | 2015-05-05 11:14:02 -0700 | [diff] [blame] | 191 | * |
| 192 | * Values are: |
| 193 | * 0x01 - FV signature, "_FVH" not present |
| 194 | * 0x02 - FFS GUID not present |
| 195 | * 0x03 - FSP INFO Header not found |
Frans Hendriks | 683e77e | 2019-04-29 13:29:36 +0200 | [diff] [blame] | 196 | * 0x04 - ImageBase does not equal CONFIG_FSP_LOC - Is the FSP rebased |
| 197 | * to a different location, or does it need to be? |
Lee Leahy | 3dad489 | 2015-05-05 11:14:02 -0700 | [diff] [blame] | 198 | * 0x05 - FSP INFO Header signature "FSPH" not found |
| 199 | * 0x06 - FSP Image ID is not the expected ID. |
| 200 | */ |
Lee Leahy | b5ad827 | 2015-04-20 15:29:16 -0700 | [diff] [blame] | 201 | movb $0xBA, %ah |
| 202 | jmp .Lhlt |
Lee Leahy | 3dad489 | 2015-05-05 11:14:02 -0700 | [diff] [blame] | 203 | |
| 204 | halt2: |
| 205 | /* |
| 206 | * Failures for postcode 0xBB - failed in the FSP: |
| 207 | * |
| 208 | * 0x00 - FSP_SUCCESS: Temp RAM was initialized successfully. |
| 209 | * 0x02 - FSP_INVALID_PARAMETER: Input parameters are invalid. |
Lee Leahy | 3dad489 | 2015-05-05 11:14:02 -0700 | [diff] [blame] | 210 | * 0x03 - FSP_UNSUPPORTED: The FSP calling conditions were not met. |
| 211 | * 0x07 - FSP_DEVICE_ERROR: Temp RAM initialization failed |
Frans Hendriks | 683e77e | 2019-04-29 13:29:36 +0200 | [diff] [blame] | 212 | * 0x0E - FSP_NOT_FOUND: No valid microcode was found in the microcode |
| 213 | * region. |
Lee Leahy | 3dad489 | 2015-05-05 11:14:02 -0700 | [diff] [blame] | 214 | * 0x14 - FSP_ALREADY_STARTED: Temp RAM initialization has been invoked |
| 215 | */ |
Lee Leahy | b5ad827 | 2015-04-20 15:29:16 -0700 | [diff] [blame] | 216 | movb $0xBB, %ah |
| 217 | jmp .Lhlt |
| 218 | |
Lee Leahy | 3dad489 | 2015-05-05 11:14:02 -0700 | [diff] [blame] | 219 | .Lhlt: |
Lee Leahy | b5ad827 | 2015-04-20 15:29:16 -0700 | [diff] [blame] | 220 | xchg %al, %ah |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 221 | #if CONFIG(POST_IO) |
Lee Leahy | b5ad827 | 2015-04-20 15:29:16 -0700 | [diff] [blame] | 222 | outb %al, $CONFIG_POST_IO_PORT |
Lee Leahy | 3dad489 | 2015-05-05 11:14:02 -0700 | [diff] [blame] | 223 | #else |
| 224 | post_code(POST_DEAD_CODE) |
| 225 | #endif |
Lee Leahy | b5ad827 | 2015-04-20 15:29:16 -0700 | [diff] [blame] | 226 | movl $LHLT_DELAY, %ecx |
Lee Leahy | 3dad489 | 2015-05-05 11:14:02 -0700 | [diff] [blame] | 227 | .Lhlt_Delay: |
Lee Leahy | b5ad827 | 2015-04-20 15:29:16 -0700 | [diff] [blame] | 228 | outb %al, $0xED |
| 229 | loop .Lhlt_Delay |
| 230 | jmp .Lhlt |
Lee Leahy | 3dad489 | 2015-05-05 11:14:02 -0700 | [diff] [blame] | 231 | |
| 232 | /* |
| 233 | * esp is set to this location so that the call into and return from the FSP |
| 234 | * in find_fsp will work. |
| 235 | */ |
| 236 | .align 4 |
| 237 | fake_fsp_stack: |
Lee Leahy | b5ad827 | 2015-04-20 15:29:16 -0700 | [diff] [blame] | 238 | .long find_fsp_ret |
Lee Leahy | a887492 | 2015-08-26 14:58:29 -0700 | [diff] [blame] | 239 | .long CONFIG_FSP_LOC /* FSP base address */ |
Lee Leahy | 3dad489 | 2015-05-05 11:14:02 -0700 | [diff] [blame] | 240 | |
| 241 | CAR_init_params: |
Lee Leahy | b5ad827 | 2015-04-20 15:29:16 -0700 | [diff] [blame] | 242 | .long CONFIG_CPU_MICROCODE_CBFS_LOC /* Microcode Location */ |
| 243 | .long CONFIG_CPU_MICROCODE_CBFS_LEN /* Microcode Length */ |
Aaron Durbin | 2524be4 | 2015-10-29 10:43:21 -0500 | [diff] [blame] | 244 | .long 0xFFFFFFFF - CONFIG_ROM_SIZE + 1 /* Firmware Location */ |
Frans Hendriks | 683e77e | 2019-04-29 13:29:36 +0200 | [diff] [blame] | 245 | .long CONFIG_ROM_SIZE /* Firmware Length */ |
Lee Leahy | 3dad489 | 2015-05-05 11:14:02 -0700 | [diff] [blame] | 246 | |
| 247 | CAR_init_stack: |
Lee Leahy | b5ad827 | 2015-04-20 15:29:16 -0700 | [diff] [blame] | 248 | .long CAR_init_done |
| 249 | .long CAR_init_params |