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review.coreboot.org / coreboot / 40cb3fe94dacfba0b146aae2be9c03c0a0ddb691 / src / drivers / intel / fsp1_1 / cache_as_ram.S
  1. 40cb3fe commonlib/console/post_code.h: Change post code prefix to POSTCODE by lilacious · 1 year, 1 month ago
  2. 0d34a50 src: Move POST_BOOTBLOCK_CAR to common postcodes and use it by Martin Roth · 1 year, 6 months ago
  3. d58599d drivers/fsp: Rewrite post code hex values in lowercase by Sean Rhodes · 2 years, 8 months ago
  4. 7522a8f arch/x86: Move prologue to .init section by Kyösti Mälkki · 3 years, 8 months ago
  5. 7590c37 drivers/intel/fsp1_1/cache_as_ram.S: Correct comment by Frans Hendriks · 3 years, 8 months ago
  6. c022a79 drivers/intel/fsp1_1: Add function to report FSP-T output by Frans Hendriks · 3 years, 8 months ago
  7. 335eb12 src/drivers/intel/fsp1_1/cache_as_ram.S: Clear _bss area only by Frans Hendriks · 3 years, 8 months ago
  8. 7ba970a drivers/intel/fsp1_1/cache_as_ram.S: Use _car_stack area for stack by Frans Hendriks · 3 years, 8 months ago
  9. 6b5bc77 treewide: Remove "this file is part of" lines by Patrick Georgi · 4 years, 2 months ago
  10. 8a3453f src/drivers: Use SPDX for GPL-2.0-only files by Angel Pons · 4 years, 3 months ago
  11. 12440ce drivers/intel/fsp1_1: Fake microcode update to make FSP happy by Arthur Heymans · 4 years, 9 months ago
  12. 8256ca0 soc/intel/braswell: Update microcode before FSP by Arthur Heymans · 4 years, 9 months ago
  13. cddd600 AUTHORS: Move src/drivers/[a*-i*] copyrights into AUTHORS file by Martin Roth · 4 years, 10 months ago
  14. 4e0ec59 {drivers,soc/intel/braswell}: Implement C_ENVIRONMENT_BOOTBLOCK support by Frans Hendriks · 5 years ago[Renamed (93%) from src/drivers/intel/fsp1_1/cache_as_ram.inc]
  15. 59b6542 soc/intel/braswell: Use common cpu/intel/car code by Arthur Heymans · 5 years ago
  16. be291e8 soc/intel/fsp1.1: Implement postcar stage by Arthur Heymans · 6 years ago
  17. 683e77e drivers/intel/fsp1_1/cache_as_ram.inc: Reduce max line length to 80 by Frans Hendriks · 5 years ago
  18. cd49cce coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX) by Julius Werner · 5 years ago
  19. 5c29daa buildsystem: Promote rules.h to default include by Kyösti Mälkki · 8 years ago
  20. ee2e936 arch/x86: Unify bootblock MMX register usage by Kyösti Mälkki · 6 years ago
  21. 613da18 drivers/intel/fsp1_1/cache_as_ram.inc: Dont include soc/car_setup.S by Frans Hendriks · 6 years ago
  22. 0d8f1da src/drivers: Get rid of whitespace before tab by Elyes HAOUAS · 6 years ago
  23. e18e642 src: change coreboot to lowercase by Martin Roth · 7 years ago
  24. 7753731 src/drivers: Capitalize CPU, RAM and ACPI by Elyes HAOUAS · 8 years ago
  25. fbdc719 intel/skylake: Implement native Cache-as-RAM (CAR) by Subrata Banik · 8 years ago
  26. fb50983 intel/fsp: Add post codes for FSP phases by Duncan Laurie · 9 years ago
  27. 2524be4 fsp1_1: pass ROM_SIZE to FSP for cacheable RO region by Aaron Durbin · 9 years ago
  28. a73b931 tree: drop last paragraph of GPL copyright header by Patrick Georgi · 9 years ago
  29. 909c512 fsp1_1: add verstage support by Aaron Durbin · 9 years ago
  30. e6af4be intel fsp1_1: prepare for romstage vboot verification split by Aaron Durbin · 9 years ago
  31. e1ecfc9 intel: update common and FSP cache-as-ram parameters by Aaron Durbin · 9 years ago
  32. a887492 FSP: Pass FSP image base address to find_fsp by Lee Leahy · 9 years ago
  33. 681012a drivers/intel/fsp_1_1: Remove useless #ifndef/#error pairs by Alexandru Gagniuc · 9 years ago
  34. 4a8c19c FSP 1.1: Bring source up-to-date by Lee Leahy · 9 years ago
  35. b5ad827 drivers/intel: Update FSP 1.1 Driver by Lee Leahy · 9 years ago
  36. b890a12 Remove address from GPLv2 headers by Patrick Georgi · 9 years ago
  37. 3dad489 FSP 1.1 Comparison Base by Lee Leahy · 9 years ago